JPH0519701A - Production of plane display device - Google Patents

Production of plane display device

Info

Publication number
JPH0519701A
JPH0519701A JP19745691A JP19745691A JPH0519701A JP H0519701 A JPH0519701 A JP H0519701A JP 19745691 A JP19745691 A JP 19745691A JP 19745691 A JP19745691 A JP 19745691A JP H0519701 A JPH0519701 A JP H0519701A
Authority
JP
Japan
Prior art keywords
paste
display device
polymer
layer
polymer type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19745691A
Other languages
Japanese (ja)
Inventor
Yuichi Hatano
祐一 波多野
Hayaji Kasai
隼次 笠井
Eiji Ito
栄二 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jeco Corp
Original Assignee
Jeco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jeco Corp filed Critical Jeco Corp
Priority to JP19745691A priority Critical patent/JPH0519701A/en
Publication of JPH0519701A publication Critical patent/JPH0519701A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To form multilayered wirings with simple process at a low cost. CONSTITUTION:A VFD 1 is constituted by integrally forming a pair of glass substrates. A surface oxide film is formed on the front surface of the rear surface glass substrate 1b. A coupling agent is applied on this surface oxide film. polymer type conductor paste, polymer type insulating paste, polymer type conductor paste, and polymer type overcoat insulating paste are respectively printed thereon and are cured to form the multilayered wirings of conductor patterns 2 of the 1st layer, the interlayer insulating layer 3, the conductor patterns 4 of the 2nd layer, and the overcoat insulating 5. Surface packaging parts 7 are mounted in such multilayered wirings and are joined by solder reflow.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、平面ディスプレイ装置
の製造方法に係わり、特に平面ディスプレイ部分とその
駆動回路部分とを同一基板上に形成した平面ディスプレ
イ装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flat panel display device, and more particularly to a method of manufacturing a flat panel display device in which a flat panel display portion and a driving circuit portion thereof are formed on the same substrate.

【0002】[0002]

【従来の技術】従来、この種の平面ディスプレイ装置の
製造方法は、ガラス基板上にカップリング剤を介してポ
リマー型Cuペーストにより電子回路を形成する方法が
例えば特開昭60−68370号公報により提案されて
おり、また、平面ディスプレイ装置の裏面側に電子回路
を形成し、電子部品を実装する方法については、例えば
実開昭63−98580号公報により提案されている。
2. Description of the Related Art Conventionally, as a method of manufacturing a flat display device of this type, a method of forming an electronic circuit on a glass substrate with a polymer type Cu paste via a coupling agent is disclosed in, for example, Japanese Patent Laid-Open No. 60-68370. A method of forming an electronic circuit on the back surface side of a flat display device and mounting an electronic component has been proposed, for example, in Japanese Utility Model Laid-Open No. 63-98580.

【0003】すなわちガラス基板の大きさに余裕があれ
ば、何等問題はないが、例えば現在自動車時計用として
使用されているVFD(寸法48.2×20.5mm)
のガラス基板の裏面にポリマー型Cuペーストによる回
路形成を行い、QFP,水晶等の表面実装用電子部品を
配置することは、電子部品の表面積のみで約50%程度
占有することから、スペース的に困難である。
That is, if the size of the glass substrate is large, there is no problem. For example, a VFD (dimension 48.2 × 20.5 mm) currently used for automobile timepieces.
By forming a circuit with polymer type Cu paste on the back surface of the glass substrate and arranging surface mounting electronic components such as QFP and crystal, the surface area of the electronic components alone occupies about 50%. Have difficulty.

【0004】このような問題を解決する手段として多層
化回路が考えられる。近年、LCDの駆動用ICをチッ
プオングラスで搭載する方法等で見られるようにITO
等の薄膜導体にNiメッキを施した配線上にポリイミド
等の樹脂により層間絶縁層を形成し、この層間絶縁層を
フォトリソグラフィ工程によりパターンニングし、VI
Aホールを形成する。この上部にITO等の薄膜導体回
路をパターンニング形成し、さらにこれにNiメッキを
施すという方法が採用されている(図4参照)。
A multi-layer circuit is conceivable as a means for solving such a problem. In recent years, ITO can be seen as a method of mounting a driving IC for an LCD on a chip-on-glass.
A thin film conductor such as Ni is plated with Ni to form an interlayer insulating layer of a resin such as polyimide, and the interlayer insulating layer is patterned by a photolithography process.
Form hole A. A method is employed in which a thin film conductor circuit such as ITO is formed on the upper portion of this by patterning, and further Ni plating is applied to this (see FIG. 4).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな方法によると、多層化回路の形成に3回のフォトリ
ソグラフィ工程,成膜工程を経て形成されるので、工程
的に複雑となるとともに設備も大規模になり、材料も高
価となるという問題があった。
However, according to such a method, since the photolithography process and the film forming process are performed three times to form the multilayer circuit, the process becomes complicated and the equipment is also required. There has been a problem that the scale becomes large and the material becomes expensive.

【0006】[0006]

【課題を解決するための手段】このような課題を解決す
るために本発明は、一対のガラス基板を一体的に成して
平面ディスプレイを構成するとともにこのガラス基板の
一方の表面に表面酸化膜を形成し、この表面酸化膜上に
カップリング剤を塗布し、ポリマー型導体ペースト,ポ
リマー型絶縁ペースト,ポリマー型導体ペースト,ポリ
マー型オーバーコート絶縁ペーストをそれぞれ印刷し、
焼成して多層化配線を形成し、この多層化配線上に表面
実装部品を載置し、はんだリフローを行って接合するよ
うにしたものである。
In order to solve such a problem, the present invention constitutes a flat display by integrally forming a pair of glass substrates and has a surface oxide film on one surface of the glass substrate. Is formed, a coupling agent is applied on the surface oxide film, and a polymer-type conductor paste, a polymer-type insulating paste, a polymer-type conductor paste, and a polymer-type overcoat insulating paste are printed,
The multilayer wiring is formed by firing, the surface mount component is placed on the multilayer wiring, and solder reflow is performed to join them.

【0007】[0007]

【作用】本発明においては、ポリマー型導体ペースト,
ポリマー型絶縁ペースト,ポリマー型導体ペースト,ポ
リマー型オーバーコート絶縁ペーストをそれぞれ印刷し
て硬化する工程で多層化配線が形成されるので、フォト
リソグラフィ工程,成膜工程等が不要となり、簡単な工
程が簡素化される。
In the present invention, the polymer-type conductor paste,
Since the multi-layered wiring is formed in the process of printing and curing the polymer type insulating paste, the polymer type conductor paste, and the polymer type overcoat insulating paste, the photolithography process, the film forming process, etc. are unnecessary, and a simple process is possible. To be simplified.

【0008】[0008]

【実施例】以下、図面を用いて本発明の実施例を詳細に
説明する。図1は本発明による平面ディスプレイ装置の
製造方法を蛍光表示管(VFD)の製造方法に適用した
一実施例を説明する要部断面図である。同図において、
まず、VFD1を構成する一対のガラス基板の表面ガラ
ス基板1aおよび裏面ガラス基板1bの表面を洗浄し、
乾燥した後、この裏面ガラス基板1bからのアルカリ溶
出防止膜としてスパッタリング等によりSiO2膜を2
00〜300μm程度の厚さに形成する。次にこの裏面
ガラス基板1bの表面にエポキシシラン系のカップリン
グ剤をスピンコートした後、Cu,Ag混合のポリマー
型導体ペースト(三井金属鉱業製:S−5300,アサ
ヒ化学研究所製:LS−005P)をスクリーン印刷
し、焼成して硬化(焼成温度150℃〜180℃)し、
図2(a)に示すような第1層目の導体パターン2を形
成する。次にこの導体パターン2上にポリマー型絶縁ペ
ースト(アサヒ化学研究所製:CR−22G)をスクリ
ーン印刷し、上記同様の焼成温度で焼成して硬化する工
程を2〜3回繰り返し行って図2(b)に示すようなパ
ターン形状の層間絶縁層3を形成する。次にこの層間絶
縁層3上にCu混合のポリマー型導体ペースト(三井金
属製:S−5300)を第1層目と同様にスクリーン印
刷し、上記同様の焼成温度で焼成して硬化し、図2
(c)に示すような第2層目の導体パターン4を形成す
る。この場合、層間絶縁層3のホール部分を全て埋める
ように位置合わせを正確に行う必要がある。次にこの導
体パターン4上にオーバーコート膜としてポリマー型絶
縁ペースト(アサヒ化学研究所製:CR−22G,CR
−30G)をスクリーン印刷し、上記同様の焼成温度で
焼成して硬化する工程を2回繰り返し行って図2(d)
に示すようなはんだ付けランドパターン5aを有するオ
ーバーコート絶縁層5を形成する。次にこのオーバーコ
ート絶縁層5のランドパターン5a上にクリームはんだ
6を印刷法または塗布法により付着させ、チップマウン
タによりICを始め表面実装部品7を全て載置し、VF
D1のリード部も折り曲げてクリームはんだ6と接触さ
せ、一括リフローによってはんだ付けを行い、VFD1
の裏面ガラス基板1b上に高密度な駆動回路部を搭載し
た一体型平面ディスプレイ装置を製作する。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of an essential part for explaining an embodiment in which a method for manufacturing a flat panel display device according to the present invention is applied to a method for manufacturing a fluorescent display (VFD). In the figure,
First, the front surfaces of the front glass substrate 1a and the back glass substrate 1b of the pair of glass substrates constituting the VFD 1 are washed,
After drying, a SiO 2 film is sputtered as an alkali elution preventing film from the back glass substrate 1b by sputtering or the like.
It is formed to a thickness of about 00 to 300 μm. Next, an epoxysilane coupling agent was spin-coated on the surface of the back glass substrate 1b, and then a Cu-Ag mixed polymer-type conductor paste (M-5, S-5300, manufactured by Asahi Chemical Laboratory: LS-) was used. 005P) is screen-printed, baked and cured (baking temperature 150 ° C. to 180 ° C.),
The conductor pattern 2 of the first layer as shown in FIG. 2A is formed. Next, a step of screen-printing a polymer-type insulating paste (CR-22G, manufactured by Asahi Chemical Laboratory) on the conductor pattern 2 and firing and curing at the same firing temperature as above is repeated 2 to 3 times, and FIG. An interlayer insulating layer 3 having a pattern shape as shown in (b) is formed. Next, a Cu-containing polymer-type conductor paste (Mitsui Kinzoku: S-5300) was screen-printed on the interlayer insulating layer 3 in the same manner as in the first layer, and was fired and cured at the same firing temperature as above. Two
The conductor pattern 4 of the second layer as shown in (c) is formed. In this case, it is necessary to perform the alignment accurately so as to fill all the hole portions of the interlayer insulating layer 3. Next, a polymer type insulating paste (made by Asahi Chemical Laboratory: CR-22G, CR as an overcoat film is formed on the conductor pattern 4.
-30G) is screen-printed and baked at the same baking temperature as above to be cured twice.
An overcoat insulating layer 5 having a soldering land pattern 5a as shown in is formed. Next, the cream solder 6 is attached onto the land pattern 5a of the overcoat insulating layer 5 by a printing method or a coating method, and all the surface mounting components 7 including the IC are mounted by a chip mounter and VF is applied.
The lead portion of D1 is also bent and brought into contact with the cream solder 6, and soldering is performed by batch reflow.
An integrated flat display device in which a high-density drive circuit unit is mounted on the back glass substrate 1b of 1 is manufactured.

【0009】このような方法によれば、第1層の導体パ
ターン2−層間絶縁層3−第2の層導体パターン4−ラ
ンドパターン5をそれぞれスクリーン印刷し、焼成して
硬化する簡単な工程で高密度な配線回路を形成すること
ができる。
According to such a method, the first-layer conductor pattern 2-interlayer insulating layer 3-second layer conductor pattern 4-land pattern 5 are respectively screen-printed, followed by a simple step of baking and curing. A high-density wiring circuit can be formed.

【0010】なお、図3は図1に示す平面ディスプレイ
装置の製造方法のフローチャートを示したものである。
FIG. 3 is a flow chart of a method of manufacturing the flat panel display device shown in FIG.

【0011】なお、前述した実施例においては、VFD
を搭載した平面ディスプレイ装置について説明したが、
本発明はこれに限定されるものではなく、ECD,E
L,PDP,LCD等を搭載した平面ディスプレイ装置
に適用しても同様な工程により裏面ガラス基板上に高密
度な駆動回路を形成できることは勿論である。
In the embodiment described above, the VFD
I explained the flat display device equipped with
The present invention is not limited to this, and ECD, E
Even if it is applied to a flat display device having L, PDP, LCD, etc., it is needless to say that a high-density drive circuit can be formed on the back glass substrate by the same process.

【0012】[0012]

【発明の効果】以上説明したように本発明によれば、第
1の層ポリマー型導体ペースト,ポリマー型絶縁ペース
ト,第2の層ポリマー型導体ペースト,ポリマー型オー
バーコート絶縁ペーストを印刷し、硬化する工程によっ
て多層化配線を形成するようにしたことにより、従来の
フォトリソグラフィ工程を含んだ複雑な薄膜の多層構造
に比べて工程が簡単となり、材料的,設備的にも厚膜多
層方式によるコストメリットが大である。また、導体ペ
ースト,絶縁ペースト等の全ての厚膜材料をポリマー系
ペーストで処理するすることにより、サーメット系導体
ペースト,低融点ガラスペーストの焼成温度(400℃
〜500℃)に比べ極めて低い温度(150℃〜180
℃)で硬化でき、ディスプレイ装置への熱的影響(熱応
力歪,酸化等)が少なく、信頼性の高い高密度実装一体
化平面ディスプレイ装置が得られる。さらに駆動回路部
をディスプレイ装置と一体的に形成するため、小型,薄
形,軽量化が図れる等の極めて優れた効果が得られる。
As described above, according to the present invention, the first layer polymer type conductive paste, the polymer type insulating paste, the second layer polymer type conductive paste, and the polymer type overcoat insulating paste are printed and cured. By forming the multi-layered wiring by the process described above, the process is simpler than the conventional thin film multi-layer structure including the photolithography process, and the cost of the thick film multi-layer method is improved in terms of material and equipment. The merits are great. Further, by treating all thick film materials such as conductor paste and insulating paste with polymer paste, the firing temperature of cermet conductor paste and low melting point glass paste (400 ° C.
-500 ° C), extremely low temperature (150 ° C-180 ° C)
It is possible to obtain a highly reliable, high-density packaging integrated flat display device that can be cured at (° C.) and has little thermal influence (thermal stress strain, oxidation, etc.) on the display device. Further, since the drive circuit portion is formed integrally with the display device, it is possible to obtain extremely excellent effects such as reduction in size, thickness and weight.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による平面ディスプレイ装置の製造方法
の一実施例を説明するVFDの要部拡大断面図である。
FIG. 1 is an enlarged cross-sectional view of a main part of a VFD for explaining an embodiment of a method of manufacturing a flat panel display device according to the present invention.

【図2】図1の各種の積層パターンを示す平面図であ
る。
FIG. 2 is a plan view showing various laminated patterns of FIG.

【図3】図1の平面ディスプレイ装置の製造方法のフロ
ーチャートを示す図である。
FIG. 3 is a diagram showing a flowchart of a method for manufacturing the flat panel display device of FIG.

【図4】従来の平面ディスプレイ装置の製造方法のフロ
ーチャートを示す図である。
FIG. 4 is a diagram showing a flowchart of a conventional method for manufacturing a flat panel display device.

【符号の説明】[Explanation of symbols]

1 VFD 1a 表面ガラス基板 1b 裏面ガラス基板 2 導体パターン 3 層間絶縁層 4 導体パターン 5 オーバーコート絶縁層 5a ランドパターン 6 はんだ 7 表面実装部品 1 VFD 1a Front glass substrate 1b Back glass substrate 2 Conductor pattern 3 Interlayer insulating layer 4 Conductor pattern 5 Overcoat insulating layer 5a Land pattern 6 Solder 7 Surface mount component

Claims (1)

【特許請求の範囲】 【請求項1】 一対のガラス基板を一体的に成して平面
ディスプレイ装置を構成するとともにこのガラス基板の
一方の表面に表面酸化膜を形成し、この表面酸化膜上に
カップリング剤を塗布し、第1層のポリマー型導体ペー
スト,ポリマー型層間絶縁ペースト,第2層のポリマー
型導体ペースト,ポリマーオーバーコート絶縁ペースト
をそれぞれ印刷し、硬化して多層化配線を形成し、この
多層化配線上に表面実装部品を載置し、半田リフローを
行って接合することを特徴とした平面ディスプレイ装置
の製造方法。
Claim: What is claimed is: 1. A flat display device is formed by integrally forming a pair of glass substrates, a surface oxide film is formed on one surface of the glass substrate, and the surface oxide film is formed on the surface oxide film. Coupling agent is applied, and the first-layer polymer-type conductor paste, polymer-type interlayer insulation paste, second-layer polymer-type conductor paste, and polymer-overcoat insulation paste are printed and cured to form multilayer wiring. A method for manufacturing a flat display device, characterized in that a surface mount component is placed on the multilayer wiring, and solder reflow is performed for bonding.
JP19745691A 1991-07-12 1991-07-12 Production of plane display device Pending JPH0519701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19745691A JPH0519701A (en) 1991-07-12 1991-07-12 Production of plane display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19745691A JPH0519701A (en) 1991-07-12 1991-07-12 Production of plane display device

Publications (1)

Publication Number Publication Date
JPH0519701A true JPH0519701A (en) 1993-01-29

Family

ID=16374816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19745691A Pending JPH0519701A (en) 1991-07-12 1991-07-12 Production of plane display device

Country Status (1)

Country Link
JP (1) JPH0519701A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8722288B2 (en) 2009-11-06 2014-05-13 Hodogaya Chemical Co., Ltd. Diphenylnaphthylamine derivatives
US8809543B2 (en) 2010-09-14 2014-08-19 Ricoh Company, Ltd. Electrophotographic photoreceptor, electrophotographic image forming method, electrophotographic image forming apparatus, and process cartridge for electrophotographic image forming apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8722288B2 (en) 2009-11-06 2014-05-13 Hodogaya Chemical Co., Ltd. Diphenylnaphthylamine derivatives
US8809543B2 (en) 2010-09-14 2014-08-19 Ricoh Company, Ltd. Electrophotographic photoreceptor, electrophotographic image forming method, electrophotographic image forming apparatus, and process cartridge for electrophotographic image forming apparatus

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