JPH0519295A - Nonlinear resistance element - Google Patents
Nonlinear resistance elementInfo
- Publication number
- JPH0519295A JPH0519295A JP3172499A JP17249991A JPH0519295A JP H0519295 A JPH0519295 A JP H0519295A JP 3172499 A JP3172499 A JP 3172499A JP 17249991 A JP17249991 A JP 17249991A JP H0519295 A JPH0519295 A JP H0519295A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- layer
- phosphorus
- linear resistance
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＬＣＤ等の表示デバイス
のアクティブマトリクス駆動に使用できる非線形抵抗素
子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-linear resistance element which can be used for active matrix driving of a display device such as an LCD.
【０００２】[0002]
【従来の技術】液晶ディスプレイ等の表示デバイスにお
いて、高精細度な画面を得るためには走査線数を増やし
た高密度なマトリクス構成が必要である。このようなマ
トリクスを有効に駆動させるため、各画素にスイッチン
グ素子を取り付けたアクティブマトリクス駆動方式が注
目されている。2. Description of the Related Art In a display device such as a liquid crystal display, in order to obtain a high-definition screen, a high-density matrix structure with an increased number of scanning lines is required. In order to drive such a matrix effectively, an active matrix drive system in which a switching element is attached to each pixel is drawing attention.
【０００３】このアクティブマトリクス駆動に使用され
るスイッチング素子として、通常、薄膜トランジスタ
（ＴＦＴ）を代表とした３端子型素子と、ＭＩＭ（Ｍｅ
ｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ）を代表とし
た２端子型素子が一般的である。２端子型素子は３端子
型素子に比べて構造が簡単で、製造しやすいため、大画
面用、そして低コスト化を実現するスイッチング素子と
して注目されている。As a switching element used for this active matrix driving, a three-terminal type element represented by a thin film transistor (TFT) and an MIM (Me) are usually used.
A two-terminal element represented by tal-insulator-metal) is generally used. The two-terminal element has a simpler structure and is easier to manufacture than the three-terminal element, and therefore has attracted attention as a switching element for a large screen and realizing cost reduction.
【０００４】図７は従来のＭＩＭ素子を液晶ディスプレ
イのスイッチング素子に適用した場合の断面構成の一例
を示す。第一電極層−非線形抵抗層（ここでは絶縁体
層）−第二電極層なる構成であり、具体的には特開昭61
-260219号公報に示されるように絶縁性基板71上にＣｒ
より成る第一電極層72の上にシリコン窒化物より成る絶
縁体層73を形成し、その上に例えばＣｒより成る第二電
極層74を形成してスイッチング素子を構成し、第二電極
層74をＩＴＯより成る透明画素電極層78に接続する。第
一電極層72と第二電極層74の間に電界を印加することに
より、絶縁体層73の中のトラップを介して電子がトンネ
ル現象により伝導する。その結果、Ｖ−Ｉ特性に非線形
性が現れ、アクティブマトリクス駆動に用いることがで
きる。FIG. 7 shows an example of a sectional structure when a conventional MIM element is applied to a switching element of a liquid crystal display. The first electrode layer-non-linear resistance layer (insulator layer in this case) -second electrode layer is used.
As shown in Japanese Patent Laid-Open No. 260219, Cr is deposited on the insulating substrate 71.
The insulating layer 73 made of silicon nitride is formed on the first electrode layer 72 made of, and the second electrode layer 74 made of, for example, Cr is formed thereon to form a switching element. Is connected to the transparent pixel electrode layer 78 made of ITO. By applying an electric field between the first electrode layer 72 and the second electrode layer 74, electrons are conducted by the tunnel phenomenon through the traps in the insulator layer 73. As a result, non-linearity appears in the VI characteristic, and it can be used for active matrix driving.
【０００５】[0005]
【発明が解決しようとする課題】非線形抵抗素子の性能
として、低電圧駆動を実現するため閾値電圧が余り高く
なく、表示品質の点でＯＮ／ＯＦＦ比が大きいことが要
求される。しかし、従来のＭＩＭでは閾値電圧が１６Ｖ
と比較的高く、ＨＤＴＶ等の高精細ディスプレイに適用
するためにはさらに大きなＯＮ／ＯＦＦ比が要求され
る。As the performance of the non-linear resistance element, it is required that the threshold voltage is not so high in order to realize low voltage driving and the ON / OFF ratio is large in view of display quality. However, in the conventional MIM, the threshold voltage is 16V.
Is relatively high, and a larger ON / OFF ratio is required for application to high-definition displays such as HDTV.
【０００６】本発明は、上記従来の問題点に鑑み成され
たものであり、Ｖ−Ｉ特性において閾値電圧を低減させ
るとともに、ＯＮ／ＯＦＦ比の高い非線形性を実現する
非線形抵抗素子を提供することを目的とする。The present invention has been made in view of the above-mentioned conventional problems, and provides a non-linear resistance element that reduces the threshold voltage in the VI characteristic and realizes a high ON / OFF ratio non-linearity. The purpose is to
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明の非線形抵抗素子は、絶縁性基板の上に第一
電極層、非線形抵抗層、第二電極層を順次積層して成る
非線形抵抗素子であって、前記非線形抵抗層はシリコン
酸化物、シリコン窒化物、シリコン炭化物のうち少なく
とも１種にリンＰをド−プして非線形抵抗素子を構成す
るものである。In order to solve the above-mentioned problems, a nonlinear resistance element of the present invention comprises a first electrode layer, a nonlinear resistance layer and a second electrode layer which are sequentially laminated on an insulating substrate. A non-linear resistance element, wherein the non-linear resistance layer is formed by doping phosphorus P into at least one of silicon oxide, silicon nitride and silicon carbide.
【０００８】あるいは、絶縁性基板上に形成した第一電
極層の上にリンＰをド−プしたシリコンより成る第一半
導体層、さらにシリコン酸化物、シリコン窒化物、シリ
コン炭化物のうち少なくとも１種にリンＰをド−プした
非線形抵抗層、リンＰをド−プしたシリコンより成る第
二半導体層、第二電極層を順次積層して非線形抵抗素子
を構成するものである。Alternatively, a first semiconductor layer made of silicon doped with phosphorus P on a first electrode layer formed on an insulating substrate, and at least one of silicon oxide, silicon nitride and silicon carbide. And a non-linear resistance layer doped with phosphorus P, a second semiconductor layer made of silicon doped with phosphorus P, and a second electrode layer are sequentially laminated to form a non-linear resistance element.
【０００９】あるいは、絶縁性基板の上に間隙部を有し
て第一電極層と第二電極層を形成し、前記第一電極層と
前記間隙部と前記第二電極層を覆う形でリンＰをド−プ
したシリコンより成る半導体層を形成し、前記半導体層
を覆う形でシリコン酸化物、シリコン窒化物、シリコン
炭化物のうち少なくとも１種にリンＰをド−プした非線
形抵抗層を形成し、さらに前記非線形抵抗層の上に導電
体層を形成して非線形抵抗素子を構成するものである。Alternatively, a first electrode layer and a second electrode layer are formed on an insulating substrate with a gap, and the first electrode layer, the gap and the second electrode layer are covered with phosphorus. A semiconductor layer made of silicon doped with P is formed, and a non-linear resistance layer is formed by doping phosphorus P to at least one of silicon oxide, silicon nitride and silicon carbide so as to cover the semiconductor layer. Then, a conductor layer is further formed on the non-linear resistance layer to form a non-linear resistance element.
【００１０】[0010]
【作用】非線形抵抗層としてシリコン酸化物、シリコン
窒化物、シリコン炭化物のうち少なくとも１種にリンＰ
をド−プすることにより、Ｐが電子のトンネル伝導を助
け、閾値電圧を低減するとともに、閾値電圧以上で電子
なだれ現象を促進し、高い電流駆動能力を示す。その結
果、ＯＮ／ＯＦＦ比の向上を可能にする。[Function] As the non-linear resistance layer, at least one of silicon oxide, silicon nitride and silicon carbide is made of phosphorus P.
P assists tunnel conduction of electrons, reduces the threshold voltage, promotes the electron avalanche phenomenon above the threshold voltage, and exhibits a high current driving capability. As a result, the ON / OFF ratio can be improved.
【００１１】[0011]
【実施例】以下に本発明の非線形抵抗素子を液晶ディス
プレイのアレイに適用した実施例を示す。EXAMPLE An example in which the nonlinear resistance element of the present invention is applied to an array of a liquid crystal display will be shown below.
【００１２】図１は第一の発明に基づく非線形抵抗素子
の断面構成図である。ガラスより成る絶縁性基板11上に
スパッタ法によりＣｒ膜を100nm の膜厚で形成し、第一
電極層12とする。この第一電極層は走査信号ラインある
いはデ−タ信号ラインに接続するか、あるいはそれを兼
ねるものである。この第一電極層12上にPH3 を１％含有
させたSiH4にO2を混合した反応ガスを用いたプラズマＣ
ＶＤ法でSiO2にＰをド−プした非線形抵抗層13を50nmの
膜厚で形成する。さらにこの上にスパッタ法によりＣｒ
膜を100nm の膜厚で形成して第二電極層14として非線形
抵抗素子を構成する。第二電極層14にはＩＴＯより成る
透明画素電極層18に接続させる。FIG. 1 is a sectional view of a non-linear resistance element according to the first invention. A Cr film having a thickness of 100 nm is formed on the insulating substrate 11 made of glass by the sputtering method to form the first electrode layer 12. This first electrode layer is connected to the scanning signal line or the data signal line, or serves also as it. Plasma C using a reaction gas obtained by mixing O 2 with SiH 4 containing 1% of PH 3 on the first electrode layer 12.
A non-linear resistance layer 13 in which P is doped on SiO 2 is formed with a film thickness of 50 nm by the VD method. Furthermore, Cr is sputtered on top of this.
The film is formed to have a film thickness of 100 nm, and the second electrode layer 14 serves as a non-linear resistance element. The second electrode layer 14 is connected to the transparent pixel electrode layer 18 made of ITO.
【００１３】図２は本実施例に基づく素子のＶ−Ｉ特性
を示している。破線はＰをド−プしていない従来の場合
であり、閾値電圧が１６Ｖと高く、ＯＮ／ＯＦＦ比は６
ｘ１０5である。これに対し、実線はＰをド−プした本
発明の場合であり、閾値電圧は１１Ｖと低減され、ＯＮ
／ＯＦＦ比も２ｘ１０6 と向上している。FIG. 2 shows the VI characteristic of the device according to this embodiment. The broken line shows a conventional case where P is not doped, the threshold voltage is as high as 16 V, and the ON / OFF ratio is 6
It is x10 5 . On the other hand, the solid line is the case of the present invention in which P is doped, and the threshold voltage is reduced to 11V,
The / OFF ratio is also improved to 2 × 10 6 .
【００１４】本実施例における非線形抵抗層をＩＣＰ法
により組成分析した結果、SiO2にＰが１％ドープされて
いることが確認された。発明者らの実験により非線形性
が向上するＰのドープ比率は0.05%から５％までの範囲
であり、５％を越えることにより閾値電圧以下のＯＦＦ
時でも電流がわずかながら流れてしまい、ON/OFF比の低
下を招くことを確認している。As a result of composition analysis of the non-linear resistance layer in this example by the ICP method, it was confirmed that SiO 2 was doped with 1% of P. According to the experiments conducted by the inventors, the doping ratio of P that improves the non-linearity is in the range of 0.05% to 5%.
It has been confirmed that a small amount of current flows even at times, leading to a reduction in the ON / OFF ratio.
【００１５】図３は第二の発明に基づく非線形抵抗素子
の断面構成図である。ガラスより成る絶縁性基板31上に
スパッタ法によりＣｒ膜を100nm の膜厚で形成し、第一
電極層32とする。この第一電極層32は走査信号ラインあ
るいはデ−タ信号ラインに接続するか、あるいはそれを
兼ねるものである。この第一電極層32上にPH3 を１％含
有させたSiH4を反応ガスとしたプラズマＣＶＤ法でアモ
ルファスＳｉ（以下、a-Siと記す）にＰをド−プした第
一半導体層35を100nm の膜厚で形成する。FIG. 3 is a sectional view of a non-linear resistance element according to the second invention. A Cr film having a thickness of 100 nm is formed on an insulating substrate 31 made of glass by a sputtering method to form a first electrode layer 32. The first electrode layer 32 is connected to the scanning signal line or the data signal line, or serves also as it. A first semiconductor layer 35 obtained by doping P onto amorphous Si (hereinafter referred to as a-Si) by a plasma CVD method using SiH 4 containing 1% of PH 3 as a reaction gas on the first electrode layer 32. Is formed with a film thickness of 100 nm.
【００１６】さらに、この第一半導体層35上にPH3を１
％含有させたSiH4にO2 を混合した反応ガスを用いたプ
ラズマＣＶＤ法でSiO2にＰをド−プした非線形抵抗層33
を50nmの膜厚で形成する。さらにこの上に第一半導体層
35と同様にPH3 を１％含有させたSiH4を反応ガスとした
プラズマＣＶＤ法でＰをド−プしたa-Siをド−プした第
二半導体層36を100nm の膜厚で形成する。さらにスパッ
タ法によりSiO2より成る保護絶縁層39を積層し、コンタ
クトホール部30を形成した後、スパッタ法によりＣｒ膜
を150nm の膜厚で形成して第二電極層34とし、コンタク
トホール部30で第二半導体層36と接触させ、素子を構成
する。なお、第二電極層34は透明画素電極層38に接続さ
せる。Further, one PH 3 is deposited on the first semiconductor layer 35.
% Non-linear resistance layer in which P is doped in SiO 2 by a plasma CVD method using a reaction gas in which Si 2 H 4 is mixed with O 2 33
Is formed with a film thickness of 50 nm. Further on top of this the first semiconductor layer
Similarly to 35, a second semiconductor layer 36 of a-Si doped with P is formed with a thickness of 100 nm by plasma CVD using SiH 4 containing 1% of PH 3 as a reaction gas. . Further, a protective insulating layer 39 made of SiO 2 is laminated by a sputtering method to form a contact hole portion 30, and then a Cr film is formed to a thickness of 150 nm by a sputtering method to form a second electrode layer 34. The element is formed by contacting the second semiconductor layer 36 with. The second electrode layer 34 is connected to the transparent pixel electrode layer 38.
【００１７】図４は第二の実施例に基づく素子のＶ−Ｉ
特性を示している。破線はＰをド−プしていない従来の
場合であり、閾値電圧が１８Ｖと高く、ＯＮ／ＯＦＦ比
は１０6 である。これに対し、実線はＰをド−プした本
発明の場合であり、閾値電圧は１３Ｖと低減され、ＯＮ
／ＯＦＦ比も５ｘ１０6 と向上している。図３に示す第
二の素子構成では図１に示す第一の構成に対して第一半
導体層35と第二半導体層36が付加されているが、以下の
点においてこの効果を発揮する。FIG. 4 shows the VI of the device according to the second embodiment.
It shows the characteristics. The broken line shows the conventional case where P is not doped, the threshold voltage is as high as 18V, and the ON / OFF ratio is 10 6 . On the other hand, the solid line is the case of the present invention in which P is doped, and the threshold voltage is reduced to 13V,
The / OFF ratio is also improved to 5 × 10 6 . In the second element structure shown in FIG. 3, the first semiconductor layer 35 and the second semiconductor layer 36 are added to the first structure shown in FIG. 1, but this effect is exhibited in the following points.
【００１８】非線形抵抗素子を液晶ディスプレイに適用
する場合、クロストーク発生の防止のため、非線形抵抗
素子の容量Cnlを液晶層の容量Clcに対して十分小さくす
ることが必要である。ところが図１に示す第一の構成で
は薄い非線形抵抗層13のためCnlが大きくなってしま
い、Cnl/Clcは1/8を示し、若干、クロストークの発生が
見られる。ところが、第二の構成では非線形抵抗層33だ
けでなく、第一半導体層35、第二半導体層36もCnlを分
担するため、Cnlを小さくすることができ、Cnl/Clcは1/
15となり、クロストークの発生は極めて少ない。When the nonlinear resistance element is applied to a liquid crystal display, it is necessary to make the capacitance Cnl of the nonlinear resistance element sufficiently smaller than the capacitance Clc of the liquid crystal layer in order to prevent crosstalk. However, in the first configuration shown in FIG. 1, Cnl becomes large because of the thin nonlinear resistance layer 13, Cnl / Clc shows 1/8, and a little crosstalk is observed. However, in the second configuration, not only the non-linear resistance layer 33, but also the first semiconductor layer 35, the second semiconductor layer 36 shares Cnl, it is possible to reduce Cnl, Cnl / Clc is 1 /.
It is 15, and the occurrence of crosstalk is extremely low.
【００１９】図５は第三の発明に基づく非線形抵抗素子
の断面構成図である。絶縁性基板51の上にスパッタ法で
Ｃｒ膜を100nm の膜厚で形成した後、間隙部50を有して
Ｃｒ膜を第一電極層52と第二電極層54に分割する。この
第一電極層52は走査信号ラインあるいはデ−タ信号ライ
ンに接続するか、あるいはそれを兼ねるものである。ま
た、第二電極層54はＩＴＯより成る透明画素電極層58に
接続させる。FIG. 5 is a sectional view showing the configuration of a non-linear resistance element according to the third invention. After forming a Cr film with a thickness of 100 nm on the insulating substrate 51 by a sputtering method, the Cr film is divided into a first electrode layer 52 and a second electrode layer 54 with a gap 50. The first electrode layer 52 is connected to the scanning signal line or the data signal line, or serves also as it. The second electrode layer 54 is connected to the transparent pixel electrode layer 58 made of ITO.
【００２０】次にPH3 を１％含有させたSiH4を反応ガス
としたプラズマＣＶＤ法でＰをド−プしたa-Siより成る
半導体層55を第一電極層52と間隙部50と第二電極層54を
覆う形で100nm の膜厚で形成する。さらに、この半導体
層55上にPH3を１％含有させたSiH4にO2 を混合した反応
ガスを用いたプラズマＣＶＤ法でSiO2にＰをド−プした
非線形抵抗層53を30nmの膜厚で形成する。さらに非線形
抵抗層53の上に導電体層57としてスパッタ法でＣｒ膜を
100nm の膜厚で形成を形成して非線形抵抗素子を構成す
る。Next, a semiconductor layer 55 made of a-Si doped with P by a plasma CVD method using SiH 4 containing 1% of PH 3 as a reaction gas is formed on the first electrode layer 52, the gap 50 and the first electrode layer 52. The two-electrode layer 54 is formed so as to have a thickness of 100 nm. Furthermore, de P to SiO 2 by plasma CVD using a reaction gas mixed with O 2 to PH 3 on the semiconductor layer 55 to the SiH 4 which contains 1% - film flop to 30nm nonlinear resistive layer 53 Form with a thick thickness. Further, a Cr film is formed as a conductor layer 57 on the nonlinear resistance layer 53 by a sputtering method.
A nonlinear resistance element is formed by forming a film with a film thickness of 100 nm.
【００２１】この第三の構成では、電流の流れは第一電
極層52−半導体層55−非線形抵抗層53−導電体層57−非
線形抵抗層53−半導体層55−第二電極層54となり、正と
負の両極性の電圧に対して各層の界面は同一の薄膜群に
基づく構成のため、対称なＶ−Ｉ特性が得られる特長を
持つ。In this third structure, the current flow is the first electrode layer 52-semiconductor layer 55-nonlinear resistance layer 53-conductor layer 57-nonlinear resistance layer 53-semiconductor layer 55-second electrode layer 54, Since the interface of each layer is based on the same thin film group for both positive and negative polarities, it has a characteristic that symmetrical VI characteristics can be obtained.
【００２２】図６は第三の実施例に基づく素子のＶ−Ｉ
特性（第一電極層52と第二電極層54の間に電圧Ｖを印
加）を示している。破線はＰをド−プしていない従来の
場合であり、閾値電圧が２０Ｖと高く、ＯＮ／ＯＦＦ比
は１０6 である。これに対し、実線はＰをド−プした本
発明の場合であり、閾値電圧は１５Ｖと低減され、ＯＮ
／ＯＦＦ比も５ｘ１０6 と向上している。FIG. 6 shows a VI of a device according to the third embodiment.
The characteristics (voltage V is applied between the first electrode layer 52 and the second electrode layer 54) are shown. The broken line shows the conventional case where P is not doped, the threshold voltage is as high as 20 V, and the ON / OFF ratio is 10 6 . On the other hand, the solid line is the case of the present invention in which P is doped, and the threshold voltage is reduced to 15V,
The / OFF ratio is also improved to 5 × 10 6 .
【００２３】なお、本実施例では非線形抵抗層としてシ
リコン酸化物にリンＰをド−プしているが、シリコン窒
化物あるいはシリコン炭化物にリンＰをドープしても同
様の効果を得ることができる。また、本実施例ではシリ
コン酸化物を化学当量物質であるSiO2として説明してい
るが、非化学当量物質であるのSiOx(0＜x＜2),SiNy(0＜
y＜3/4),SiCz(0＜z＜1)を適用しても、リンＰをドープ
することにより、ON/OFF比の向上が認められ、有効であ
る。Although phosphorus P is doped in the silicon oxide as the non-linear resistance layer in this embodiment, the same effect can be obtained by doping phosphorus P in silicon nitride or silicon carbide. . Further, in the present embodiment, silicon oxide is described as SiO 2 which is a chemical equivalent substance, but SiOx (0 <x <2) and SiNy (0 <
Even if y <3/4) and SiCz (0 <z <1) are applied, the ON / OFF ratio is improved by doping with phosphorus P, which is effective.
【００２４】本実施例において、電極層の材料をＣｒと
して説明しているが、これに限定されるものでなく、Ａ
ｌ等でもよい。In this embodiment, the material of the electrode layer is described as Cr, but the material is not limited to this, and A
1 or the like may be used.
【００２５】[0025]
【発明の効果】以上のように本発明によれば、Ｖ−Ｉ特
性において閾値電圧を低減させるとともに、ＯＮ／ＯＦ
Ｆ比の高い非線形性を実現する非線形抵抗素子を提供す
ることができ、その工業的価値は極めて高い。As described above, according to the present invention, it is possible to reduce the threshold voltage in the VI characteristic and to turn ON / OF.
It is possible to provide a non-linear resistance element that realizes non-linearity with a high F ratio, and its industrial value is extremely high.
【図１】本発明の非線形抵抗素子の第１の実施例の構成
を示す断面図FIG. 1 is a sectional view showing the configuration of a first embodiment of a nonlinear resistance element of the present invention.
【図２】同実施例素子のＶ−Ｉ特性図FIG. 2 is a VI characteristic diagram of the device of the example.
【図３】本発明の非線形抵抗素子の第２の実施例の構成
を示す断面構成図FIG. 3 is a cross-sectional configuration diagram showing a configuration of a second embodiment of a nonlinear resistance element of the present invention.
【図４】同実施例素子のＶ−Ｉ特性図FIG. 4 is a VI characteristic diagram of the device of the same example.
【図５】本発明の非線形抵抗素子の第３の実施例の構成
を示す断面構成図FIG. 5 is a sectional configuration diagram showing a configuration of a third embodiment of a nonlinear resistance element of the present invention.
【図６】同実施例素子のＶ−Ｉ特性図FIG. 6 is a VI characteristic diagram of the device of the same example.
【図７】従来の非線形抵抗素子の構成を示す断面図FIG. 7 is a cross-sectional view showing the configuration of a conventional nonlinear resistance element.
11,31,51 絶縁性基板 12,32,52 第一電極層 13,33,53 非線形抵抗層 14,34,54 第二電極層 34 第一半導体層 35 第二半導体層 54 半導体層 57 導電体層 11,31,51 Insulating substrate 12,32,52 First electrode layer 13,33,53 Non-linear resistance layer 14,34,54 Second electrode layer 34 First semiconductor layer 35 Second semiconductor layer 54 Semiconductor layer 57 Conductor layer
Claims (4)
層、第二電極層を順次積層して成る非線形抵抗素子であ
って、前記非線形抵抗層はシリコン酸化物、シリコン窒
化物、シリコン炭化物のうち少なくとも１種にリンＰを
ド−プして構成した非線形抵抗素子。1. A non-linear resistance element comprising a first electrode layer, a non-linear resistance layer and a second electrode layer which are sequentially laminated on an insulating substrate, the non-linear resistance layer being made of silicon oxide, silicon nitride, A non-linear resistance element formed by doping phosphorus P to at least one of silicon carbide.
リンＰをド−プしたシリコンより成る第一半導体層、さ
らにシリコン酸化物、シリコン窒化物、シリコン炭化物
のうち少なくとも１種にリンＰをド−プした非線形抵抗
層、リンＰをド−プしたシリコンより成る第二半導体
層、第二電極層を順次積層して構成した非線形抵抗素
子。2. A first semiconductor layer made of silicon doped with phosphorus P on a first electrode layer formed on an insulating substrate, and at least one of silicon oxide, silicon nitride and silicon carbide. A non-linear resistance element formed by sequentially stacking a non-linear resistance layer doped with phosphorus P, a second semiconductor layer made of silicon doped with phosphorus P, and a second electrode layer.
層と第二電極層を形成し、前記第一電極層と前記間隙部
と前記第二電極層を覆う形でリンＰをド−プしたシリコ
ンより成る半導体層を形成し、前記半導体層を覆う形で
シリコン酸化物、シリコン窒化物、シリコン炭化物のう
ち少なくとも１種にリンＰをド−プした非線形抵抗層を
形成し、さらに前記非線形抵抗層の上に導電体層を形成
して構成した非線形抵抗素子。3. A first electrode layer and a second electrode layer are formed on an insulating substrate with a gap portion, and a phosphorus is formed so as to cover the first electrode layer, the gap portion and the second electrode layer. A semiconductor layer made of silicon doped with P is formed, and a non-linear resistance layer is formed by doping phosphorus P to at least one of silicon oxide, silicon nitride and silicon carbide so as to cover the semiconductor layer. And a non-linear resistance element formed by further forming a conductor layer on the non-linear resistance layer.
は0.05％から５％までの範囲にある請求項１乃至３の何
れかに記載の非線形抵抗素子。4. The nonlinear resistance element according to claim 1, wherein the phosphorus P doping ratio in the nonlinear resistance layer is in the range of 0.05% to 5%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3172499A JPH0519295A (en) | 1991-07-12 | 1991-07-12 | Nonlinear resistance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3172499A JPH0519295A (en) | 1991-07-12 | 1991-07-12 | Nonlinear resistance element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0519295A true JPH0519295A (en) | 1993-01-29 |
Family
ID=15943110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3172499A Pending JPH0519295A (en) | 1991-07-12 | 1991-07-12 | Nonlinear resistance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0519295A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100282983B1 (en) * | 1993-06-28 | 2001-03-02 | 박영구 | Low reflection matrix blanks for liquid crystal display devices and method of manufacturing the same |
| KR100288768B1 (en) * | 1998-04-10 | 2001-05-02 | 윤종용 | Tft-lcd |
| WO2009150751A1 (en) * | 2008-06-13 | 2009-12-17 | 株式会社船井電機新応用技術研究所 | Switching element |
-
1991
- 1991-07-12 JP JP3172499A patent/JPH0519295A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100282983B1 (en) * | 1993-06-28 | 2001-03-02 | 박영구 | Low reflection matrix blanks for liquid crystal display devices and method of manufacturing the same |
| KR100288768B1 (en) * | 1998-04-10 | 2001-05-02 | 윤종용 | Tft-lcd |
| WO2009150751A1 (en) * | 2008-06-13 | 2009-12-17 | 株式会社船井電機新応用技術研究所 | Switching element |
| US8653912B2 (en) | 2008-06-13 | 2014-02-18 | Funai Electric Advanced Applied Technology Research Institute Inc. | Switching element |
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