JPH05190776A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method wherein the deterioration of the characteristic of a bipolar transistor is eliminated in a semiconductor device which is provided with the bipolar transistor and a MOS transistor. CONSTITUTION:In the manufacturing method of a semiconductor device which is provided with a bipolar transistor and a MOS transistor, the following are included: a process wherein the formation region of the bipolar transistor is covered with a gate formation material 6a when a gate for the MOS transistor is formed; a process wherein the gate formation material in the electrode formation region of the bipolar transistor is removed; a process wherein a sidewall oxide film 8 is formed in the electrode formation region of the bipolar transistor and in the formation region of said gate; and a process wherein an interlayer insulating film 9 is formed. In addition, a process wherein the interlayer insulating film 9 in the formation region of the bipolar transistor and the sidewall oxide film 8 in the electrode formation region of the bipolar transistor are removed is included.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor, which eliminates characteristic deterioration of the bipolar transistor.

[0002]

2. Description of the Related Art FIGS. 6 to 8 show BiC according to a conventional method.
FIG. 6 is a top sectional view of a silicon substrate of a bipolar transistor part and a channel PMOS transistor part in a MOS transistor manufacturing process.

As shown in FIG. 6A, an N ^- layer 1, a bipolar transistor and a CMO are formed in the collector region and the PMOS transistor region of the bipolar transistor.
P ⁺ isolation 2 is formed in the region separating each device of the S transistor, P ⁻ layer 3 is formed in the base region of the bipolar transistor, P ⁺ layer 4, field oxide film 5, and oxide film 7 are formed in the source and drain regions of the PMOS transistor. After that, polysilicon is formed on the entire surface of the silicon substrate by the low pressure CVD method, and then the polysilicon 6a of the gate electrode portion of the CMOS transistor is left,
Polysilicon in the other regions is removed by RIE.

Next, an oxide film is formed on the entire surface of the silicon substrate by the low pressure CVD method, and then the entire surface is etched back by RIE. As shown in FIG. 6B, the sidewall oxide film 8 is formed on the side wall of the gate electrode portion of the CMOS transistor. Formed in.

Next, P ⁺ ions are implanted into the source and drain regions of the P channel MOS transistor to form a P ⁺ layer 4, and then an oxide film 7 is formed by thermal oxidation as shown in FIG. 6C. The BPSG film 9 is formed by the atmospheric pressure CVD method.

Next, as shown in FIG. 7 (a), after opening contact holes by RIE in the base electrode portion, the emitter electrode portion, and the collector electrode portion of the bipolar transistor, as shown in FIG. 7 (b). Polysilicon 6 is formed on the entire surface of the silicon substrate by the low pressure CVD method.
Next, as shown in FIG. 7C, the polysilicon 6c of the base electrode portion, the emitter electrode portion, and the collector electrode portion is left, and R
Other polysilicon 6 is removed by IE.

Next, as shown in FIG. 8A, RIE is performed on the source electrode portion and the drain electrode portion of the CMOS transistor.
After the contact hole is opened by, aluminum is vapor-deposited as shown in FIG. 8B, and then the electrode portions of the bipolar transistor and the CMOS transistor are left by RIE, and aluminum is removed to remove the base electrode 12, the emitter electrode 11, Collector electrode 1
3, the source electrode 14 and the drain electrode 15 are formed.

[0008]

However, in the above method, the oxide film 7 formed on the entire surface of the silicon substrate by the CVD method and shown in FIG. 6A is etched back by RIE and removed. In the step b), the silicon substrate surface of the active portion 16 of the bipolar transistor is also etched. In the step of opening contact holes in the base electrode portion, the emitter electrode portion, and the collector electrode portion of the bipolar transistor by RIE shown in FIG. 7A, the silicon substrate surface of each electrode portion is also etched. ..
As described above, in the conventional process, the active region of the surface of the silicon substrate, which is not desired to be etched, is etched, and the characteristics of the bipolar transistor are deteriorated.

If wet etching is used instead of RIE in order to avoid the above-described problem of etching damage in the step of FIG. 7A, it is not suitable for fine processing due to the nature of isotropic etching of wet etching.

Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor device that eliminates the deterioration of the characteristics of a bipolar transistor.

[0011]

According to the present invention, in the method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor, the above-mentioned gate forming material is used when the gate of the MOS transistor is formed in the bipolar transistor forming region. And a step of removing the gate forming material in the electrode forming region of the bipolar transistor, a step of forming a sidewall oxide film in the electrode forming region and the gate forming region of the bipolar transistor, and an interlayer insulating film. And a step of removing the interlayer insulating film in the bipolar transistor formation region and the sidewall oxide film in the electrode formation region of the bipolar transistor by wet etching. It is solved by the manufacturing method.

Further, according to the present invention, there is provided the above-mentioned object, wherein the step of covering the bipolar transistor forming region with the gate forming material at the time of forming the gate of the MOS transistor, the bipolar transistor forming region and the MOS transistor gate forming region. Removing the gate forming material in regions other than the above, forming a sidewall oxide film in the gate forming region, forming an interlayer insulating film, and removing the interlayer insulating film in the bipolar transistor forming region And a step of removing the gate forming material of the bipolar transistor forming region by RIE, and a step of removing the oxide film of the bipolar transistor electrode forming region by wet etching. It

[0013]

According to the present invention, as shown in FIG.
In the step of forming the sidewall oxide film 8 in the gate forming region of the MOS transistor by etching back the entire surface by the above, in the bipolar transistor forming region, the base electrode portion and the emitter electrode portion opened in the step shown in FIG. The sidewall oxide film 8 remains, and the gate forming material 6a is formed in regions other than these openings.
2A does not damage the active part of the bipolar transistor, and in the step of removing the interlayer insulating film 9 and the sidewall oxide film 8 of the bipolar transistor part as shown in FIG. A side wall oxide film 8 is formed on each of the base electrode portion, the emitter electrode portion, and the collector electrode portion, and an oxide film 7 is formed below the side wall oxide film 8. Further, the peripheral portion of the side wall oxide film 8 has a gate forming material 6a. Since wet etching is formed, wet etching can be used for fine processing due to the etching selectivity, and therefore damage to the silicon substrate at the contact hole opening can be eliminated.

Further, according to the present invention, as shown in FIG. 4B, in the step of etching back the entire surface by RIE to form the sidewall oxide film 8 in the gate formation region of the MOS transistor, in the bipolar transistor formation region. Since it is covered with the gate forming material 6a, it does not damage the active portion of the bipolar transistor, and as shown in FIG. 5A, after removing the interlayer insulating film 9 in the bipolar transistor forming region, the base electrode portion, In the step of opening the contact holes in the emitter electrode portion and the collector electrode portion, the gate forming material 6a in the opening can be removed first by the etching selectivity of RIE, and then the oxide film in the opening can be formed by wet etching. By removing 7, the silicon of this opening It is possible to eliminate the damaging the plate surface.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIGS. 1 to 3 show a first embodiment of the present invention, which is an upper sectional view of a silicon substrate of a bipolar transistor portion and a P-channel MOS transistor portion in a manufacturing process of a BiCMOS transistor. 1 is a sectional view in the first half process, FIG. 2 is a middle half process, and FIG. 3 is a sectional view in the latter half process.

As shown in FIG. 1A, an N ^- layer 1, a bipolar transistor and a CMO are formed in the collector region and the PMOS transistor region of the bipolar transistor.
P ⁺ isolation 2 is formed in the region separating the device of the S transistor, P ⁻ layer 3 is formed in the base region of the bipolar transistor, P ⁺ layer 4 and field oxide film 5 are formed in the source and drain regions of the PMOS transistor, and then thermal oxidation is performed. Forming an oxide film 7 with a thickness of 30 nm in the bipolar transistor and CMOS transistor regions by means of a low pressure CVD method for 400 n
Polysilicon is formed to a thickness of about m. Then, by RIE, in the MOS transistor formation region, the polysilicon in the region other than the gate formation region and the polysilicon in the openings of the base electrode portion, the emitter electrode portion, and the collector electrode portion of the bipolar transistor are 0.6 μm wide.
When removed to a certain extent, polysilicon 6a is formed in regions other than the base electrode part, the emitter electrode part, and the collector electrode part in the gate electrode part and the bipolar transistor formation region.

Next, after forming an oxide film with a thickness of about 300 nm on the entire surface of the silicon substrate by the low pressure CVD method,
When the entire surface is etched back by RIE, as shown in FIG. 1B, sidewall oxide films 8 are formed on the gate electrode portion, the base electrode portion, the emitter electrode portion, and the collector electrode portion, respectively. Next, P ⁺ ions are implanted into the source and drain regions of the P channel MOS transistor to form P ⁺ . Next, as shown in FIG. 1C, after forming an oxide film 7 with a thickness of about 40 nm in the source and drain regions of the CMOS transistor by thermal oxidation,
The BPSG film 9 is formed to a thickness of about 600 nm by the atmospheric pressure CVD method.

Next, the CMOS transistor portion is covered with a resist pattern at a predetermined position, and as shown in FIG. 2A, the BPSG film 9 and the sidewall oxide film 8 of the bipolar transistor are removed by wet etching.
As a result, although the silicon substrate surface (active region) of the contact opening is conventionally damaged by etching by RIE, this can be eliminated.

Next, as shown in FIG. 2B, polysilicon 6 is formed to a thickness of about 100 nm on the entire surface of the silicon substrate by a low pressure CVD method, and then a bipolar transistor is formed as shown in FIG. 2C. The polysilicons 6a and 6b in the contact portions are left, and the polysilicons 6 and 6a in other regions are removed by RIE.

Next, as shown in FIG. 3A, RIE is performed on the source electrode portion and the drain electrode portion of the CMOS transistor.
After opening the contact hole by N.sub.2, N.sup. ⁺ Ions are implanted into the emitter electrode portion of the bipolar transistor to form the N.sup. ⁺ Layer 10, and then, as shown in FIG.
Aluminum is vapor-deposited on the entire surface of the silicon substrate to a thickness of about μm, the polysilicon 6 and aluminum in the region other than the electrode portion of the bipolar transistor are removed by RIE, and the emitter electrode portion 11, the base electrode portion 12, the collector electrode portion 13, Source electrode portion 14 and drain electrode portion 1
5 are sequentially formed.

FIGS. 4 and 5 show a second embodiment, which is Bi.
FIG. 9 is a cross-sectional top view of the silicon substrate of the bipolar transistor portion and the P-channel MOS transistor portion in the first half manufacturing process and the middle half partial manufacturing process of the CMOS transistor.

Similar to FIG. 1, first in FIG. 4A, the collector region and PMO of the bipolar transistor are formed.
N ⁻ layer 1 in the S transistor region, P ⁺ isolation 2 in the region separating the bipolar transistor and CMOS transistor devices, P ⁻ layer 3 in the base region of the bipolar transistor, P ⁺ layer 4 in the source and drain regions of the PMOS transistor. After forming the field oxide film 4 and the oxide film 7, the polysilicon 6 is formed on the entire surface of the silicon substrate to a thickness of about 400 nm by the low pressure CVD method, and then the polysilicon of the bipolar transistor formation region and the gate formation region of the CMOS transistor is formed. Other polysilicon 6 is removed by RIE while leaving 6a.

Next, after forming an oxide film with a thickness of about 300 nm on the entire surface of the silicon substrate by the low pressure CVD method, R
When the entire surface is etched back by IE, the sidewall oxide film 8 is formed on the gate electrode portion as shown in FIG. Next, P ⁺ ions are implanted into the source and drain regions of the P channel MOS transistor to form a P ⁺ layer 4, and then, as shown in FIG. 4C, thermal oxidation is performed to the CMOS transistor and the drain region with a thickness of about 40 nm. After forming the oxide film to a thickness, the BPSG film 9 is formed to a thickness of about 600 nm by the atmospheric pressure CVD method.

Next, as shown in FIG. 5 (a), the CMOS transistor portion is covered with a resist pattern, and the BPSG film 9 is removed by RIE. Then, as shown in FIG. 5 (b), the base electrode portion of the bipolar transistor, Regions other than the emitter electrode portion and the collector electrode portion are covered with a resist pattern, the polysilicon 6a is removed by RIE, and then the oxide film 7 is removed by wet etching as shown in FIG. 5C. At this time, polysilicon 6 is formed by RIE.
Since only a is removed and the oxide film 7 is removed by wet etching, the silicon substrate surface of the electrode portion of the bipolar transistor is not damaged.

Next, after the polysilicon 6 is formed on the entire surface of the silicon substrate in the same manner as in FIG. 2B, FIG.
Similarly to the above, the polysilicon 6a and 6b at the contact portion of the bipolar transistor are left, and the other polysilicon 6 and 6a are removed by RIE.

Next, after opening contact holes in the source electrode portion and the drain electrode portion in the same manner as in FIG. 3A, N ⁺ ions are implanted in the emitter electrode portion, and the N ⁺ layer 10 is formed.
After forming, the electrodes of the bipolar transistor and the CMOS transistor are formed in the same manner as in FIG. In this embodiment, polysilicon is used as the material film for forming the gate electrode of the CMOS transistor, but silicide such as tungsten is also applicable.

[0028]

As described above, according to the present invention, the bipolar transistor and the MOS which eliminate the damage caused by the RIE at the time of forming the sidewall and the RIE at the time of forming the contact of the bipolar transistor and eliminate the influence on the characteristics of the bipolar transistor. A semiconductor device having a transistor can be provided.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention, and is an upper sectional view of a silicon substrate of a bipolar transistor portion and a P-channel MOS transistor portion in a first half manufacturing process of a BiCMOS transistor.

FIG. 2 is a first embodiment of the present invention and is a cross-sectional top view of the silicon substrate of the bipolar transistor portion and the P-channel MOS transistor portion in the middle half manufacturing process of the BiCMOS transistor.

FIG. 3 is a first embodiment of the present invention, and is an upper sectional view of the silicon substrate of the bipolar transistor portion and the P-channel MOS transistor portion in the latter half manufacturing process of the BiCMOS transistor.

FIG. 4 is a second embodiment of the present invention, and is an upper sectional view of the silicon substrate of the bipolar transistor portion and the P-channel MOS transistor portion in the first half manufacturing process of the BiCMOS transistor.

FIG. 5 is a second embodiment of the present invention and is a cross-sectional top view of the silicon substrate of the bipolar transistor portion and the P-channel MOS transistor portion in the manufacturing process of the middle half of the BiCMOS transistor.

FIG. 6 shows a bipolar transistor portion and P in a first half manufacturing process of a BiCMOS transistor according to a conventional example.
It is an upper sectional view of a silicon substrate of a channel MOS transistor part.

FIG. 7 shows a bipolar transistor portion and P in a middle manufacturing process of a BiCMOS transistor according to a conventional example.
It is an upper sectional view of a silicon substrate of a channel MOS transistor part.

FIG. 8 shows a bipolar transistor portion and P in a second half manufacturing process of a BiCMOS transistor according to a conventional example.
It is an upper sectional view of a silicon substrate of a channel MOS transistor part.

[Explanation of symbols]

1 N ^- layer 2 P ⁺ isolation 3 P ^- layer 4 P ⁺ layer 5 Field oxide film 6,6a, 6b, 6c Polysilicon 7 Oxide film 8 Sidewall oxide film 9 BPSG film 10 N ⁺ layer 11 Emitter electrode 12 Base Electrode 13 Collector electrode 14 Source electrode 15 Drain electrode 16 Bipolar transistor active area

Claims (2)

[Claims] 1. A bipolar transistor and a MOS
In a method of manufacturing a semiconductor device having a transistor, a step of covering the bipolar transistor forming region with a gate forming material when forming a gate of the MOS transistor, and a step of removing the gate forming material of an electrode forming region of the bipolar transistor. Forming a sidewall oxide film in the electrode forming region and the gate forming region of the bipolar transistor; forming an interlayer insulating film; forming the interlayer insulating film and the electrode of the bipolar transistor in the bipolar transistor forming region; A method of manufacturing a semiconductor device, comprising a step of removing a sidewall oxide film in a region by wet etching. 2. Bipolar transistor and MOS
In a method of manufacturing a semiconductor device having a transistor, a step of covering the bipolar transistor formation region with the gate formation material when forming a gate of the MOS transistor, the bipolar transistor formation region and the MO transistor.
Removing the gate forming material in a region other than the S transistor gate forming region; forming a sidewall oxide film in the gate forming region; forming an interlayer insulating film; and interlayer insulating in the bipolar transistor forming region A semiconductor device comprising: a step of removing a film; a step of removing a gate forming material in the bipolar transistor forming region by RIE; and a step of removing an oxide film in an electrode forming region of the bipolar transistor by wet etching. Manufacturing method.