JPH05190761A - Delay-element package - Google Patents
Delay-element packageInfo
- Publication number
- JPH05190761A JPH05190761A JP101492A JP101492A JPH05190761A JP H05190761 A JPH05190761 A JP H05190761A JP 101492 A JP101492 A JP 101492A JP 101492 A JP101492 A JP 101492A JP H05190761 A JPH05190761 A JP H05190761A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- delay element
- pins
- terminal
- gnd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は情報処理装置のクロック
分配系の遅延時間の調整に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to adjusting a delay time of a clock distribution system of an information processing device.
【0002】[0002]
【従来の技術】従来、この種の遅延時間の調整は、1つ
の入力に対して遅延時間の異なる複数の出力を持つ素子
と切り替えスイッチにより構成された遅延時間調整回路
を使用するか、あるいは複数個のある一定の遅延時間を
有する遅延素子(以下固定遅延素子と称する)の接続を
調整値に応じて切り替える方法で遅延時間調整を行なっ
ていた。2. Description of the Related Art Conventionally, this kind of delay time adjustment uses a delay time adjusting circuit composed of an element having a plurality of outputs having different delay times for one input and a changeover switch, or a plurality of delay time adjusting circuits. The delay time is adjusted by a method of switching the connection of a plurality of delay elements having a certain delay time (hereinafter referred to as fixed delay elements) according to the adjustment value.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の方法
は、遅延時間の異なる素子を使用する遅延時間調整回路
は切り替えスイッチの形状が大きくそれだけ広い実装ス
ペースを必要とし、このために電気的特性が劣化し配線
が長くなることにより装置性能も劣化するという欠点が
あった。また、固定遅延素子による方法は電気的特性は
問題ないが実装上1つの素子について多数の接地端子
(以下GND端子と称する)を要し、前記遅延時間調整
回路ほどではないがある程度の実装スペースを必要と
し、特にこの固定遅延素子複数個を一定の範囲の中に実
装しようとすると固定遅延素子の外形的制約で無理な場
合も起こるという欠点がある。In the conventional method described above, the delay time adjusting circuit using elements having different delay times requires a large mounting space because of the large shape of the changeover switch. There is a drawback that the device performance is deteriorated due to deterioration and lengthening of wiring. In addition, although the fixed delay element method has no problem in electrical characteristics, a large number of ground terminals (hereinafter referred to as GND terminals) are required for one element in terms of mounting, and a certain mounting space is required although it is not as large as that of the delay time adjusting circuit. It is necessary, and there is a drawback that, especially when trying to mount a plurality of these fixed delay elements within a certain range, it may be impossible due to the external restrictions of the fixed delay elements.
【0004】本発明の目的は、電気的特性や装置性能が
劣化せず、一定の範囲の中に実装可能な遅延素子パッケ
ージを提供することである。An object of the present invention is to provide a delay element package which can be mounted within a certain range without deterioration in electrical characteristics and device performance.
【0005】[0005]
【課題を解決するための手段】本発明の第1の遅延素子
パッケージは、電気的遅延時間をもつ複数個の遅延素子
と、各遅延素子の入力端子、出力端子および接地端子に
それぞれ着脱可能に接続される外部入力ピン、外部出力
ピンおよび外部接地ピンが設けられ、かつ前記遅延素子
を着脱可能に保持する基体とを有する。A first delay element package of the present invention is detachably attachable to a plurality of delay elements having an electrical delay time and an input terminal, an output terminal and a ground terminal of each delay element. An external input pin, an external output pin, and an external ground pin to be connected are provided and a base body that detachably holds the delay element.
【0006】本発明の第2の遅延素子パッケージは、基
体に設けられた外部接地ピンの数が、前記基体に保持さ
れた遅延素子の接地端子の数の総和より小さい。In the second delay element package of the present invention, the number of external ground pins provided on the base is smaller than the total number of ground terminals of the delay elements held on the base.
【0007】[0007]
【作用】第1の遅延素子パッケージは遅延素子を交換し
て遅延時間の調整ができるので切替えスイッチ等が不要
となり、実装スペースが小さくてすみ、かつ性能の劣化
が低減できる。In the first delay element package, the delay element can be exchanged to adjust the delay time, so that a changeover switch or the like is unnecessary, a mounting space can be reduced, and deterioration of performance can be reduced.
【0008】第2の遅延素子パッケージは、外部接地ピ
ンの数が少ないので、さらに実装スペースが小さくな
り、一層性能の劣化が防止できる。Since the second delay element package has a small number of external ground pins, the mounting space can be further reduced and the deterioration of performance can be further prevented.
【0009】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0010】図1は本発明の遅延素子パッケージの第1
実施例の斜視図、図2は図1の平面図である。FIG. 1 shows a first delay element package of the present invention.
FIG. 2 is a perspective view of the embodiment, and FIG. 2 is a plan view of FIG.
【0011】この遅延素子パッケージは基体6と遅延素
子7と8と9とより構成されている。This delay element package comprises a base 6 and delay elements 7, 8 and 9.
【0012】遅延素子7,8,9は電気的遅延時間をも
つ遅延素子であって、遅延素子7は接地端子(以下GN
D端子と称する)71,74と入力端子73と出力端子
72を、遅延素子8はGND端子81,84と入力端子
83と出力端子82、および遅延素子9はGND端子9
1,94と入力端子93と出力端子92を備えており、
各端子はパッドを兼ねている。基体6は上面に実装部1
0,11,12を備え、一側面に外部接地ピン(以下G
NDピンと称する)1,5と外部入力ピン(以下入力ピ
ンと称する)2,3,4を備え、他の側面にGNDピン
11 ,51 と外部出力ピン(以下出力ピンと称する)2
1 ,31 ,41 を備えている。実装部10と11と12
にはそれぞれバネ接点101,102,103,104
と111,112,113,114と121,122,
123,124が設けられており、遅延素子7,8,9
がそれぞれ実装部10,11,12の各バネ接点によっ
て着脱自在に装着される。GNDピン1,11 ,5,5
1 は母線(不図示)を介して配線によって接続されたバ
ネ接点101,103,111,113,121,12
3によって、遅延素子7,8,9のGND端子71,7
4,81,84,91,94に接触によって接続され
る。入力ピン2,3,4はそれぞれ配線によって接続さ
れたバネ接点103,113,123によって遅延素子
7,8,9の入力端子73,83,93に接触によって
接続され、出力ピン21 ,31 ,41 も同様にそれぞれ
配線によって接続されたバネ接点102,112,12
2によって遅延素子7,8,9の出力端子72,82,
92に接触によって接続される。この遅延素子パッケー
ジではGNDピンが4個であり、個々の遅延素子につい
てGNDピンを2個ずつ使用した場合は3個の遅延素子
について6個を必要とするのに比べてGNDピンの数が
減少している。The delay elements 7, 8 and 9 are delay elements having an electrical delay time, and the delay element 7 is a ground terminal (hereinafter referred to as GN).
71 and 74, an input terminal 73 and an output terminal 72, a delay element 8 having GND terminals 81 and 84, an input terminal 83 and an output terminal 82, and a delay element 9 having a GND terminal 9
1, 94, an input terminal 93 and an output terminal 92 are provided,
Each terminal also serves as a pad. The base 6 is mounted on the upper surface of the mounting portion 1.
It is equipped with 0, 11, 12 and an external ground pin (hereinafter G
ND pins) 1, 5 and external input pins (hereinafter referred to as input pins) 2, 3, 4 are provided, and GND pins 1 1 , 5 1 and external output pins (hereinafter referred to as output pins) 2 are provided on the other side surface.
It is equipped with 1 , 3 1 , and 4 1 . Mounting parts 10, 11 and 12
Are spring contacts 101, 102, 103, 104, respectively.
And 111, 112, 113, 114 and 121, 122,
123, 124 are provided and delay elements 7, 8, 9 are provided.
Are detachably mounted by the spring contacts of the mounting portions 10, 11, and 12, respectively. GND pins 1, 1 1 , 5, 5
1 is a spring contact 101, 103, 111, 113, 121, 12 connected by wiring through a bus bar (not shown)
3, the delay terminals 7, 8 and 9 have GND terminals 71 and 7
4, 81, 84, 91, 94 are connected by contact. The input pins 2, 3 and 4 are connected to the input terminals 73, 83 and 93 of the delay elements 7, 8 and 9 by contact by spring contacts 103, 113 and 123 respectively connected by wiring, and the output pins 2 1 , 3 1 , 4 1 are similarly connected to the spring contacts 102, 112, 12 respectively by wiring.
2, the output terminals 72, 82 of the delay elements 7, 8, 9 are
Connected to 92 by contact. This delay element package has four GND pins, and when two GND pins are used for each delay element, the number of GND pins is reduced as compared with the case where three delay elements are required for six. is doing.
【0013】本実施例の遅延素子パッケージでは遅延素
子を必要により交換できるので遅延時間調整のための切
替スイッチ等を要せず、GNDピンの数も少なくできる
ので実装スペースが小さく、また、配線が長くなること
によって生ずる電気的特性の劣化が少ない。In the delay element package of this embodiment, since the delay element can be replaced if necessary, a changeover switch or the like for adjusting the delay time is not required, and the number of GND pins can be reduced, so that the mounting space is small and the wiring is small. There is little deterioration of electrical characteristics caused by the lengthening.
【0014】図3は本発明の遅延素子パッケージの第2
実施例の斜視図である。FIG. 3 shows a second delay element package of the present invention.
It is a perspective view of an Example.
【0015】第1実施例においてはいわゆるデュアルイ
ンラインパッケージの形態となっているが、この実施例
においてはシングルインラインパッケージの形態となっ
ている他は、図1、図2の遅延素子パッケージと同様の
構成となっている。すなわち、基体16の実装部30,
31,32のそれぞれのバネ接点(不図示)によって遅
延素子17,18,19が着脱自在に実装され、GND
ピン21,25と入力ピン22,23,24と出力ピン
221 ,231 ,241 のそれぞれと遅延素子17,1
8,19の各端子(不図示)に対する接続は図1の遅延
素子パッケージと同様の構成によってなされている。こ
の遅延素子パッケージでは2個のGNDピン21,25
から母線(不図示)を介して各遅延素子17,18,1
9のGND端子に接続されているので、遅延素子の個々
にGNDピンを設けた場合(6個)に対して遥かに少な
い数(2個)ですんでいる。The first embodiment is in the form of a so-called dual in-line package, but this embodiment is similar to the delay element package of FIGS. 1 and 2 except that it is in the form of a single in-line package. It is composed. That is, the mounting portion 30 of the base body 16,
Delay elements 17, 18 and 19 are detachably mounted by respective spring contacts (not shown) of 31 and 32.
Pins 21, 25, input pins 22, 23, 24, output pins 22 1 , 23 1 , 24 1 and delay elements 17, 1 respectively
Connections to terminals 8 and 19 (not shown) are made in the same configuration as the delay element package of FIG. This delay element package has two GND pins 21, 25.
From each delay element 17, 18, 1 via a bus (not shown)
Since it is connected to the GND terminal of 9, the number (2) is far smaller than the case where the GND pin is provided for each delay element (6).
【0016】本実施例の遅延素子パッケージは第1実施
例の場合よりもさらにGNDピンの数が減少している
他、高さ方向に長い構造となっているので、平面方向の
実装スペースをさらに減少させる効果がある。The delay element package of this embodiment has a smaller number of GND pins than that of the first embodiment and has a structure elongated in the height direction, so that the mounting space in the plane direction is further increased. It has a reducing effect.
【0017】[0017]
【発明の効果】以上説明したように本発明の第1の遅延
素子パッケージは、複数個の遅延素子を着脱可能に基体
に実装することにより、遅延素子を交換して遅延時間の
調整ができ、遅延素子の切替スイッチ等が不要となるの
で、実装スペースが小さくてすみ、配線が長くなること
による電気的特性の劣化などの性能低下が防止できる。
また、第2の遅延素子パッケージは外部接地ピンの数が
減少するので、実装スペースと性能劣化がさらに減少す
るという効果がある。As described above, in the first delay element package of the present invention, a plurality of delay elements are removably mounted on the base body so that the delay elements can be exchanged and the delay time can be adjusted. Since the changeover switch of the delay element is unnecessary, the mounting space can be small, and the deterioration of the performance such as the deterioration of the electrical characteristics due to the long wiring can be prevented.
In addition, since the number of external ground pins is reduced in the second delay element package, there is an effect that mounting space and performance deterioration are further reduced.
【図1】本発明の遅延素子パッケージの第1実施例の斜
視図である。FIG. 1 is a perspective view of a first embodiment of a delay element package according to the present invention.
【図2】図1の平面図である。FIG. 2 is a plan view of FIG.
【図3】本発明の遅延素子パッケージの第2実施例の斜
視図である。FIG. 3 is a perspective view of a second embodiment of a delay element package according to the present invention.
1,11 ,5,51 ,21,25 GNDピン 2,3,4,22,23,24 入力ピン 21 ,31 ,41 ,221 ,231 ,241 出力ピ
ン 6,16 基体 7,8,9,17,18,19 遅延素子 10,11,12,30,31,32 実装部 71,74,81,84,91,94 GND端子 72,82,92 出力端子 73,83,93 入力端子 101,102,103,104,111,112,1
13,114,121,122,123,124 バ
ネ接点1, 1 1 , 5, 5 1 , 21, 25 GND pins 2, 3, 4, 22, 23, 24 Input pins 2 1 , 3 1 , 4 1 , 22 1 , 23 1 , 24 1 Output pins 6, 16 Substrate 7, 8, 9, 17, 18, 19 Delay element 10, 11, 12, 30, 31, 32 Mounting portion 71, 74, 81, 84, 91, 94 GND terminal 72, 82, 92 Output terminal 73, 83 , 93 input terminals 101, 102, 103, 104, 111, 112, 1
13, 114, 121, 122, 123, 124 Spring contact
Claims (2)
間の調整に使用される遅延素子パッケージであって、 電気的遅延時間をもつ複数個の遅延素子と、 各遅延素子の入力端子、出力端子および接地端子にそれ
ぞれ着脱可能に接続される外部入力ピン、外部出力ピン
および外部接地ピンが設けられ、かつ前記遅延素子を着
脱可能に保持する基体とを有する遅延素子パッケージ。1. A delay element package used for adjusting a delay time of a clock distribution system of an information processing apparatus, comprising a plurality of delay elements having an electrical delay time, and an input terminal and an output terminal of each delay element. And a grounding terminal provided with an external input pin, an external output pin, and an external grounding pin detachably connected to the grounding terminal, and a base body detachably holding the delay element.
いて、基体に設けられた外部接地ピンの数が、前記基体
に保持された遅延素子の接地端子の数の総和より小さい
ことを特徴とする遅延素子パッケージ。2. The delay element package according to claim 1, wherein the number of external ground pins provided on the base is smaller than the total number of ground terminals of the delay element held on the base. Element package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP101492A JPH05190761A (en) | 1992-01-07 | 1992-01-07 | Delay-element package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP101492A JPH05190761A (en) | 1992-01-07 | 1992-01-07 | Delay-element package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05190761A true JPH05190761A (en) | 1993-07-30 |
Family
ID=11489722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP101492A Pending JPH05190761A (en) | 1992-01-07 | 1992-01-07 | Delay-element package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05190761A (en) |
-
1992
- 1992-01-07 JP JP101492A patent/JPH05190761A/en active Pending
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