JPH05190623A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To measure an average delay time inside a chip by arranging an self-excitation oscillation circuit for delaytime measurement while dispersing it inside a chip. CONSTITUTION:A self-excitation oscillation circuit 4 for measuring delay time is composed by arranging a NOT-AND operation circuits 3 in the peripheral part of a chip at equal intervals for being electrically in inseries connected. An average delay time of an element of the chip inside can be measured by connecting output of an optional NOT-AND operation circuit 3 to the in-and- output terminals 2 so as to oscillate a self-excitation oscillation circuit. Accordingly, a danger of mistake selection at the time of chip selection can be reduced by knowing an average delay time of the whole of a chip at the time of different delay time of the element depending on the place inside the chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a circuit arrangement of a semiconductor integrated circuit by a logical operation circuit.

[0002]

2. Description of the Related Art In recent years, due to the speeding up of semiconductor integrated circuits,
Since the delay time of the logical operation circuit has become extremely small,
It has become difficult to measure the delay time of a single logic operation circuit.

Therefore, in the conventional technique, as shown in FIG. 3, a self-excited oscillation circuit 2 for delay time measurement, in which an odd number of negative logic operation circuits 23 are used in a part of a chip 26 and are connected in series in a ring shape.
4 was placed in a limited small area with chips. This delay time measurement self-excited oscillation circuit has one reset terminal and one output terminal, and the oscillation circuit oscillates by resetting, and the oscillation condition is to connect a frequency measuring instrument to the output terminal. Can be observed by.

When this circuit is reset, a signal of level "1" is input to the first-stage negative logic operation circuit, and a signal of level "0" inverted from the output is input to the second-stage negative logic operation circuit. Signals are sequentially transmitted through the negative logic operation circuit as if they were input, and a signal of level "1" is input to the final stage negative logic operation circuit. As a result, a signal of level "0" is output to the output of the final NOR circuit. That is, the output of the final-stage negative logic operation circuit always shows a signal of the opposite level to the input signal of the first-stage negative logic operation circuit.

Since this inverted signal is output from the output terminal and at the same time becomes an input signal to the first-stage negative logic operation circuit, the output from the final last-stage negative logic operation circuit is at level "1". Become a signal.

A rectangular wave signal having a certain frequency is observed from the output terminal by the series of signal transfer mechanisms.
For example, if the number of negative logic operation circuit stages of the self-excited oscillation circuit is 45
And the frequency of the output signal is 120 MHz, the delay time per negative logic operation circuit is

## EQU1 ## It can be calculated as 1 / (120 MHz × 45 stages × 2) ≈92.5 [ps].

[0007]

The layout of the self-excited oscillation circuit for measuring the delay time in the above-described conventional semiconductor integrated circuit is such that the oscillation circuit is provided in a limited narrow area in the chip apart from the internal element area. ing. Therefore, when variations occur in the delay times of the elements inside the chip, this circuit arrangement allows the delay times of only a small portion of the chips to be known, but not the delay times of the entire chip. ..

In particular, as the chip size increases, the variation in the delay time inside the chip also increases, and the difference between the delay time measured by the conventional technique and the delay time of the internal element increases.

As a result, there is a problem that the risk of wrong selection at the time of chip selection increases, and the failure occurrence rate when the chip is mounted on the computer main body increases.

In the case of a large chip of about 15 mm square used in a large computer, the defect occurrence rate due to a delay time defect that occurs when a chip selected as a good product at the time of chip selection is mounted on the computer is about 1%. It is said.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel semiconductor integrated circuit device capable of solving the above problems inherent in the prior art. To do.

[0012]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a negative logic operation circuit forming a self-excited oscillation circuit for delay time measurement, and a semiconductor integrated circuit chip as a whole. It is characterized in that it is arranged around the chip so as to surround it, or for each circuit block of the semiconductor integrated circuit divided into two or more, it is arranged around the circuit block so as to surround the whole circuit block.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings for each of its preferred embodiments.

FIG. 1 is a schematic plan view showing a first embodiment of a semiconductor integrated circuit device according to the present invention.

Referring to FIG. 1, along the inner circumference of each of the upper, lower, left and right sides of the chip 6, the NOT logic operation circuits 3 are arranged at equal intervals.
The delay time measuring self-excited oscillation circuit 4 is configured by arranging 1, 12, 11, and 11 pieces and electrically connecting them in series. By connecting the output of one negative logic operation circuit 3 to an arbitrary input / output terminal 2 and connecting a frequency measuring device to that terminal, the average delay time of the elements on the inner circumference of the chip can be measured.

For example, the delay time at the top of the chip is large,
In the case of a chip having a delay time distribution in which the delay time becomes smaller toward the bottom of the chip, the oscillation circuit was provided in an extremely small area within the chip in the conventional technology, and therefore the entire chip It was impossible to measure the average delay time. However, according to the present invention, when the delay times of the elements are varied in the vertical and horizontal directions of the chip, the total of the delay times of the negative logic operation circuits 3 arranged in the upper and lower parts of the chip causes the elements in the horizontal direction of the chip. Can be obtained, and similarly, the average delay time of the elements in the vertical direction of the chip can be obtained by the total delay time of the respective negative logic operation circuits arranged on the left side or the right side of the chip. .. If the total delay times of the negative logic operation circuits arranged on the upper, lower, left and right sides of the chip are A, B, C and D respectively, the average delay time T of the entire chip is

## EQU2 ## It can be obtained by T = (A + B + C + D) / 45.

The frequency f observed from the input / output terminal 2 is

Since f = 1 / {(A + B + C + D) × 2},

## EQU4 ## The delay time can be calculated by T = 1 / (2 × f × 45).

FIG. 2 is a plan conceptual view showing a second embodiment of the semiconductor integrated circuit device according to the present invention.

Referring to FIG. 2, as in the first embodiment, 45 negative logic circuits 3 are arranged on the inner periphery of the first region 11 of the chip 16 and electrically connected in series. A first delay time measuring self-exciting circuit 41 is configured. Similarly, the second delay time measurement self-excited oscillation circuit 42 is provided in the second region 12, the third delay time measurement self-excited oscillation circuit 43 is provided in the third region 13, and the fourth region 14 is provided. The fourth delay time measuring self-excited oscillation circuit 44 is configured, and the average delay time can be measured in each region in the same manner as in the first embodiment.

In the case of the first embodiment, the average delay time of the entire chip can be measured, but the variation tendency of the delay time in the chip cannot be grasped.

However, by disposing a plurality of delay time measuring self-excited oscillation circuits in the chip as in the second embodiment, it is possible to grasp the tendency of dispersion of the delay time inside the chip in detail. Become.

[0022]

As described above, according to the present invention,
Since the self-oscillation circuits for delay time measurement are distributed and arranged in one chip, when the delay times of the elements in the chip vary, the average delay time of the entire chip and the variation tendency of the delay time are detailed. Can be measured. Therefore, it is possible to eliminate almost any inconvenience at the time of mounting, which occurs when the chips are selected based on the delay time of a small part of the chips as in the conventional technique.

[Brief description of drawings]

FIG. 1 is a conceptual plan view showing a first embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a conceptual plan view showing a second embodiment of the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a conceptual plan view of a semiconductor integrated circuit device for explaining a conventional technique.

[Explanation of symbols]

 1, 21 ... Scribe line 2, 22 ... Input / output terminal 3, 23 ... Negative logic operation circuit 4, 24 ... Self-excited oscillation circuit for delay time measurement 5, 25 ... Internal element region 6, 26 ... Chip 11 ... First Region 12 ... Second region 13 ... Third region 14 ... Fourth region 41 ... First delay time measuring self-excited oscillation circuit 42 ... Second delay time measuring self-excited oscillation circuit 43 ... Third Self-oscillation circuit for delay time measurement 44 ... Fourth self-oscillation circuit for delay time measurement

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having a delay time measuring automatic oscillation circuit therein, wherein a negative logic operation circuit constituting the delay time measuring oscillation circuit is arranged on an outer peripheral portion of a semiconductor integrated circuit chip, Alternatively, the semiconductor integrated circuit device is characterized in that each block of the semiconductor integrated circuit divided into two or more is arranged around the block so as to surround the entire block. 2. The semiconductor integrated circuit device according to claim 1, further comprising a part of the configuration of the NOT logic operation circuit arranged inside the chip in addition to the peripheral part.