JPH05190308A - Multiple chip resistor - Google Patents

Multiple chip resistor

Info

Publication number
JPH05190308A
JPH05190308A JP4006279A JP627992A JPH05190308A JP H05190308 A JPH05190308 A JP H05190308A JP 4006279 A JP4006279 A JP 4006279A JP 627992 A JP627992 A JP 627992A JP H05190308 A JPH05190308 A JP H05190308A
Authority
JP
Japan
Prior art keywords
multiple chip
terminal
terminal electrodes
insulating substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4006279A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yamada
博之 山田
Akio Fukuoka
章夫 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4006279A priority Critical patent/JPH05190308A/en
Publication of JPH05190308A publication Critical patent/JPH05190308A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To allow easy production by using a conventionally used simple structure insulating board. CONSTITUTION:A plurality of resistance films 3 are formed on the top plane of a rectangular insulating board 2 and a plurality of terminal electrodes 4 and 5 connected with the resistance films 3 are formed on the facing edges of the insulating board 2. The pitch of the terminal electrodes on the facing edges of the insulating board 2 is permitted to be the almost double pitch of the wiring pattern on a wiring board on which the multiple chip resistor is to be installed, the terminal electrode on the one edge and the terminal electrode on the other edge are formed with the positional deviation of approximately the wiring pattern pitch and the terminal electrode structure on the one edge 4 is permitted to be a recessed electrode and the terminal electrode structure on the other edge 5 is permitted to be a protruding electrode.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、方形の絶縁基板の上面
に複数個の抵抗膜を形成した多連チップ抵抗器に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple chip resistor having a plurality of resistive films formed on the upper surface of a rectangular insulating substrate.

【0002】[0002]

【従来の技術】従来、この種の多連チップ抵抗器は、例
えば図4に示すように構成されている。この多連チップ
抵抗器20は、アルミナ等からなる方形の絶縁基板21
の上面に複数個の抵抗膜22を横に並べて形成するとと
もに、その絶縁基板21の対向する両端縁の向かい合う
位置に抵抗膜22に接続された端子電極23,24をそ
れぞれ形成し、その絶縁基板21の対向する両端縁の端
子電極23,24のピッチをこの多連チップ抵抗器20
を取り付ける配線基板の配線パターンピッチの2倍かあ
るいはそれに近似した値にするとともに、一方の端縁側
の端子電極23と他方の端縁側の端子電極24とを互い
に配線パターンピッチあるいはそれに近似した値だけ位
置をずらせて形成したものである。そのため、例えば図
5に示すように端子電極23,24を接続するための配
線パターン8,9を同じ方向に引き伸ばして形成する場
合に、一方の端縁側の端子電極23を接続する隣合う配
線パターン8a,8b間に、他の端縁側の端子電極24
を接続する配線パターン9aを形成することができるよ
うになる。すなわち、この場合の配線パターン8a,9
a,8b,9b間のピッチは、半導体ICを取り付ける
配線パターンに等しいかあるいはそれに近似した値とな
る。この図5に示す配線パターン8a,8b,9a,9
bは、すべて同じ方向に伸びるように形成されたもので
あるが、例えば図6に示すように、配線パターン8a,
8b,9a,9bが互いに逆方向に伸びるように形成さ
れている場合には、隣合う配線パターン8a,8b間お
よび10a,10b間に別の配線パターン11aを形成
することができるようになり、配線基板の配線パターン
密度を大きくすることができるという利点がある。
2. Description of the Related Art Conventionally, this type of multiple chip resistor is constructed, for example, as shown in FIG. This multiple chip resistor 20 includes a rectangular insulating substrate 21 made of alumina or the like.
A plurality of resistive films 22 are formed side by side on the upper surface of the insulating substrate 21, and terminal electrodes 23 and 24 connected to the resistive film 22 are formed at opposite ends of the insulating substrate 21, respectively. The pitch of the terminal electrodes 23 and 24 at the opposite end edges of the multi-chip resistor 20
The wiring pattern pitch of the wiring board on which the wiring board is attached or a value close to the wiring pattern pitch, and the terminal electrode 23 on one edge side and the terminal electrode 24 on the other edge side are the wiring pattern pitch or a value close to it. It is formed by shifting the position. Therefore, for example, when the wiring patterns 8 and 9 for connecting the terminal electrodes 23 and 24 are extended and formed in the same direction as shown in FIG. 5, adjacent wiring patterns connecting the terminal electrodes 23 on one edge side are formed. Terminal electrodes 24 on the other edge side between 8a and 8b
It becomes possible to form the wiring pattern 9a for connecting to each other. That is, the wiring patterns 8a and 9 in this case
The pitch between a, 8b and 9b is equal to or close to the wiring pattern for mounting the semiconductor IC. The wiring patterns 8a, 8b, 9a, 9 shown in FIG.
Although all b are formed so as to extend in the same direction, for example, as shown in FIG. 6, the wiring patterns 8a,
When 8b, 9a and 9b are formed so as to extend in mutually opposite directions, another wiring pattern 11a can be formed between adjacent wiring patterns 8a and 8b and between 10a and 10b. There is an advantage that the wiring pattern density of the wiring board can be increased.

【0003】また、図4に示す多連チップ抵抗器では、
端子電極23,24は図示していないが、それぞれ絶縁
基板21の側面および下面にも連続して形成されてい
る。また、図示していないが、絶縁基板21の上面には
抵抗膜22を覆うようにグレーズ材料からなる保護膜が
設けられている。なお、絶縁基板21の対向する両端縁
の隣合う端子電極23,23間及び24,24間には凹
溝25,26がそれぞれ形成され、端子電極23,24
を配線基板の配線パターンにはんだ付けしたときに、隣
合う端子電極間がはんだで短絡しないようになってい
る。
Further, in the multiple chip resistor shown in FIG. 4,
Although not shown, the terminal electrodes 23 and 24 are also continuously formed on the side surface and the lower surface of the insulating substrate 21, respectively. Although not shown, a protective film made of a glaze material is provided on the upper surface of the insulating substrate 21 so as to cover the resistance film 22. It should be noted that recessed grooves 25 and 26 are formed between the terminal electrodes 23 and 23 and 24 and 24 which are adjacent to each other on opposite ends of the insulating substrate 21, respectively.
When is soldered to the wiring pattern of the wiring board, the adjacent terminal electrodes are prevented from being short-circuited by the solder.

【0004】[0004]

【発明が解決しようとする課題】上記のように構成され
る多連チップ抵抗器20は、一般に大版の絶縁基板に同
時に複数の多連チップ抵抗器20を形成するシート工法
により製造される。図7は、従来の大版の絶縁基板にお
ける一部分での隣合う多連チップ抵抗器20,20′の
配置を示す平面図である。
The multiple chip resistor 20 constructed as described above is generally manufactured by a sheet method in which a plurality of multiple chip resistors 20 are simultaneously formed on a large-sized insulating substrate. FIG. 7 is a plan view showing an arrangement of adjacent multiple chip resistors 20 and 20 'in a part of a conventional large-sized insulating substrate.

【0005】このような方法を採用する場合、端子電極
23,24はずらせて形成しており、一枚の絶縁基板で
の取れ数をできるだけ多くし生産性をあげるには、凹溝
25,26を隣合う多連チップ抵抗器20′の凹溝2
5′,26′と共通して配置しなければならない。この
場合、端子電極23と23′あるいは24と24′が隣
合うように配置され、通常23,24間の複数の抵抗膜
22を同時に抵抗値修正する際に端子電極23,24上
に抵抗値計測用の検針を立て、修正後W寸法側に検針を
ステップ移動させ23′,24′間の複数の抵抗値2
2′を修正するが、単純にステップ移動したのでは、2
4に接触していた検針は23′に接触をすることができ
ないため、機械的に補正する必要が生じる。また、多連
チップ抵抗器20と20′は電極の配置が線対称とな
り、完成抵抗値計測および実装の際に方向性の制約が生
じ、不都合となる。
When such a method is adopted, the terminal electrodes 23 and 24 are formed so as to be offset from each other, and in order to maximize the number to be taken in one insulating substrate and improve the productivity, the concave grooves 25 and 26 are provided. The groove 2 of the multiple chip resistors 20 'adjacent to each other
Must be placed in common with 5 ', 26'. In this case, the terminal electrodes 23 and 23 'or 24 and 24' are arranged so as to be adjacent to each other, and when the resistance values of the plurality of resistance films 22 between 23 and 24 are simultaneously corrected, the resistance values on the terminal electrodes 23 and 24 are usually adjusted. Set up the meter for measurement, and after correction, move the meter to the W dimension side stepwise.
Correct 2 ', but if you simply move step 2
The meter that was in contact with 4 cannot contact 23 ', so it is necessary to make mechanical correction. Further, the electrodes of the multiple chip resistors 20 and 20 'are arranged in line symmetry, which limits the directionality of the completed resistance value measurement and mounting, which is inconvenient.

【0006】また、抵抗値修正の際に検針を単純にステ
ップ移動させようとすると、図8に示すように多連チッ
プ抵抗器20,20′を配置し、その間を接続する部分
27を設けざるを得ないため、絶縁基板での取れ数が少
ないにもかかわらず、凹溝25,26を設けるための基
板の加工が多くなり、生産コスト高になるという問題が
生じる。
If the meter reading is simply moved in steps when the resistance value is corrected, multiple chip resistors 20 and 20 'are arranged as shown in FIG. 8 and a portion 27 for connecting them is provided. Therefore, although the number of insulating substrates to be taken is small, the number of processing of the substrate for providing the concave grooves 25 and 26 increases, which causes a problem of high production cost.

【0007】本発明は、このような課題を解決するもの
で、従来から一般に多連チップ抵抗器に使用されている
構造の絶縁基板を使用して、容易に製造することができ
る多連チップ抵抗器を提供することを目的としている。
The present invention solves such a problem, and can be easily manufactured by using an insulating substrate having a structure conventionally used for a multiple chip resistor. The purpose is to provide a vessel.

【0008】[0008]

【課題を解決するための手段】このような目的を達成す
るために、本発明の多連チップ抵抗器は、方形の絶縁基
板の上面に複数個の抵抗膜を形成するとともに、その絶
縁基板の対向する両端縁に抵抗膜と接続された複数個の
端子電極をそれぞれ形成することにより構成され、その
絶縁基板の対向する両端縁の端子電極のピッチをこの多
連チップ抵抗器を取り付ける配線基板の配線パターンピ
ッチの2倍かあるいはそれに近似した値にするととも
に、一方の端縁側の端子電極と他方の端縁側の端子電極
とを互いに配線パターンピッチあるいはそれに近似した
値だけ位置をずらせて形成し、かつ一方の端縁側の端子
電極構造を凹電極、他方の端縁側の端子電極構造を凸電
極として形成したものである。
In order to achieve such an object, the multiple chip resistor of the present invention has a plurality of resistive films formed on the upper surface of a rectangular insulating substrate, and the insulating substrate It is configured by forming a plurality of terminal electrodes respectively connected to the resistance film on the opposite end edges, and the pitch of the terminal electrodes on the opposite end edges of the insulating substrate is set to the wiring board to which this multiple chip resistor is attached. The wiring pattern pitch is set to be twice the wiring pattern pitch or a value close to the wiring pattern pitch, and the terminal electrodes on one edge side and the terminal electrodes on the other edge side are formed so as to be displaced from each other by the wiring pattern pitch or a value close thereto. In addition, the terminal electrode structure on one edge side is formed as a concave electrode, and the terminal electrode structure on the other edge side is formed as a convex electrode.

【0009】[0009]

【作用】従来から一般に多連チップ抵抗器に使用されて
いる構造の絶縁基板を使用し、従来の抵抗値修正の方法
を変更することなく製造することができる。そのため、
多連チップ抵抗器を簡単にかつ安価に形成することがで
きるようになる。
It is possible to manufacture an insulating substrate having a structure which has been conventionally used for a multiple chip resistor without changing the conventional method of correcting the resistance value. for that reason,
The multiple chip resistors can be easily formed at low cost.

【0010】[0010]

【実施例】以下、本発明の一実施例を図面を用いて説明
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0011】図1は、本発明の一実施例による多連チッ
プ抵抗器の平面図であり、図2はその断面側面図であ
る。
FIG. 1 is a plan view of a multiple chip resistor according to an embodiment of the present invention, and FIG. 2 is a sectional side view thereof.

【0012】これらの図において、多連チップ抵抗器1
は、アルミナ等からなる方形の絶縁基板2の上面に形成
された複数個の抵抗膜3と、この抵抗膜3に接続され、
絶縁基板2の対向する両端縁に形成されたそれぞれ複数
個の端子電極4,5とから構成されている。これらの端
子電極4,5は、例えばAg,Ag−Pd,Cu等の電
極ペーストが印刷され、焼成されて形成されており、隣
合う端子電極4、4間および5、5間のピッチPは、こ
の多連チップ抵抗器1を取り付ける配線基板に形成され
た配線パターンピッチの2倍かあるいはそれに近似した
値に設定されている。また、一方の端縁側の端子電極4
と他方の端縁側の端子電極5は、その位置が配線パター
ンピッチあるいはそれに近似した値だけ位置をずらせて
形成されている。すなわち、一方の端縁側の端子電極4
は他方の端縁側の隣合う端子電極5、5間に、また他方
の端縁側の端子電極5は一方の端縁側の隣合う端子電極
4、4間に位置するような関係になっている。また、そ
れぞれの端子電極4,5は、絶縁基板2の側面及び下面
にも連続して形成され、その上面側の先端部分がL型に
形成されて互いに対となる端子電極4,5どうしが対向
するような形状になっている。抵抗膜3は、例えば酸化
ルテニウム等のサーメット抵抗ペーストが端子電極4,
5の先端部分間にまたがって印刷され焼成されて形成さ
れている。絶縁基板2の両端縁の端子電極のうち、端子
電極4部分はスルーホール電極による凹電極でその両側
には凸部6が、端子電極5部分は凸電極でその両側には
凹溝7がそれぞれ形成されている。さらに、図示はして
いないが、絶縁基板2の上面には抵抗膜3を覆うように
グレーズ材料等からなる保護膜が形成される。
In these figures, multiple chip resistors 1
Is a plurality of resistance films 3 formed on the upper surface of a rectangular insulating substrate 2 made of alumina or the like, and connected to the resistance film 3.
The insulating substrate 2 is composed of a plurality of terminal electrodes 4 and 5 formed on opposite edges of the insulating substrate 2. These terminal electrodes 4 and 5 are formed by printing an electrode paste of Ag, Ag-Pd, Cu or the like and firing them. The pitch P between adjacent terminal electrodes 4, 4 and 5, 5 is The wiring pattern pitch formed on the wiring board to which the multiple chip resistor 1 is attached is set to a value twice or close to the wiring pattern pitch. In addition, the terminal electrode 4 on one edge side
The terminal electrodes 5 on the other edge side are formed such that their positions are displaced by the wiring pattern pitch or a value close thereto. That is, the terminal electrode 4 on one edge side
Is positioned between the adjacent terminal electrodes 5 and 5 on the other edge side, and the terminal electrode 5 on the other edge side is positioned between the adjacent terminal electrodes 4 and 4 on the one edge side. Further, the respective terminal electrodes 4, 5 are continuously formed on the side surface and the lower surface of the insulating substrate 2, and the tip portions on the upper surface side thereof are formed in an L shape so that the terminal electrodes 4, 5 forming a pair are connected to each other. It is shaped so as to face each other. For the resistance film 3, for example, a cermet resistance paste such as ruthenium oxide is used for the terminal electrodes 4,
It is formed by printing across the tip portions of 5 and firing. Of the terminal electrodes on both edges of the insulating substrate 2, the terminal electrode 4 portion is a concave electrode formed by a through-hole electrode and has convex portions 6 on both sides thereof, and the terminal electrode 5 portion is a convex electrode having concave grooves 7 on both sides thereof. Has been formed. Further, although not shown, a protective film made of a glaze material or the like is formed on the upper surface of the insulating substrate 2 so as to cover the resistive film 3.

【0013】なお、絶縁基板2の対向する両端縁間の寸
法Wは、配線基板への取付の関係で端子電極4,5間の
ピッチPに合わせておくことが望ましい。
Incidentally, it is desirable that the dimension W between the opposite edges of the insulating substrate 2 is set to the pitch P between the terminal electrodes 4 and 5 in relation to the mounting on the wiring substrate.

【0014】このように構成された多連チップ抵抗器1
は、従来の多連チップ抵抗器に一般に使用されていた等
間隔ピッチの凹溝7および凹電極の端子電極4を有する
絶縁基板により構成される。そのため、抵抗値修正工程
において、端子電極5,6に抵抗値計測用の検針を立
て、修正後W寸法側に単純にステップ移動して隣合って
配置された多連チップ抵抗器を抵抗値修正することがで
きるようになり、機械的に補正をかける必要がなくな
る。ただし、このとき隣合う多連チップ抵抗器の凸電極
の端子電極5と凹電極の端子電極4は、印刷形成時に電
気的に接続されないことが必要である。
The multiple chip resistor 1 thus constructed
Is composed of an insulating substrate having concave grooves 7 with an equal pitch and a terminal electrode 4 of a concave electrode, which are generally used in a conventional multiple chip resistor. Therefore, in the resistance value correction process, a meter for resistance value measurement is set up on the terminal electrodes 5 and 6, and after correction, simply step-moves to the W dimension side to correct the resistance value of the multiple chip resistors arranged next to each other. It becomes possible to do so, and it is not necessary to make a mechanical correction. However, at this time, it is necessary that the terminal electrode 5 of the convex electrode and the terminal electrode 4 of the concave electrode of the adjacent multiple chip resistors are not electrically connected at the time of printing formation.

【0015】なお、本発明の多連チップ抵抗器は上記の
実施例のものに限らず、例えば、図3に示すような構成
とすることもできる。
The multiple chip resistor of the present invention is not limited to that of the above-described embodiment, but may have the structure shown in FIG. 3, for example.

【0016】この図3に示す多連チップ抵抗器11は、
絶縁基板2上面の中央長手方向に両端部の端子電極4,
5間に接続された共通電極12を形成し、抵抗膜3を端
子電極4,5と共通電極13とにまたがって形成したも
のである。
The multiple chip resistor 11 shown in FIG.
Terminal electrodes 4 at both ends in the central longitudinal direction on the upper surface of the insulating substrate 2
The common electrode 12 connected between the electrodes 5 is formed, and the resistance film 3 is formed so as to extend over the terminal electrodes 4 and 5 and the common electrode 13.

【0017】さらには、抵抗膜3と端子電極4,5との
接続態様はその他にも種々あり、本発明の多連チップ抵
抗器はそれらのすべてを含むものである。
Furthermore, there are various other modes of connection between the resistance film 3 and the terminal electrodes 4 and 5, and the multiple chip resistor of the present invention includes all of them.

【0018】[0018]

【発明の効果】以上の説明から明らかなように本発明に
よれば、絶縁基板の対向する両端縁の端子電極の一方の
端縁側の端子電極構造を凹電極、他方の端縁側の端子電
極構造を凸電極としたことにより、絶縁基板の構造が簡
単となり、抵抗値修正工程が容易に行うことが可能とな
る。
As is apparent from the above description, according to the present invention, the terminal electrode structure on one edge side of the terminal electrodes on opposite edges of the insulating substrate is a concave electrode and the terminal electrode structure on the other edge side. By using as the convex electrode, the structure of the insulating substrate is simplified, and the resistance value correction process can be easily performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例による多連チップ抵抗器の平
面図
FIG. 1 is a plan view of a multiple chip resistor according to an embodiment of the present invention.

【図2】本発明の一実施例による多連チップ抵抗器の断
面側面図
FIG. 2 is a sectional side view of a multiple chip resistor according to an embodiment of the present invention.

【図3】本発明の他の実施例による多連チップ抵抗器の
平面図
FIG. 3 is a plan view of a multiple chip resistor according to another embodiment of the present invention.

【図4】従来の多連チップ抵抗器の平面図FIG. 4 is a plan view of a conventional multiple chip resistor.

【図5】本発明による多連チップ抵抗器を取り付ける配
線基板の配線パターン図
FIG. 5 is a wiring pattern diagram of a wiring board to which the multiple chip resistor according to the present invention is attached.

【図6】本発明による多連チップ抵抗器を取り付ける配
線基板の配線パターン図
FIG. 6 is a wiring pattern diagram of a wiring board to which the multiple chip resistor according to the present invention is attached.

【図7】従来の隣合う多連チップ抵抗器の配置を示す平
面図
FIG. 7 is a plan view showing the arrangement of conventional multiple chip resistors adjacent to each other.

【図8】従来の隣合う多連チップ抵抗器の配置を示す平
面図
FIG. 8 is a plan view showing an arrangement of conventional adjacent multiple chip resistors.

【符号の説明】[Explanation of symbols]

1 多連チップ抵抗器 2 絶縁基板 3 抵抗膜 4 スルーホール電極による凹電極の端子電極 5 凸電極による端子電極 6 凸部 7 凹溝 1 Multiple Chip Resistors 2 Insulating Substrate 3 Resistive Film 4 Terminal Electrode of Recessed Electrode with Through Hole Electrode 5 Terminal Electrode with Convex Electrode 6 Convex 7 Recessed Groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】方形の絶縁基板の上面に複数個の抵抗膜を
形成するとともに、その絶縁基板の対向する両端縁に抵
抗膜と接続された複数個の端子電極をそれぞれ形成する
ことにより構成され、かつその絶縁基板の対向する両端
縁の端子電極のピッチをこの多連チップ抵抗器を取り付
ける配線基板の配線パターンピッチの2倍かあるいはそ
れに近似した値にするとともに、一方の端縁側の端子電
極と他方の端縁側の端子電極とを互いに配線パターンピ
ッチあるいはそれに近似した値だけ位置をずらせて形成
し、かつ一方の端縁側の端子電極構造を凹電極、他方の
端縁側の端子電極構造を凸電極としたことを特徴とする
多連チップ抵抗器。
1. A rectangular insulating substrate is formed with a plurality of resistive films on the upper surface thereof, and a plurality of terminal electrodes connected to the resistive films are formed on opposite end edges of the insulating substrate, respectively. And, the pitch of the terminal electrodes on both opposite edges of the insulating substrate is set to a value twice or close to the wiring pattern pitch of the wiring board on which the multiple chip resistor is mounted, and the terminal electrodes on one edge side And the terminal electrode on the other edge side are formed with their positions shifted by the wiring pattern pitch or a value close thereto, and the terminal electrode structure on one edge side is a concave electrode and the terminal electrode structure on the other edge side is a convex shape. A multiple chip resistor characterized by using electrodes.
JP4006279A 1992-01-17 1992-01-17 Multiple chip resistor Pending JPH05190308A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4006279A JPH05190308A (en) 1992-01-17 1992-01-17 Multiple chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4006279A JPH05190308A (en) 1992-01-17 1992-01-17 Multiple chip resistor

Publications (1)

Publication Number Publication Date
JPH05190308A true JPH05190308A (en) 1993-07-30

Family

ID=11633965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4006279A Pending JPH05190308A (en) 1992-01-17 1992-01-17 Multiple chip resistor

Country Status (1)

Country Link
JP (1) JPH05190308A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043717A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Electronic parts and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043717A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Electronic parts and its manufacturing method
JP4547781B2 (en) * 2000-07-28 2010-09-22 パナソニック株式会社 Method for manufacturing multiple chip resistors

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