JPH05189984A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To perform write before erasure in a short time in a nonvolatile semiconductor memory device capable of performing electrical rewrite and comprehensive erasure. CONSTITUTION:An address buffer 11 and a decoder 12 select two bit lines (or word lines) out of four bit lines (or word lines) simultaneously when data of prescribed value is written on all the transistor cells before data erasure. In other words. when a power save signal PD is set at 'L'. and a signal XERHS at 'L', and addresses N, M at 'H', respectively, (1) and (3) go to 'H', and the bit lines connected to them can be selected simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device which can be electrically rewritten and erased collectively.

As an electrically rewritable non-volatile semiconductor memory device, an EEPROM (Electrically Erasabl) is used.
There is known an e programmable read only memory) or a flash memory configured to erase a large number of cell information at once. This non-volatile semiconductor memory device has an overall configuration as shown in FIG. 4, for example. In the figure, N pieces as the cell block comprising a plurality of transistor cells indicated by 71 ₁ -71 _N (eg 8) are arranged in parallel, bit selection for each of the cell blocks 71 ₁ -71 _N Circuit 72 _1-
72 _N and sense amplifier and write buffer 73 _{1 to} 73
_N is provided separately.

A row address signal obtained from a row address buffer 74 through a row decoder 75 is commonly supplied to the cell blocks 71 _{1 to} 71 _N. The bit selection circuit 72 ₁ to 72 _N column address signals obtained through the column address decoder 77 from the column address buffer 76 in common is provided. Further, the voltage V _S from the source power supply circuit 78 and the source electrode of each transistor cell in the cell block 71 ₁ -71 _N are commonly applied.

FIG. 5 shows one cell block 71 of the non-volatile semiconductor memory device and its peripheral circuit section. In the figure, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. In FIG. 5, the bit selection circuit 72 comprises N-channel MOS field effect transistors Q _{1 to} Q _n ,
Column address signals Y _{1 to} Y _n from the column decoder 77 are applied to the gates of the respective transistors Q _{1 to} Q _n .

Further, one cell block 71 has a floating gate and a control gate and has a total of n.
A row decoder 7 is provided at each gate of n transistors Q _{i1 to} Q _in (where i = 1, 2, ..., N) which are composed of × n field effect transistors Q _{11 to} Q _nn and are arranged in the row direction.
The row address signal X _i from 5 is applied via the word line.

The drains of the n transistors Q _{1i to} Q _ni arranged in the column direction are connected to the drains of the transistors Q _i in the bit selection circuit 72 via bit lines. Voltage from the source power supply circuit 78 is applied to further the sources of the transistors Q ₁₁ to Q _nn. Also,
Sense amplifiers 73a, writeback 73b are commonly connected to the sources of the transistors Q ₁ to Q _n.

In such a semiconductor memory device, by selecting the row address X _i and the column address Y _j at the time of writing, each one of the cell blocks 71 _{1 to} 71 _N is selected.
The data from the write buffer 73 is written in the individual transistors Q _ij . That is, writing is performed simultaneously for each bit of the cell blocks 71 _{1 to} 71 _N designated by the row address signal and the column address signal, that is, N bits in total. On the other hand, erasing of data is performed collectively for all the transistors of all the cell blocks 71 ₁ -71 _N.

The above batch erasable nonvolatile semiconductor memory device
When erasing (flash memory), it becomes a memory cell
MOSFET depletion, Iwayu
In order to prevent excessive erasure,
All cell block 71 ₁~ 71_NAll tran
I have to write about this
It is necessary to do it in the shortest possible time.

[0009]

2. Description of the Related Art Each of the cell blocks 71 _{1 to} 71 _N of the nonvolatile semiconductor memory device shown in FIG. 4 is composed of n × n transistors Q _{11 to} Q _nn , which are n × n in number, as described above. Of the transistor cell of. The structure of one transistor cell is as shown in FIG.
1, N-type diffusion regions 82 and 83 are formed at a certain interval, a floating gate (FG) 84 and a control gate (CG) 85 are formed above the P-type substrate 81, and these are further formed as an oxide film 86. It is a structure formed by coating. Further, the source electrode 8 is formed in the N-type diffusion regions 82 and 83.
7 and the drain electrode 89 are connected, and the gate electrode 88 is connected to the control gate 85.

To erase (write "1") to this transistor cell, a high voltage is applied to the source electrode 87, zero V is applied to the gate electrode 88, and the drain electrode 89 is opened. This is performed by extracting the electrons accumulated in the floating gate 84.

Here, "0" is added to the above transistor cell.
Is written, that is, when electrons are accumulated in the floating gate 84, the threshold value of the cell is lowered as indicated by I in FIG. 7, and the data “1” is determined by the erase time T. Erase is completed when the threshold level is reached.

On the other hand, when "1" is written in the above transistor cell, that is, when electrons are not accumulated in the floating gate 84, the threshold level is originally low, so that the above erase operation is performed. As a result, the threshold value of the cell decreases as indicated by II in FIG. 7, so that the threshold level becomes "0" in a shorter time than the erase time T. Therefore, in the transistor cell in which "1" is written, electrons are excessively extracted due to the above erasing, and the transistor cell is in a normally-on state.

[0013] Such to prevent over-erase, all before erasure when collective erasure cell block 71 _1-7
It is necessary to write data "0" in the 1 _N transistor cell. The writing of the data “0” is performed for all the transistor cells without discriminating the value of the data written in the transistor cells. That is, the source electrode 87 of the transistor cell shown in FIG.
The source voltage V _S to the gate electrode 88 is set to 0 V, the gate voltage V _g to the gate electrode 88 is set to a high voltage, and the drain voltage V _D to the drain electrode 89 is set to a high voltage. High-energy electrons generated by applying a high voltage reach the floating gate 84 through the oxide film 86 and are accumulated therein. In this way, the data "0" is written in the transistor cell.

[0014]

However, conventionally, the above-mentioned writing before erasing is performed in order of one bit for each of the cell blocks 71 _{1 to} 71 _{N in} the same manner as the above-mentioned writing of the normal data "0". N = for doing
In the case of 8, it takes about 1.2 seconds to write all the bits of the 1-megabit memory. On the other hand, considering that the time required for batch erasing is about 1 second, there is a problem that the writing time is long with respect to the entire data erasing time and the erasing cannot be performed efficiently.

The present invention has been made in view of the above points,
An object of the present invention is to provide a non-volatile semiconductor memory device capable of performing writing before erasing in a short time.

[0016]

According to a first aspect of the present invention, at least one of all bit lines and all word lines is provided with a plurality of lines when writing a predetermined value of data to all transistor cells before data erasure. A multiple selection circuit for simultaneously selecting is provided.

According to the second aspect of the present invention, a plurality of divided cell blocks to which an address signal is commonly input, and a plurality of divided cell blocks are provided corresponding to each of the divided cell blocks, and data is stored in the divided cell blocks corresponding to the operation. A plurality of write circuits to be written and a write control circuit that activates all of the plurality of write circuits when writing a predetermined value of data to all the transistor cells before erasing data are provided.

According to a third aspect of the invention, a spare cell block and a spare write circuit are further added to the second aspect of the invention, and the write control circuit is provided for each bit line connected to the defective transistor cell. Writing to the transistor cells is prohibited, and the spare write circuit is activated to control writing to the transistor cells in the spare cell block.

[0019]

According to the first aspect of the present invention, at the time of writing before erasing, it is possible to simultaneously write predetermined value data to the multi-valued transistor cells connected to the multiple selected multiple bit lines or word lines. ..

According to the second aspect of the present invention, since each bit line of the plurality of divided cell blocks is simultaneously selected at the time of writing before erasing, data of a predetermined value can be simultaneously written to the plurality of transistor cells. Furthermore, according to the third aspect of the invention, writing to the defective transistor cell is prohibited, and data can be written to the transistor cell in the spare cell block instead of the defective transistor cell.

[0021]

1 is a circuit diagram of a first embodiment of the present invention.
In the figure, 11 is an address buffer and 12 is a decoder. The decoder 12 is the row decoder 75 or the column decoder 77 described above, and similarly, the address buffer 11 corresponds to the row address buffer 74 or the column address buffer 76 described above. Here, for simplicity of explanation, it is assumed that there are four word lines (or bit lines) to be selected.

The address buffer 11 has an address signal N,
2-input NOR to which M and power save signal PD are input
Circuits 111 and 112, inverters 113 and 114 that invert their output signals, an inverter 115, two-input NAND circuits 116 and 117, and an inverter 118. The power save signal PD is set to "H" only when the nonvolatile semiconductor memory device (flash memory in this case) is set to the standby mode, and is set to "L" during operation. The signal XERS input to one input terminal of each of the NAND circuits 116 and 117 is a signal that is set to "L" only at the time of writing before collective erasing.

The decoder 12 is a 2-input NAND circuit 121.
-124 and inverters 125-128. N
The output signal S11 of the NAND circuit 116 is commonly input to the AND circuits 121 and 122, and the NAND circuit 123
The output signal S12 of the NAND circuit 117 is commonly input to the output terminals 124 and 124. In addition, the NAND circuits 121 and 123
The output signal S21 of the inverter 114 is commonly input to the NAND circuits 122 and 124.
8 output signals S22 are commonly input. The address buffer 11 and the decoder 12 described above form a multiplex selection circuit.

The operation of this embodiment will be described. At the time of writing before batch erasing, the power save signal PD is "L",
The address signals N and M are both "H", and the signal XERS is "L". As a result, the respective output signals S11 and S12 of the NAND circuits 116 and 117 become "H", the output signal S21 of the inverter 114 becomes "H", and the output signal S22 of the inverter 118 becomes "L".

Therefore, the output signals of the inverters 125 and 127 become "H", the output signals of the inverters 126 and 128 become "L", and the two word lines connected to the output terminals of the inverters 125 and 127 are connected. (Or bit line) are simultaneously selected.

For example, the selected two word lines are shown in FIG.
Of the row addresses X ₁ and X ₃ are transmitted, the bit line extracted from the column decoder 77 at this time and selected by the column address is
For example, assuming that the bit line is selected by Y _{1, the} data “0” can be simultaneously written in each of the transistors (cells) Q ₁₁ and Q ₃₁ .

On the other hand, the selected two are bit lines,
If the column addresses Y ₁ and Y ₃ (not shown) in FIG. 5 are assumed, the word line selected by the row address at that time is, for example, the word line selected by X _1. Data "0" can be simultaneously written to each of the cells) Q ₁₁ and Q ₁₃ .

In the same manner as described above, the column address (or row address) is sequentially changed in a state where two word lines (or bit lines) are simultaneously selected, and each of the four word lines is connected to the two word lines. After writing the data to a total of eight transistor cells, the address signals N and M are both switched to "L". Then, the output signals of the inverters 125 and 127 become "L", the output signals of the inverters 126 and 128 become "H", and another pair of two connected to the output terminals of the inverters 126 and 128 are connected. Word lines (or the number of bits) are simultaneously selected.

In this state, the column address (or row address) is sequentially changed in the same manner as above,
Data can be written in the remaining eight transistor cells in total. In this way, according to this embodiment, it is possible to write before erasing in half the time of the conventional one.

Of course, the circuit of FIG. 1 may be provided in both the row address buffer 74 and the row decoder 75, and the column address buffer 76 and the column decoder 77. In this case, the writing time before erasing can be further shortened. In the circuit of FIG. 1, since the signal XERS is set to “H” during normal writing, only the output signal of any one of the inverters 125 to 128 is “H”.
Only the word lines (bit lines) of the book are selected. Next, a second embodiment of the present invention will be described. FIG. 2 shows a configuration diagram of a second embodiment of the essential part of the present invention. In FIG. 2, divided cell blocks 21 ₁ and 21 ₂ are blocks obtained by dividing one cell block (71 _{i in} FIG. 4) into two, and the same row address and the same column address are input respectively. . The spare cell block 22 is composed of a plurality of transistor cells redundantly provided for relieving a defective bit (transistor cell). The spare cell block 22 receives a part of the same row address and column address as the input row address of the divided cell blocks 21 ₁ and 21 ₂ .

Divided cell block 21₁And 21₂To each
Write circuit 23 in a one-to-one correspondence ₁, And 23₂Set up
And spare corresponding to the spare cell block 22
A write circuit 24 for writing is provided. Writing circuit 2
Three₁And 23₂The spare write circuit 24 is described above.
It corresponds to the write buffer 73b. In addition, write control
The circuit 25 is a writing circuit 23₁And 23₂And spare books
A circuit that controls the operation of the write-in circuit 24.
23₁And 23₂Write inhibit signals WD1 and XW respectively
D1 is supplied, and the spare write circuit 24 and N
Channel MOS field effect transistor Q₁₃The gate of
And an operation control signal RED is supplied to each. Also, the signal AD
_nAnd XAD_nIs, for example, the address buffer 11 of FIG.
Signals S11 and S12 from can be used. Signal A above
D_nIs the writing circuit 23₁And N-channel MOS type electric
Field effect transistor Q₁₁Supplied to the gates of
The selection signal XADn is the write circuit 23.₂And N
Channel MOS field effect transistor Q₁₂At the gate of
Each is supplied.

The drains of the transistors Q ₁₁ , Q ₁₂ and Q ₁₃ are connected to the divided cell blocks 21 ₁ and 21 ₂ and the spare cell block 22, respectively, while their respective sources are commonly connected to the sense amplifier 26.

The write control circuit 25 described above is shown in FIG.
The circuit configuration is as shown in. In the figure, the defective address storage device 31 shows the position of the defective transistor cell (defective bit line) which is preliminarily inspected and discriminated among a large number of transistor cells forming the divided cell blocks 21 ₁ and 21 _2. The indicated address (that is, defective address) is stored in advance.

Assuming that the output of the defective address storage device 31 has a defective address of (n + 1) bits, each bit output RA _{0 to} RA _{n of} the defective address is a 2-input exclusive NOR circuit (EX-NOR) circuit. The address signal AD ₀ is applied to one of the input terminals 32 _{0 to} 32 _n.
~ AD _n is exclusive-ored. EX-NOR
The output signal of the circuit 32 _n is NANDed with the signal XERS by the 2-input NAND circuit 34 via the inverter 33, and then the EX-N signal is sent to the (n + 1) -input NAND circuit 35.
It is input together with the output signals of the OR circuits 32 _{0 to} 32 _n-1 .

The output signal of the NAND circuit 35 is output as the operation control signal RED through the inverter 36, and is also input to the NAND circuits 38 and 39, where the most significant bits RA _n and R _n of the defective address from the defective address storage device 31 are input. Value XRA that is inverted by the inverter 37
_N and _n are taken respectively. NAND circuits 38 and 3
The respective output signals of 9 are output as the write inhibit signals WD1 and XWD1 through the inverters 40 and 41.

Next, the operation of the embodiment shown in FIGS. 2 and 3 will be described. At the time of writing before collective erasing, the signal XERS is set to "L". Further, when writing to a normal transistor cell when the input address signals (row address and column address) AD _{0 to} AD _n do not match the defective address, the output operation control signal RED of the inverter 36 of FIG.
Is set to "L", so that the write inhibit signal WD1 extracted from the inverter 40 and the write inhibit signal XWD1 extracted from the inverter 41 are both "L".

As a result, the spare write shown in FIG.
The circuit 24 is disabled, and the transistor Q₁₃
Is turned off. In addition, when writing before batch erase,
AD _nAnd XAD_nAre both "H" and the result is
As a result, the writing circuit 23₁And 23₂Are operating
It is said that.

Divided cell block 21₁And 21₂Same as
One address signal (row address and column address)
Is input, it is instructed by the address signal.
Divided cell block 21₁And 21₂Both Transis in
Write circuit 23 in the tacel ₁And 23₂Data from
Are written at the same time. In this way, the divided cell block
21₁And 21₂Simultaneously with each transistor cell of
Then, the data writing is sequentially performed.

By the way, the above is the operation at the normal time when the input address does not match the defective address, but when the input address matches the defective address, N shown in FIG.
Since the output signal of the AND circuit 35 becomes "L", the operation control signal RED extracted from the inverter 36 is "H".
Therefore, the output signal W of the inverters 40 and 41 is
One of D1 and XWD1 is set to "H".

Here, when the most significant bit RA _n of the defective address is “H”, the transistor cell in the divided cell block 21 ₁ is defective, and when RA _n is “L”, the divided cell block 21 1. The transistor cells in ₂ are marked as bad. Therefore, for example, when the transistor cell in the divided cell block 21 ₁ has a defect, the most significant bit RA _n of the defective address is “H”, and therefore the output signals WD1 and WD1 of the inverters 40 and 41 shown in FIG. WD1 of XWD1 is set to "H".

When the signal WD1 becomes "H", the operation of the write circuit 23 ₁ is prohibited. Further, since the operation control signal RED becomes "H", the spare write circuit 24 is activated and the transistor Q ₁₃
Is turned on.

Thus, when a defective address is designated, in the above case, the spare cell block 22 is replaced with the defective address transistor cell in the divided cell block 21 ₁ .
The same predetermined data is simultaneously written into the internal transistor cells together with the transistor cells of the divided cell block 21 ₂ .

It should be noted that during normal writing, only one of the signals AD _n and XAD _n is set to "H", and when the defective addresses do not match, the signal RED is set to "L".
Therefore, only one of the write circuits 23 ₁ and 23 ₂ is activated and data is written to only one of the divided cell blocks 21 ₁ and 21 ₂ .

In this way, by simultaneously writing, for example, four words at the time of writing before collective erasing, it is possible to write to all cells in a time 1/4 times as long as the time of normal writing.

[0045]

As described above, according to the first and second aspects of the present invention, a predetermined value of data is simultaneously applied to a plurality of transistor cells connected to a plurality of multiple selected bit lines or word lines. Since data can be written, the time for writing all bits before batch erasing can be shortened as compared with the conventional case. Further, according to the invention of claim 3, when there is a defective bit at the time of writing all bits before batch erasing. Has a feature that data can be written into a redundant spare cell block in place of a defective bit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a main part of the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the main part of the present invention.

3 is a circuit diagram of an embodiment of a write control circuit in FIG.

FIG. 4 is an overall configuration diagram of a semiconductor memory device to which the present invention is applied.

5 is a circuit diagram of a main part of FIG.

FIG. 6 is a structural diagram of a transistor cell.

FIG. 7 is an explanatory diagram of overerasing.

[Explanation of symbols]

11 Address Buffer 12 Decoder 21 ₁ 21 ₂ Divided Cell Block 22 Spare Cell Block 23 ₁ , 23 ₂ Write Circuit 24 Spare Write Circuit 25 Write Control Circuit 31 Bad Address Memory 711 _{1 to} 71 _N Cell Block Q _{11 to} Q _nn Floating Field effect transistor with gate (transistor cell)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (3)

[Claims] 1. A plurality of word lines are commonly connected to the gates of a plurality of transistor cells (Q _{i1 to} Q _in ) arranged in the row direction, and each of the plurality of bit lines is A plurality of transistor cells (Q
_1j to Q _nj) are commonly respectively connected to the drain of the electric batch erasable non-volatile semiconductor memory device of the data of electrical writing and all transistor cells to any transistor cell, all the transistor cells before data erasure At the time of writing data of a predetermined value to at least one of all the bit lines and all the word lines, the lines are simultaneously selected in a unit of a plurality of lines, and the multiple selected bit lines or word lines are selected. A nonvolatile semiconductor memory device, wherein the predetermined value of data is simultaneously written into a plurality of transistor cells connected to each other. Wherein all of the transistor cells (Q ₁₁ ~
Consists Q _nn) a plurality each transistor cell obtained by dividing a plurality of divided cells block address signal is commonly input (21 _1, 22 _2), the divided cell block (21 _1, 21 ₂ ), A plurality of write circuits (23 ₁ , 23 ₂ ) for writing data to the corresponding divided cell blocks during operation, and a plurality of write circuits (23 ₁ , 23 ₂ ) for normal writing. A write control circuit (25), in which only one circuit is in operation at a time, and each of the plurality of write circuits (23 ₁ , 23 ₂ ) is in operation when data of a predetermined value is written in all the transistor cells before the data is erased. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising: 3. The plurality of divided cell blocks (21 ₁ ,
21 ₂ ) Spare cell block (22) consisting of transistor cells used in place of defective transistor cells
And a spare write circuit (24) provided corresponding to the spare cell block (22), and the write control circuit (25) includes the plurality of write circuits (2).
(3 ₁ , 23 ₂ ) is in an operating state, writing to each transistor cell of the bit line connected to the defective transistor cell is prohibited, and the spare write circuit (2
4) with the spare cell block (22) in the operating state
3. The non-volatile semiconductor memory device according to claim 2, wherein the transistor cell in the memory cell is controlled to perform writing.