JPH05183032A - Aging method of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an effective aging method by comprising an aging signal generating circuit within a semiconductor integrated circuit, forming a wiring for supply electrical power to the semiconductor integrated circuit on a wafer, supplying electrical power simultaneously to a plurality of semiconductor integrated circuits and also operating the aging signal generating circuit. CONSTITUTION:An aging signal generating circuit is comprised within a semiconductor integrated circuit formed on a semiconductor wafer and wirings are also formed to connect power supply terminals VCC and VSS of a plurality of semiconductor integrated circuits formed on such semiconductor wafer. Moreover, the electrical power is supplied to a plurality of semiconductor integrated circuit through such wirings and the aging signal generating circuit is also operated to simultaneously conduct the aging of a plurality of semiconductor integrated circuits on the semiconductor wafer. Thereby, the aging can immediately be done to the integrated circuits formed on the wafer without preparing for an aging board or the like and detection of initial fault can be realized in the initial stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for aging a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Aging is an accelerated test for identifying an initial failure of a device in a semiconductor integrated circuit. The conventional aging method is generally performed by mounting a semiconductor integrated circuit device on an aging board.

[0003]

In the conventional aging method, the semiconductor integrated circuit device is inserted into the IC socket on the aging board, and when the aging is completed, the semiconductor integrated circuit device is taken out from the IC socket and then the aging is performed. This involves a troublesome work of inserting a semiconductor integrated circuit device to be used. Therefore, the inventor of the present application has proposed that a plurality of semiconductor integrated circuits completed on a semiconductor wafer or a film tape (T
AB; T ape A utomated B onding ) thought to be aged at the same time a plurality of semiconductor integrated circuit mounted on a lead frame substrate (semiconductor chip). An object of the present invention is to provide an efficient method for aging a semiconductor integrated circuit device. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor integrated circuit has a built-in aging signal generating circuit, and wiring for supplying power to the semiconductor integrated circuit on the semiconductor wafer or the semiconductor integrated circuit mounted on the TAB substrate is formed, and on the semiconductor wafer or the TAB substrate. Simultaneously supplies power to a plurality of semiconductor integrated circuits and operates the aging signal generation circuit.

[0005]

According to the above means, the semiconductor integrated circuit completed on the semiconductor wafer can be immediately subjected to aging without preparing an aging board or the like, and the initial defects can be washed out at the initial stage. It is possible,
Alternatively, a plurality of semiconductor integrated circuits mounted on the TAB substrate can be simultaneously aged.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a plan view and a partially enlarged view of a semiconductor wafer for explaining an embodiment of an aging method for a semiconductor integrated circuit device according to the present invention. Semiconductor integrated circuits are formed in a grid pattern on the wafer. The boundary portion of each semiconductor integrated circuit is called a scribe line, which is cut after the probing process to separate each semiconductor integrated circuit. In this embodiment, by utilizing this scribe line, although not particularly limited, three lines are formed vertically and horizontally.

That is, as shown in the enlarged view of the figure, a pair of power supply terminals VCC and VSS of the semiconductor integrated circuit are respectively connected to one wiring. A power supply voltage such as 5 V is supplied to the terminal VCC, and the ground potential of the circuit is supplied to VSS. Further, the semiconductor integrated circuit has an aging terminal AGN, and by setting the level thereof to a predetermined level, an aging operation by the aging signal generating circuit as described later is executed.

The wirings formed on the scribe lines on the semiconductor wafer are set as described above in order to supply power and aging control signals to all the semiconductor integrated circuits formed on the wafer at the same time. In order to suppress the power source impedance to be small, it is desirable to form three wirings vertically and horizontally. However, it is necessary to form a multilayer structure at the cross portion of the wiring, which makes manufacturing difficult. Therefore, it is convenient to arrange the three wirings so as to connect the respective semiconductor integrated circuits like a single stroke. For example, in FIG.
Two rows of chips can be connected in parallel by extending from the lower right to the left, extending one chip upward at the left end, and vice versa. And 1 at the right end
The tip is extended upward, and the tip is extended leftward from the tip. After that, all the chips on the wafer can be connected in parallel by repeating similar wiring.

Although not particularly limited, in order to facilitate power supply on the wafer, a relatively large electrode is formed in an extra area where the semiconductor integrated circuit is not formed at the end of the wiring, and a clip-shaped electrode is used. It may be one that enables easy power supply and control signal input.

FIG. 2 shows a block diagram of an embodiment of the semiconductor integrated circuit. In this embodiment, the TFT
(Thin Film Transistor) This is directed to a semiconductor integrated circuit which constitutes a drive circuit of a liquid crystal display panel. For example, a semiconductor integrated circuit such as "HD66107T" sold by Hitachi, Ltd., which forms a drive signal of 160 channels, includes the following aging signal generation circuit.

The oscillator circuit OSC is a pull-up MOS.
A high-level control signal is constantly input by the FET Q while the power supply voltage is being supplied. When the control signal is at the high level, the oscillation operation is stopped, the multiplexer MPX2 transmits the clock CK input from the external terminal to the clock generation circuit CPG by the control signal, and the multiplexer MPX1 outputs the address signal input from the external terminal. Data signal ADD / DAT is transferred to TFTLC
Tell the D driver. That is, in this state, the aging signal generation circuit is in a non-operating state, and the TFT LCD driver performs a normal operation according to the input signal input from the external terminal.

When a low-level control signal is input from the control terminal ANG, the oscillation circuit OSC performs an oscillation operation, and the multiplexer MPX2 supplies the output signal of the frequency divider circuit that receives the oscillation output to the clock pulse generation circuit CPG. As a result, the internal clock pulse required for the operation of the TFTLCD driver is formed by dividing the oscillation output of the oscillation circuit OSC. In addition, in response to the input of a low level control signal from the control terminal ANG,
The multiplexer MPX1 is the clock generation circuit CPG.
The output signal of the counter circuit CNT which receives the output signal of the above is replaced with the regular signal from the external terminal ADD / DAT and is input to the TFT LCD driver as the input signal for aging. That is, in the semiconductor integrated circuit of this embodiment, when power is supplied and the control signal ANG is set to the low level, each circuit of the TFT LCD driver operates to perform aging.

As shown in FIG. 1, for a semiconductor integrated circuit completed in a grid pattern on a wafer, although not particularly limited, power is supplied to VCC and VSS for aging at a high temperature, and AGN is supplied. When a low level such as the ground potential is supplied, all semiconductor integrated circuits operate according to the operation of the built-in aging signal generation circuit. After this, a DC / AC test is performed by probing to wash out defective chips including those that have become initial defects due to aging. If the problem is that the power supply lines are connected in parallel on all chips in the above probing,
Prior to probing, the above wiring may be divided by a laser beam or the like so that the wiring on the scribe line does not pose a problem. Finally, the wiring is divided into individual semiconductor integrated circuits by cutting the scribe line.

FIG. 3 is a plan view of a TAB substrate for explaining another embodiment of the aging method of the semiconductor integrated circuit device according to the present invention. A copper foil is attached to a film tape made of a polyimide resin, and a lead frame is formed in a lead-like pattern by a photoetching technique. The ends of the leads are tin-plated. On the other hand, bumps are provided on the connection electrodes of the semiconductor chip, and the film-shaped lead frame is aligned on the chip, and all the lead inner ends and the chip bumps are put together. Thermocompression bonded TA
A plurality of semiconductor integrated circuits are formed on the B substrate.

On the TAB substrate, in addition to the lead pattern as described above, two wirings VCC and VSS for power supply and one wiring AGN for control are formed. This wiring is connected to the lead corresponding to the corresponding connection electrode of each semiconductor integrated circuit.

As shown in FIG. 3, the semiconductor integrated circuit mounted (bonded) on the TAB substrate is not particularly limited, but power is supplied to VCC and VSS for aging at a high temperature, and to AGN. When a low level such as the ground potential is supplied, all semiconductor integrated circuits operate in accordance with the operation of the built-in aging signal generating circuit, as described above. After this, although not particularly limited, the chip with the inner leads of the film tape bonded is mounted according to the lead pattern on the ceramic substrate, and the lead pattern on the ceramic substrate and the outer lead ends of the film tape are collectively packaged. All the bonding is completed by thermocompression bonding.

The operational effects obtained from the above embodiment are as follows. That is, (1) a wiring for supplying power to the semiconductor integrated circuit on the semiconductor wafer or the semiconductor integrated circuit mounted on the TAB substrate is formed while the aging signal generating circuit is built in the semiconductor integrated circuit, and A plurality of semiconductor integrated circuits are simultaneously supplied with power on the TAB substrate and the aging signal generating circuit is operated. This makes it possible to immediately perform aging on a semiconductor integrated circuit completed on a semiconductor wafer without preparing an aging board or inserting or removing the semiconductor integrated circuit device into or from the IC socket one by one. Yes, initial defects can be washed out at an early stage, or TAB
The effect that the plurality of semiconductor integrated circuits mounted on the substrate can be simultaneously aged is obtained. (2) According to the above (1), since aging can be performed before probing, initial defects can be washed out in the probing process, and the subsequent assembling process can be rationalized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the wiring for supplying power to the semiconductor integrated circuit formed on the semiconductor wafer at the same time may be formed so that a part thereof remains outside the scribe line, in other words, on the semiconductor chip side. The aging signal generation circuit uses an oscillation circuit and a counter circuit, and the input pattern is a ROM.
It is possible to adopt various embodiments such as storing in a memory or the like and repeatedly reading it. The present invention can be widely used as an aging method for semiconductor integrated circuits.

[0019]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor integrated circuit has a built-in aging signal generating circuit, and wiring for supplying power to the semiconductor integrated circuit on the semiconductor wafer or the semiconductor integrated circuit mounted on the TAB substrate is formed, and on the semiconductor wafer or the TAB substrate. Simultaneously supplies power to a plurality of semiconductor integrated circuits and operates the aging signal generation circuit. This will prepare an aging board, etc.
The semiconductor integrated circuit completed on the semiconductor wafer can be immediately subjected to aging without inserting or removing the semiconductor integrated circuit device into or from the C socket one by one, and the initial defects can be washed out in the initial stage. Alternatively, a plurality of semiconductor integrated circuits mounted on the TAB substrate can be simultaneously aged.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor wafer and a partially enlarged view thereof for explaining an embodiment of an aging method for a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a semiconductor integrated circuit in which aging is performed.

FIG. 3 is a plan view of a TAB substrate for explaining another embodiment of the aging method of the semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

MPX1, MPX2 ... Multiplexer, CNT ... Counter circuit, CPG ... Clock pulse generation circuit, OSC ... Oscillation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Akio Hayasaka 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Mobara factory

Claims (5)

[Claims] 1. A semiconductor integrated circuit formed on a semiconductor wafer has an aging signal generating circuit built therein, and a wiring for connecting power supply terminals of a plurality of semiconductor integrated circuits formed on the semiconductor wafer is formed. Then, power is supplied to the plurality of semiconductor integrated circuits through this wiring and the aging signal generating circuit is operated to simultaneously perform aging of the plurality of semiconductor integrated circuits on the semiconductor wafer. .. 2. The method for aging a semiconductor integrated circuit device according to claim 1, wherein the wiring is formed on a scribe line. 3. An aging signal generating circuit is built in a plurality of semiconductor integrated circuits mounted on a lead frame formed on a thin film tape, and power supply terminals of the plurality of semiconductor integrated circuits are provided on the film tape. Forming a wiring for connecting the plurality of semiconductor integrated circuits through the wiring and operating an aging signal generation circuit to simultaneously perform aging of the plurality of semiconductor integrated circuits on the film tape. Method of aging integrated circuit device. 4. The aging signal generation circuit includes an oscillation circuit, a counter circuit that counts pulses formed based on the oscillation signal of the oscillation circuit, and a signal supplied to the semiconductor integrated circuit from its input terminal. 3. A aging method for a semiconductor integrated circuit device according to claim 1, further comprising a multiplexer for transmitting the pulse or the output signal of the counter circuit. 5. The operation of the oscillating circuit and the switching of the multiplexer are performed by supplying a predetermined control signal from the outside, and the wiring for supplying the control signal includes a plurality of semiconductors like the power feeding wiring. The method for aging a semiconductor integrated circuit device according to claim 1 or 3, wherein the integrated circuit devices are formed so as to be connected to each other.