JPH0518197B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a dynamic MOS transistor consisting of one transistor and one capacitor with adjusted operation timing.
It relates to semiconductor storage devices such as RAM (hereinafter referred to as semiconductor memory).

[Prior Art] Since this semiconductor memory is most applicable to an N-channel dynamic MOS/RAM, the following conventional example will be explained regarding this.

FIG. 4 is a circuit diagram around a sense amplifier in a conventional dynamic MOS RAM consisting of one transistor and one capacitor. In the figure, 1 is the X address buffer, (Row Address
When the Strobe signal changes from "H" to "L", it is activated and generates the X address signal 2. Reference numeral 3 denotes an X decoder, which has the role of selecting a word line (not shown) according to the X address signal 2.
4 is a Y address buffer, 5 is a delay circuit, and 5a is a
In the AND gate, (Column Address
Strobe) changes from “H” to “L” and
Delay circuit 5 triggered by address signal 2
When the conditions for the output φ ₁ to change from “L” to “H” are satisfied, the AND gate 5a which is a logic circuit
The output φ _2a changes from "L" to "H" and is activated using this output φ _2a as a trigger to generate a Y address signal. 6 is a delay circuit triggered by the X address signal 2, which generates an output _φ3 .
Reference numeral 7 denotes a sense amplifier drive circuit triggered by this output _φ3 , which generates a slow sense signal _φs1 and a fast sense signal _φs2 . 8 is a MOS transistor whose gate is connected to slow sense signal φ _s1 , drain is connected to sense amplifier source line _s , and source ground (0V), and 9 is a gate connected to fast sense signal φ _s2 . MOS whose drain is connected to the sense amplifier source line _s and whose source is connected to ground
The channel width of the MOS transistor 9 is several ten times larger than that of the MOS transistor 8. 10 is a sense amplifier for detecting the binary information of "0" or "1" stored in the memory cell (not shown), and 11 and 12 are bit lines that detect the binary information stored in the memory cell. The information is first transmitted to these bit lines 11 and 12, and then transmitted to the sense amplifier 10 via the bit lines 11 and 12. 13 and 14 are Y decoders provided close to the sense amplifier 10;
and 14 function as one Y decoder. 15a, 15b, 15c left Y decoder 1
This is a Y address signal line input to bit line 11, and is laid out orthogonally to bit line 11. Similarly, 16a, 16b, and 16c are Y address signal lines input to the right Y decoder 15, which are laid out orthogonally to the bit line 12. Y address signal lines 15a-15c and 16a-16
C is a transmission line for the Y address signal which is the output of the Y address buffer 4, and the Y address buffer 4, Y decoders 13 and 14, and MOS transistors 20 and 21 form a decoder circuit. 17 is an I/O line, 18 is a line, Y
When the outputs 19 of the decoders 13 and 14 are at "H" level (when selected by the Y decoder), the bit line 11 is connected to the I/O through the MOS transistors 20 and 21.
bit line 12 is connected to line 1
Connected to 8. On the other hand, when the outputs 19 of the Y decoders 13 and 14 are at "L" level (when the Y decoders are not selected), the MOS transistors 20 and 21
is off, so bit line 11 and I/O line 1
7 is not electrically connected, and the bit line 12 and I/O line 18 are also not electrically connected.

FIG. 5 is a time chart for explaining the operation of the circuit diagram of FIG. 4.

The circuit around the sensor amplifier 10 of a conventional dynamic MOS/RAM consisting of one transistor and one capacitor is configured as described above, and the signal changes from "H" to "L" at time _t0 in FIG. is triggered, X address buffer 1 is activated and generates X address signal 2. Using the rise of the X address signal 2 as a trigger, an angle signal having two independent time series (Y address time series and sense time series) is generated. One of them is through the delay circuit 5, and the output φ ₁ of the delay circuit 5 changes from "L" to "H" at time t ₁ using the X address signal 2 as a trigger. By time _t2 , the signal has already changed from "H" to "L", so the AND gate 5
The output φ _2a of a rises from "L" to "H" at time t ₂ . Subsequently, at time _t3 , using the AND gate 5a output _φ2a as a trigger, the Y address buffer 4 is activated and a Y address signal is generated. more than time t ₁
The t ₃ sequence from is called the Y address time sequence here.

The other time series passes through the delay circuit 6, and the output φ ₃ of the delay circuit 6 changes from "L" to "H" at time s ₁ using the X address signal 2 as a trigger.
At this time, the word line rises, and a potential difference according to the information in the X memory cell is created between bit line 11 and bit line 12.
occurs between FIG. 5 shows a case where the information of the memory cell connected to the bit line 11 is "0", and a larger voltage drop occurs than that of the bit line 12. However, the potential difference between the bit line 11 and the bit line 12 is several hundred mV at time _s1 .
Very little. At time _s2 , the slow sense signal _φs1 changes from "L" to "H", turning on the MOS transistor 8. Then, the potential of the sense amplifier source line _s starts to drop gradually, and the sense amplifier 10 starts operating. Along with this, time
The slight potential difference occurring between bit line 11 and bit line 12 at _s1 begins to be amplified. Next, at time _s3 , the first sense signal φ _s2
changes from “L” to “H”, turning on the MOS transistor 9. Then, MOS transistor 9
Since the channel width is large, the sense amplifier source line _s begins to fall rapidly and the sense amplifier 10 is strongly activated. Along with this, the bit line 11,
The potential difference between bit lines 12 and 12 is further increased, and finally, at time _s4 , bit line 11 becomes 0V. on the other hand,
Bit line 12 is “H” although there is some voltage drop
maintaining the level. A series of times s ₁ to s ₃ triggered by such an X address signal 2
The period from time _s3 to time _s4 is called the amplification period. Furthermore, here, the series from time s ₁ to s ₄ will be referred to as a sense time series.

Generally, in order to detect the potential difference appearing between the bit line 11 and the bit line 12 with high sensitivity using the sense amplifier 10, it is necessary to detect the difference between the bit line 11 and the bit line 12.
It is important to balance the two as much as possible. In other words, the stray capacitance of the bit line 11
Consideration must be given to making C _BL and the stray capacitance C _BR of the bit line 12 as equal as possible. Furthermore, in the time period from time s ₁ to s ₃ in FIG. 5, the potential difference between bit line 11 and bit line 12 is very small, so they are easily affected by noise mixed into bit lines 11 and 12. It is necessary to reduce noise mixed into the time zone.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory as described above, Y address signal lines 15a to 15c and 16a to 16c
Since a coupling capacitance _C1 exists between the bit lines 11 and 12, the following problem occurs. That is, since the Y address signal either remains "L" or rises from "L" to "H", the Y address signal lines 15a to 1
The amount of capacitively coupled noise mixed into bit line 11 by Y address signal lines 16a to 16c is different from the amount of capacitively coupled noise mixed into bit 12 by Y address signal lines 16a to 16c. Furthermore, as described in the explanation of the operation of the conventional semiconductor memory, since the Y address time series and the sense time series proceed independently, for example, as shown in FIG _. may overlap between the sense periods s ₁ to s ₃ which are most sensitive to noise. Therefore, the sense period s ₁ that is most susceptible to noise
~ s ₃ , an imbalance in the amount of capacitively coupled noise due to the coupling capacitance C ₁ occurs, which may reduce the sensitivity of the sense amplifier 10 or even cause a malfunction of the sense amplifier 10 . There was a problem that there were cases where

The present invention was made to solve this problem, and provides a highly sensitive sense amplifier by preventing capacitive coupling noise from the Y address signal line from entering during the sensing period, which is most susceptible to noise. The purpose is to obtain a semiconductor memory having the following characteristics.

[Means for solving problems]

The semiconductor memory according to the present invention includes a sense amplifier connected to a pair of bit lines to detect and amplify the potential difference appearing on the pair of bit lines, and a sense amplifier that outputs a sense signal for activating the sense amplifier. an amplifier driving means, a decoder circuit that receives an address signal and outputs a signal for selecting the pair of bit lines, and a point in time when the sense signal from the sense amplifier driving means activates the sense amplifier; The device is equipped with a theoretical circuit that outputs a signal for activating the decoder circuit thereafter.

[Effect]

In the present invention, a signal for activating the decoder circuit is output from the logic circuit after the point in time when the sense signal most susceptible to noise activates the sense amplifier.

〔Example〕

FIG. 1 is a circuit diagram around a sense amplifier in a dynamic MOS/RAM consisting of one transistor and one capacitor of a semiconductor memory showing an embodiment of the present invention.
c, 16a to 16c, and 17 to 21 are completely the same as the conventional device shown in FIG. 5b is
In the AND gate, the conditions for the delay circuit 5 and its output φ ₁ to go from "L" to "H", the conditions for the signal to go from "H" to "L", and the signal for activating the sense amplifier 10, that is, Slow sense signal φ _s1 which is the output of the sense amplifier drive circuit 7
The logic is constructed so that when the conditions for changing from "L" to "H" are satisfied, the output φ _2b of the AND gate 5b, which is a theoretical circuit, changes from "L" to "H". Then, the output φ _2b of the AND gate 5b of this logic circuit is used as a trigger to activate the Y address buffer 4.

FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG.

In the circuit surrounding the sense amplifier 10 in the semiconductor memory configured as described above, the second
The operation of the Y address time series from time t ₀ to t ₁ and the operation of the sense time series from time s ₀ to s ₄ in the figure are the same as those of the conventional example shown in FIG. 4. Even if the output φ ₁ of the delay circuit 5 changes from “L” to “H” at time t ₁ , the slow sense signal φ _s1 , which is one of the three inputs of the AND gate 5b, remains “L”.
Therefore, the output φ _2b of the AND gate 5b remains at "L". Next, at time s ₂ of the sense time series, the slow sense signal φ _s1 rises from “L” to “H”, and therefore, at time t ₂ , the output φ _2b of the AND gate 5b changes from “L” to “H”. stand up.
Subsequently, at time _t3 , _φ2b of AND gate 5b is used as a trigger to activate Y address buffer 4,
A Y address signal is generated. As is clear from the above explanation of the operation, the Y address time series and the sense time series do not proceed independently in this embodiment, but are related to each other via the slow sense signal φ _s1 , so that s ₃ <t By satisfying the condition ₃ , it becomes possible to set time t ₃ , which is the rising point of the Y address signal, after the sensing times s ₁ to s ₃ when the sense amplifier 10 is most susceptible to noise. Therefore, the sense period
Between s ₁ and _{s 3} , capacitive coupling noise due to the coupling capacitance C ₁ does not occur, and the sensitivity of the sense amplifier 10 does not decrease.

In addition, in the above embodiment, the output φ ₁ of the delay circuit 5 is “
Conditions for going from “L” to “H” and the signal being “H”
When the conditions for the slow sense signal _φs1 , which is the output of the sense amplifier drive circuit 7, to change from “L” to “H” are both satisfied, the output of the AND gate 5 becomes “L”. _2b changes from “L” to “H”
However, when the fast sense signal φ s2, which is the output of the sense amplifier drive circuit 7, changes from “L” to “H _{” in place of the slow sense signal φ s1 ,} the theoretical circuit is
The output of the AND gate 5b may be configured to change from "L" to "H".

FIG. 3 shows a dynamic MOS transistor consisting of one transistor and one capacitor, showing another embodiment of the present invention.
FIG. 2 is a circuit diagram around a sense amplifier in RAM. In FIG. 3, symbols 1 to 5, 6 to 14, 1
5a to 15c, 16a to 16c, and 17 to 21 are the same as the conventional one shown in FIG. 5
c is an AND gate and the delay circuit 5 and its output φ ₁ 0
The conditions for the signal to go from "L" to "H", the conditions for the signal to go from "H" to "L", and the conditions for the first sense signal φ _s2 , which is the output of the sense amplifier drive circuit 7, to go from "L" to "H". When both conditions are satisfied, the output φ _2c of the AND gate 5c becomes “L”
Since the logic is set up so that the signal goes from "H" to "H", the condition of s ₃ <t ₃ is always satisfied in this embodiment as well. Therefore, the circuit of this embodiment can also be expected to have the same effect as that shown in FIG.

In each of the above embodiments, a dynamic MOS transistor consisting of one N-channel transistor and one capacitor is used.
Although the case of RAM is shown, the case of P channel, CMOS, and other configurations are shown.
Needless to say, this method can also be applied to RAM.

〔Effect of the invention〕

As explained above, the present invention includes a sense amplifier connected to a pair of bit lines to detect and amplify the potential difference appearing on the pair of bit lines, and a sense amplifier that outputs a sense signal to activate the sense amplifier. an amplifier driving means, a decoder circuit that receives an address signal and outputs a signal for selecting the pair of bit lines, and a point in time when the sense signal from the sense amplifier driving means activates the sense amplifier; Since it is equipped with a theoretical circuit that outputs a signal for activating the decoder circuit thereafter, the Y address signal is activated after the sensing period in which the sense amplifier is susceptible to noise has ended, making it easy to This has the effect of preventing the influence of associative noise.

[Brief explanation of drawings]

FIG. 1 shows an IC of an embodiment of the present invention.
Dynamic consisting of a transistor and one capacitor
A circuit diagram around the sense amplifier in MOS/RAM, FIG. 2 is a time chart for explaining the operation of the sense amplifier in the IC of this invention shown in FIG. 1, and FIG. 3 is a circuit showing another embodiment of the invention. Figure 4 is a circuit diagram around the sense amplifier in a dynamic MOS/RAM consisting of one transistor and one capacitor in a conventional IC, and Figure 5 is a circuit diagram around the sense amplifier.
This is a time chart for explaining the operation of the conventional device shown in the figure. In the figure, 1 is the X address buffer, 2 is the
address signal, 3 is an X decoder, 4 is a Y address buffer, 5 is a delay circuit, 5a, 5b, 5c are
AND gate, 6 is a delay circuit, 7 is a sense amplifier drive circuit, 8, 9 are MOS transistors, 10 is a sense amplifier, 11, 12 are bit lines, 13, 1
4 is a Y decoder, 15a, 15b, 15c, 16
a, 16b, 16c are Y address signal lines, 17
is an I/O line, 18 is an I/O line, 19 is an output of the Y decoder, and 20 and 21 are MOS transistors.
Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A sense amplifier connected to a pair of bit lines to detect and amplify the potential difference appearing on the pair of bit lines, and a sense amplifier that outputs a sense signal to activate the sense amplifier. drive means,
a decoder circuit that receives an address signal and outputs a signal for selecting the pair of bit lines; a decoder circuit that receives a sense signal from the sense amplifier driving means; A semiconductor memory device equipped with a theoretical circuit that outputs a signal to activate the circuit. 2. A patent characterized in that the sense signal for activating the sense amplifier is derived from one of the signals different from the sense signal input to the logic circuit for activating the decoder circuit. A semiconductor memory device according to claim 1. 3 The sense signal has two signals, a slow sense signal and a fast sense signal, and the logic circuit has
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device receives a slow sense signal of the sense signal. 4. The sense signal has two values, a slow sense signal and a fast sense signal, and the logic circuit receives the fast sense signal of the sense signal, or 2. The semiconductor memory device according to item 2.