JPH0765580A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device with a decrease in current flowing through a bit line or a sense amplifier. CONSTITUTION:An address change detecting circuit 8 to which an address signal 11 is given is provided. A sensing sensitivity changing means 7 for changing the sensitivity of sensing is connected to a Y selector 32 and a precharge control circuit 51 is connected to a gate electrode of a precharge circuit 5, while an equalization control circuit 61 is connected to a gate electrode of an equalizing circuit 6. The precharge control circuit 51, the equalization control circuit 61 and a latch 73 are given an X address coincidence signal 81 from the address change detecting circuit 8. When there is no change in an address, precharge and equalization are not executed, current consumption with the precharge and the equalization is reduced and the current consumption due to sensing with higher sensitivity than needed can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device with reduced current consumption.

[0002]

2. Description of the Related Art FIG. 12 shows a conventional semiconductor memory device.
FIG. 7 is a circuit diagram in which the 2-port RAM of the 24-bit floating point signal processor mSP2 described in the Proceedings of the Spring National Convention of the Institute of Electronics, Information and Communication Engineers in 1988 is changed to a single-port RAM for convenience of operation explanation. (Proceedings of IEICE Spring National Congress 1988 C-2
75).

Conventionally, in the case of a memory (synchronous storage device) including a logic circuit operating on the same chip in synchronization with a clock, such as a microprocessor, a clock signal is precharged or sensed for ease of timing design. Used for timing control of amplifier enable.

In FIG. 12, a precharge circuit 5 is connected to a memory cell array 4 composed of a plurality of memory cells 41 by a bit line 42 via an equalize circuit 6. Here, the bit line 42 is formed by collecting a plurality of bit line pairs, each pair consisting of two bit lines.

To the memory cell array 4, the Y selector 32 connected to the Y decoder 3 by the Y selector control signal line 31 is connected by the bit line 42, and the Y selector 3 is connected.
2, the sense amplifier 70 and the write driver 9 are I / O.
It is connected by an O line pair 33, and the X decoder 2 is connected by a word line 21. An address latch 1 is connected to the X decoder 2 and the Y decoder 3.

As inputs, a clock signal T0 is applied to the gate electrodes of the precharge circuit 5 and the equalize circuit 6, the address latch 1 and the X decoder 2, the clock signal T2 is applied to the sense amplifier 70, and the write driver is applied. A clock signal T3 is applied to 9. Here, the clock signal T1 is a signal used to secure a period from the rise of the word line 21 to the start of sensing by the sense amplifier 70, and is a signal that is not directly involved in the control of the memory. These clock signals T0 to T3
Are non-overlapping clocks. Address signal 11 is applied to address latch 1. The write data signal 91 is input to the write driver 9. As an output, the output signal 74 is output from the sense amplifier 70.

Next, the operation will be described. This memory operates with non-overlapping 4-phase clocks. Therefore, one access cycle can be divided into four periods in which the clock signals T0, T1, T2 and T3 are applied.

First, during the period in which the clock signal T0 is applied, the precharge circuit 5 is turned on to precharge the bit line 42 and the equalize circuit 6 is supplied.
Is turned on, the bit line 42 is equalized. Precharge and equalization are also performed on the I / O line pair 33 at the same timing. Further, the address is decoded during the period in which the clock signal T0 is applied, the X decoder 2 selects the word line 21, and the Y line is selected.
The decoder 3 selects the Y selector control signal line 31.

The word line 21 operates in synchronization with the clock, rising at the falling edge of the clock signal T0 and falling at the rising edge of T0. When the word line 21 rises, the data in the memory cell 41 connected to the word line 21 is output to the bit line 42. The data output to the bit line 42 enters the sense amplifier 70 via the Y selector 32. The sense amplifier 70 is enabled by the clock signal T2 and outputs the output signal 74.

Data is written during the period of the clock signal T3. During this period, the write driver 9 is enabled, and the data is written to the memory cell 41 on the memory cell array 4 via the Y selector 32 and the bit line 42.

Here, it is assumed that the addresses of the memory cell array 4 are mapped as shown in FIG. The X decoder 2 decodes the upper 10 bits (MSB side) of the address, and the Y decoder 3 decodes the lower 2 bits (LSB side) of the address. If the addresses are 0 to 1, 2, 3, 4
When incremented by ..., Only the address that enters the Y decoder 3 changes from 0 to 3, the address that enters the X decoder 2 does not change, and the address that enters the X decoder 2 changes when the address changes from 3 to 4. The X address does not change from 4 to 7 after that. Thereafter, this operation is repeated.

[0012]

Since the conventional semiconductor memory device such as the synchronous memory device is configured as described above, when the memory is read in the order of address 0 and address 1, the memory cell at address 0 is read. 41 and memory cell 4 at address 1
Since 1s are connected to the same word line 21, the data of the 1st address is also read to the bit line 42 different from the 0th bit line 42 when the 0th address is read. However, when the address 1 is read next time, it is already read 1
The address data is canceled by precharging and equalizing, and the same data is read again. That is, the conventional example has a problem that unnecessary current is consumed by repeating unnecessary precharge and equalization. Further, in the conventional example, when the memory 41 connected to the same word line 21 is continuously read, if the bit line 42 is not initialized by precharging and equalization,
Since the active time of the word line 21 becomes long, the potential amplitude of the bit line 42 becomes large, and if a high-sensitivity sense amplifier is used in accordance with the case where the potential amplitude of the bit line 42 is small, data can be transferred faster than necessary. Will be output. Generally, it is said that the current consumption is reduced when the sensitivity of the sense amplifier is lowered, so that sensing with a sense amplifier having a sensitivity higher than necessary is an act of increasing the current consumption.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device in which the current flowing through a bit line or a sense amplifier is reduced.

[0014]

According to a first aspect of a semiconductor memory device of the present invention, a first decoder selects a word line according to an address signal and a second decoder selects a bit line pair according to the address signal. In a semiconductor memory device including a decoder, a precharge circuit for precharging the bit line pair, and an equalize circuit for equalizing the bit line pair, an address for detecting a change in an address signal decoded by the first decoder. A change detection circuit, and a precharge control circuit and an equalize control circuit that operate the precharge circuit and the equalize circuit when the address change detection circuit detects an address change are provided.

According to a second aspect of the semiconductor memory device of the present invention, a first decoder selects a word line according to an address signal, a second decoder selects a bit line pair according to the address signal, and the bit line. In a semiconductor memory device including a precharge circuit for precharging a pair and an equalize circuit for equalizing the bit line pair, an address change detection circuit for detecting a change in an address signal decoded by the first decoder; A precharge control circuit and an equalize control circuit for operating the precharge circuit and the equalize circuit at the time of detecting an address change of the address change detection circuit, and interlocking with the operation of the precharge control circuit and the equalize control circuit,
And a sense sensitivity changing means for changing the sense sensitivity and amplifying the signal of the bit line pair.

A third aspect of the semiconductor memory device according to the present invention is characterized in that the sense sensitivity changing means comprises two or more sense amplifiers having different sense sensitivities.

A fourth aspect of the semiconductor memory device according to the present invention is characterized in that the sense sensitivity changing means comprises a sense amplifier for changing the sense sensitivity by increasing or decreasing the number of transistors relating to the sense sensitivity. .

According to a fifth aspect of the semiconductor memory device of the present invention, a first decoder for selecting a word line according to an address signal, a second decoder for selecting a bit line according to the address signal, and the bit line are provided. In a semiconductor memory device including a precharge circuit for precharging,
An address change detection circuit that detects a change in the address signal decoded by the first decoder and a precharge control circuit that operates the precharge circuit and the like when the address change detection circuit detects an address change. .

According to a sixth aspect of the semiconductor memory device of the present invention, a first decoder for selecting a word line according to an address signal, a second decoder for selecting a bit line according to the address signal, and the bit line are provided. In a semiconductor memory device including a precharge circuit for precharging,
An address change detection circuit that detects a change in an address signal decoded by the first decoder, a precharge control circuit that operates the precharge circuit when an address change is detected by the address change detection circuit, and the precharge control circuit In conjunction with the operation of, the signal of the bit line,
And a sense sensitivity changing means for changing and amplifying the sense sensitivity.

[0020]

According to the first aspect of the semiconductor memory device of the present invention, the precharge control circuit and the equalize control circuit cause the precharge circuit and the equalize control circuit to detect the change in the address signal only when the address change is detected. Since the equalizing circuit is operated, precharging and equalization are not performed if the address does not change when the signal is read to the bit line pair.

According to the second aspect of the semiconductor memory device of the present invention, the precharge control circuit and the equalize control circuit operate the precharge circuit and the equalize circuit only when the address change detection circuit detects the address change. If the address does not change when the signal is read to the bit line pair, precharge and equalization are not performed, and the sense sensitivity changing means senses whether or not there is an address change when the signal is read to the bit line pair. Since sensitivity is changed and amplification is performed, it is possible to prevent unnecessarily high sensitivity.

According to the third aspect of the semiconductor memory device of the present invention, by switching and using two or more sense amplifiers having different sense sensitivities, it is possible to determine whether or not there is an address change at the time of reading a signal to a bit line pair. Correspondingly, since the sense sensitivity can be changed and amplified, it is possible to prevent an unnecessarily high sensitive sense.

According to the fourth aspect of the semiconductor memory device of the present invention, the sense amplifier for changing the sense sensitivity by increasing or decreasing the number of transistors relating to the sense sensitivity can be used to address the signal read to the bit line pair. Since the sense sensitivity can be changed and amplified depending on the presence or absence of a change, it is possible to prevent an unnecessarily high sensitive sense.

According to the fifth aspect of the semiconductor memory device of the present invention, the precharge control circuit operates the precharge circuit only when the address change detection circuit for detecting the change in the address signal detects the address change. If there is no address change when reading the signal to the bit line, precharge is not performed.

According to the sixth aspect of the semiconductor memory device of the present invention, the precharge circuit is operated by the precharge control circuit only when the address change detection circuit detects the address change. If there is no address change, precharge is not performed,
In addition, the sense sensitivity changing means amplifies the sense sensitivity by changing the sense sensitivity according to the presence or absence of an address change at the time of reading a signal to the bit line, so that it is possible to prevent the high-sensitivity sense more than necessary.

[0026]

1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, a precharge circuit 5 is connected to a memory cell array 4 composed of memory cells 41 by a bit line 42 via an equalize circuit 6. Here, the bit line 42 is formed by collecting a plurality of bit line pairs, each pair consisting of two bit lines.

To the memory cell array 4, the X decoder 2 is connected by the word line 21, and the Y selector 32 is connected by the Y selector control signal line 31 to the Y decoder 3.
Are connected by a bit line 42. X decoder 2
And the Y decoder 3 is connected to the address latch 1.

Sense sensitivity changing means 7 for changing the sense sensitivity and amplifying the signal of the bit line 42 is connected to the Y selector 32. In this embodiment, two sense amplifiers having different sense sensitivities, that is, a first sense amplifier 71 and a second sense amplifier 72 are provided, and the sensitivity is changed by switching to either one according to the situation. The control signal A from the sense amplifier control latch 73 and its inverted signal B are applied to the sense sensitivity changing means 7. A specific description of the sense sensitivity changing means 7 will be given later.

A precharge control circuit 51 is connected to the gate electrode of the precharge circuit 5, and an equalize control circuit 61 is connected to the gate electrode of the equalize circuit 6.

The X address coincidence signal 81 is applied from the address change detection circuit 8 to the precharge control circuit 51, the equalize control circuit 61 and the sense amplifier control latch 73.

As an input, the precharge control circuit 51
Further, clock signal φ1 is applied to equalize control circuit 61 and sense amplifier control latch 73, and clock signals φ1 and φ2 are applied to address detection circuit 8.
Further, the address change detection circuit 8 and the address latch 1
An address signal 11 is applied to the. As an output, the output signal 74 is output via the sense sensitivity changing means 7.

Next, the operation will be described with reference to FIGS. In this embodiment, non-overlapping two-phase clock signals φ1 and φ2 are used.
The memory has a storage capacity of 4K bits and a configuration of 1024 rows and 4 columns.

In FIG. 1, the address signal 11 is given from another block inside the chip or outside the chip at the timing of the clock signal φ2, and is input to the address latch 1 and the address change detection circuit 8. Address latch 1
After latching the address signal with the clock signal φ1,
The upper 10 bits (MSB side) are output to the X decoder 2 and the lower 2 bits (LSB side) are output to the Y decoder 3. The X decoder 2 decodes the upper 10 bits and outputs 1
One of the 024 word lines 21 is clocked by the clock signal φ.
1 is active only during a period of high potential (hereinafter, high potential is abbreviated as “H” and low potential is abbreviated as “L”). The Y decoder 3 decodes the lower 2 bits and activates one of the four Y selector control signal lines 31. Four memory cells 41 are connected to each word line 21. When the word line 21 becomes active, the access gates of the four memory cells connected to the word line become conductive, and the data held in the memory cell 41 becomes the bit line 42.
Are output to four pairs of bit lines. The bit line 42 is formed by the precharge transistor circuit 5 and the equalize transistor circuit 6 while the clock signal φ1 is “H”.
Precharging and equalization are performed, and the data of the memory cell 41 connected to the selected word line is output while the clock signal φ1 is "H". The Y selector 32 selects one of four bit line pairs of the bit line pair 42 according to the active Y selector control signal line 31. The output of the Y selector 32 is given to the sense sensitivity changing means 7, sensed by one of the sense amplifiers 71 and 72 having different sensitivities, and finally 1-bit data is output.

The address change detection circuit 8 includes an X decoder 2
The incoming address signal, that is, the address change of the upper 10 bits is detected. FIG. 2 shows a block diagram of the address change detection circuit 8. As shown in FIG. 2, the address change detection circuit 8 holds the data of one clock cycle before of the clock signals φ1 and φ2 by the latches 82 and 83, and compares the address one clock cycle before and the present address. This is performed by the device 84 while the clock signal φ2 is "H". At this time, if the addresses are the same, the X address coincidence signal 81 is activated.

The precharge control circuit 51 uses the clock signal φ1 when the X address match signal 81 is inactive.
Is sent to the precharge circuit 5 at the timing "H" to precharge the bit line 42.
When the X address coincidence signal 81 is active, the precharge signal is not given and the bit line 42 is not precharged.

Also for the equalize control circuit 61, when the X address coincidence signal 81 is inactive, the clock signal φ
When 1 is "H", an equalizing signal is sent to the equalizing circuit 6 to equalize the bit line 42. When active, no equalize signal is given and bit line 42
Is not equalized.

The sense amplifier 71 is a highly sensitive sense amplifier and is connected to the Y selector 32 to perform a sensing operation when the X address match signal 81 via the sense amplifier control latch 73 for the clock signal φ1 is inactive.
The sense amplifier 72 is a sense amplifier having low sensitivity, and is connected to the Y selector 32 to perform a sensing operation when the X address match signal 81 via the sense amplifier control latch 73 of the clock signal φ1 is active.

FIG. 3 shows an address map of the memory cell array 4 having 1024 rows and 4 columns according to this embodiment. As an example, a case of accessing in the order of addresses 4 (n-1), 4n + 1, 4n + 3 will be described with reference to the timing chart of FIG.

The address signal 11 changes at the timing when the clock signal φ2 is "H". The address is 4 (n-
When changing from 1) to 4n + 1 {period (from (1) to (2)}), the address entering the X decoder 2 changes from (n-1) to n. Therefore, the X address coincidence signal 81 becomes inactive (“L” in this case), the precharge signal and the equalize signal are output in synchronization with the clock signal φ1, and the bit line 42 is precharged and equalized {(3). Period}.

When the clock signal φ1 falls and precharge and equalization are completed {period (3) to (4)}, the word line 21 of the nth row becomes active ("H" in this example). The data of each memory cell 41 is output to each bit line 42. At this time, the Y selector 32 selects the first column. In the sense amplifier, since the X address coincidence signal 81 is inactive (“L” in this example), the highly sensitive sense amplifier 71 is selected, and the minute potential difference of the bit line 42 in the first column is sensed at high speed. To be done. The sense amplifier outputs 1-bit data of the address 4n + 1 during the period (4 ') shown in FIG.

When the address signal 11 changes from 4n + 1 to 4n + 3 at the timing of the clock signal φ2, the address entering the X decoder 2 does not change, so the X address match signal 81 becomes active (“H” in this example). . Since the access at this time accesses the word line 21 of the same row, the same data as the data read in the previous cycle is read to the four pairs of bit lines of the bit line 42. Therefore, it is not necessary to precharge and equalize, and when the X address coincidence signal 81 is active, the precharge signal and the equalize signal are not given, and the bit line 42 is not precharged or equalized {period (5)}. .

In the word line 21, the nth row becomes active at the timing of the clock signal φ1 as in the previous cycle {period (6)}. Since the bit line 42 has a potential difference .DELTA.V1 in the read of the previous cycle, the potential difference is further widened to .DELTA.V2 in the read of the current cycle.

The Y selector 32 is switched from the first column to the third column, but the sense amplifier does not need to have a high sensitivity because the potential of the bit line 42 has a large amplitude. Therefore, when the X address coincidence signal 81 is active, the low sensitivity sense amplifier 72 is selected. The data is output from the sense amplifier at the timing when the clock signal φ2 is “H” in the period (6 ′) shown in FIG.

In this case, the access time {(A2) period} is the access time when the X address coincidence signal 81 is inactive and a highly sensitive sense amplifier is used {(A
It becomes almost the same as the period of 1)}. Here, the access time is the time from when the clock signal φ2 rises until the output of the sense amplifier is determined.

Although the above description has been made only for reading data from the memory, the present invention can be applied to writing data as well, as will be described below.

FIG. 5 shows a circuit diagram when the write driver 9 is added. In FIG. 5, I from the Y selector 32
The write driver 9 is connected to the / O line 33. AND of clock signal φ2 and write enable signal 10
Write pulse signal 1 from the AND circuit connected to the circuit
1 and write data 91 are given to the write driver 9. Other configurations are similar to those of the first embodiment described with reference to FIG.

FIG. 6 shows a timing chart at the time of writing. In FIG. 6, the write enable signal 10 given at the timing of the clock signal φ1 is given to the AND circuit together with the clock signal φ2 to write pulse signal 1
1 is output. Here, the write enable signal 10 does not depend on the address coincidence signal and is a signal that is brought into the “H” state when writing is desired. When the write pulse signal 11 is “H”, the write driver 9 inputs the write data
When it is output to the O line 33 and the write pulse signal 11 is “L”, it is in a high impedance state.

At the time of writing, the write driver 9 swings the potential of the bit line 42 selected through the Y selector 32, and the data is written in the memory cell 41 selected in the active word line 21. At this time, regarding the bit line 42 not selected by the Y selector 32,
The data is read when the word line 21 becomes active. Conventionally, the same word line 21
When data is continuously written to the memory cells 41 connected to, the same data is read every time writing is performed, and precharge and equalization are performed each time. According to the present invention, when the memory cells 41 connected to the same word line 21 are continuously written, precharging or equalization can be prevented, and current consumption can be reduced.

Next, the sense sensitivity changing means 7 used in this embodiment will be described. In this embodiment, two sense amplifiers having different sense sensitivities, that is, the first sense amplifier 71
And the sensitivity was changed by switching and using the second sense amplifier 72 according to the situation.

FIG. 7 shows a circuit diagram of a first example of the sense sensitivity changing means 7 used in this embodiment. In FIG. 7, the first sense amplifier 71 and the second sense amplifier 72 are each configured by the same current mirror type circuit, and the I / O line pair 33 has an I
It is connected to the / O line and the bar I / O line. By changing the transistor sizes of the transistors forming the first sense amplifier 71 and the second sense amplifier 72, different sense sensitivities can be obtained for each sense amplifier, and the signals A and B from the sense amplifier control latch 73 can be obtained. Switch the sense amplifier to be used.

FIG. 8 shows a circuit diagram of a second example of the sense sensitivity changing means 7 used in this embodiment. In FIG. 8, the first sense amplifier 71 has the same configuration as the first example, the second sense amplifier 72 is simply an inverter, and switching of the sense amplifier to be used according to the signals A and B from the sense amplifier control latch 73. I do. The operation is performed by the first sense amplifier 71 when the potential difference between the bit line pair 42 is small, and the second sense amplifier when the potential difference between the bit line pair 42 is large and can be sufficiently used as an output signal without amplification.
The sense amplifier 72 is used. Since the sense amplifier 72 is an inverter, the bar I / O line is connected to the input of the inverter. FIG. 9 shows a circuit diagram of a third example of the sense sensitivity changing means 7 used in this embodiment. In FIG. 9, two sense amplifiers are connected in series. The preceding stage sense amplifier is a cross-couple type sense amplifier for performing pre-sense, and after the pre-sense is performed by the amplifier, the amplification factor is improved by further passing through the succeeding stage sense amplifier. The current-mirror type sense amplifier described in the first example is used as the sense amplifier in the subsequent stage. The operation switches the sense amplifier to be used by the signals A and B from the sense amplifier control latch 73. When the potential difference of the bit line 42 is small, the cross-couple type sense amplifier of the previous stage and the sense amplifier of the subsequent stage are operated for sensing, and when the potential difference of the bit line 42 is large, the cross-couple type sense amplifier of the previous stage is Senses only with the sense amplifier in the latter stage without operating.

That is, the case where the preceding cross-couple type sense amplifier and the succeeding stage sense amplifier are connected can be restated as the first sense amplifier 71, and the case where only the succeeding stage sense amplifier is formed can be restated as the second sense amplifier 72.

Although the sense sensitivity changing means 7 is composed of two sense amplifiers in the embodiment described above, the number of sense sensitivities may be increased by further increasing the sense amplifiers.

The embodiments described above can be modified as follows. That is, in the first embodiment, the sense sensitivity changing means 7 is composed of two sense amplifiers having different sense sensitivities, and the sense sensitivity is changed by switching the sense amplifiers depending on the situation. Instead of switching the amplifier, only the sense sensitivity may be directly changed.

FIG. 10 shows a circuit diagram of a semiconductor memory device to which this modification is applied. In FIG. 10, the control signal from the sense amplifier control latch 73 provided to the sense sensitivity changing means 7A is only the control signal B. Other configurations are similar to those of the first embodiment described with reference to FIG.

FIG. 11 shows a circuit diagram of the sense sensitivity changing means 7A. In FIG. 11, N-channel transistors N1 and N2 are arranged in series with each of P-channel transistors P1 and P2 that are arranged to face each other and form a current mirror, and the source electrodes of the N-channel transistors N1 and N2 are common. It is connected to ground potential. N-channel transistors N3 and N4 connected in series between the drain electrode and the source electrode of the N-channel transistor N1
And N-channel transistors N5 and N6 connected in series are connected between the drain electrode and the source electrode of the N-channel transistor N2. The I / O line and the bar I / O line pair of the I / O line pair 33 are connected to the gate electrodes of the N-channel transistors N1, N2 and N3, N5, respectively, and the control signal B is supplied to the N-channel transistor N4.
And the gate electrode of N6, and the output signal 74 is output from the drain electrode of the P-channel transistor P2.

The operation will be described. When the control signal B becomes "H", the N-channel transistors N4 and N6 operate to operate the N-channel transistors N1 and N2, and the number of transistors to which the I / O line pair 33 is input increases to sense. The sensitivity is improved. When the control signal B is "L", the number of transistors does not change, so the sense sensitivity remains unchanged.

Although the precharge circuit 5, the equalizing circuit and the sense sensitivity changing means 7 are controlled by the X address coincidence signal 81 in the above-described embodiments and modified examples, the current can be obtained only by controlling the precharge circuit 5 and the equalizing circuit. The consumption can be reduced. Further, since most of the current consumption is precharged, the effect of reducing the current consumption is great even if only the control of the precharge circuit 5 is performed.

Further, although the semiconductor memory device for transferring data by the bit line pair is shown in the above-described embodiments and modifications, the present invention is also applied to the semiconductor memory device for transferring data by one bit line. Applicable. In that case, since the equalizing circuit is not necessary, the control by the X address coincidence signal 81 is performed on the precharge circuit 5 and the sense sensitivity changing means 7. In particular, since the current consumption due to the precharge is large, the effect of reducing the current consumption is large only by controlling the precharge circuit 5.

[0060]

According to the semiconductor memory device of the first aspect, the precharge circuit and the equalize circuit are operated only when the address is changed when the signal is read to the bit line pair. Therefore, the address is not changed. In this case, precharging and equalization are not performed, and current consumption associated with precharging and equalization is reduced.

According to the semiconductor memory device of the second aspect,
The precharge circuit and the equalize circuit are operated only when the address is changed when the signal is read to the bit line pair. Therefore, when the address is not changed, the precharge and the equalize are not performed, and the current accompanying the precharge and the equalize is not performed. Since the consumption is reduced and the sense sensitivity is changed and amplified in accordance with the presence / absence of an address change at the time of reading the signal to the bit line pair, it is possible to suppress the current consumption due to the unnecessarily high sensitivity sense.

According to the semiconductor memory device of the third aspect,
By switching and using two or more sense amplifiers with different sense sensitivities, it is possible to change and amplify the sense sensitivities depending on the presence / absence of an address change when reading a signal to a bit line pair. It is possible to suppress the current consumption due to the high-sensitivity sensing.

According to the semiconductor memory device of the fourth aspect,
By the sense amplifier that changes the sense sensitivity by increasing or decreasing the number of transistors related to the sense sensitivity, the sense sensitivity can be changed and amplified according to the presence or absence of an address change at the time of reading a signal to the bit line pair. Therefore, it is possible to suppress current consumption due to unnecessarily high-sensitivity sensing.

According to the semiconductor memory device of the fifth aspect,
Since the precharge circuit and the equalize circuit are operated only when the address changes when the signal is read to the bit line, the precharge is not performed when the address does not change, and the current consumption accompanying the precharge is reduced. .

According to the semiconductor memory device of the sixth aspect,
Since the precharge circuit is operated only when the address changes when the signal is read to the bit line, the precharge is not performed when the address does not change, and the current consumption accompanying the precharge is reduced, and the bit Since the sense sensitivity is changed and amplified in accordance with the presence or absence of an address change when the signal is read out to the line, it is possible to suppress the current consumption due to the unnecessarily high sensitivity sense.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit configuration diagram of an address change detection circuit of a semiconductor memory device according to the present invention.

FIG. 3 is a diagram showing an address map of a memory cell of a semiconductor memory device according to the present invention.

FIG. 4 is a timing chart showing the operation of the semiconductor memory device according to the present invention.

FIG. 5 is a circuit diagram in which a write function is added to one embodiment of a semiconductor memory device according to the present invention.

FIG. 6 is a timing chart showing a write operation of the semiconductor memory device according to the present invention.

FIG. 7 is a circuit diagram showing a first example of the sense sensitivity changing means of the semiconductor memory device according to the present invention.

FIG. 8 is a circuit diagram showing a second example of the sense sensitivity changing means of the semiconductor memory device according to the present invention.

FIG. 9 is a circuit diagram showing a third example of the sense sensitivity changing means of the semiconductor memory device according to the present invention.

FIG. 10 is a circuit diagram showing a modified example of the embodiment of the semiconductor memory device according to the present invention.

FIG. 11 is a circuit diagram showing a sense sensitivity changing means of a modified example of the embodiment of the semiconductor memory device according to the present invention.

FIG. 12 is a circuit diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

 7, 7A Sense sensitivity changing means 8 Address change detection circuit 51 Precharge control circuit 61 Equalize control circuit 71 First sense amplifier 72 Second sense amplifier 73 Sense amplifier control latch 81 X address coincidence signal 82, 83 Latch 84 Comparator φ1, φ2 clock signal A, B sense amplifier control signal P1, P2 P channel transistor N1 to N6 N channel transistor

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 21, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

[0020]

According to the first aspect of the semiconductor memory device of the present invention, only when the address change detection circuit detects the address change of the address change detecting circuit for detecting the change of the address signal for selecting the word line .
Since the precharge circuit and the equalize circuit are operated by the precharge control circuit and the equalize control circuit, the precharge and the equalize are not performed when the address does not change when the signal is read to the bit line pair.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

According to the fifth aspect of the semiconductor memory device of the present invention, the precharge control circuit causes the precharge circuit only when the address change detection circuit detects the change in the address signal for selecting the word line. Is operated, the precharge is not performed when the address does not change when the signal is read to the bit line.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

In FIG. 1, the address signal 11 is given from another block inside the chip or outside the chip at the timing of the clock signal φ2, and is input to the address latch 1 and the address change detection circuit 8. Address latch 1
After latching the address signal with the clock signal φ1,
The upper 10 bits (MSB side) are output to the X decoder 2 and the lower 2 bits (LSB side) are output to the Y decoder 3. The X decoder 2 decodes the upper 10 bits and outputs 1
One of the 024 word lines 21 is clocked by the clock signal φ.
1 is active only during a period of low potential (high potential is abbreviated as “H” and low potential is abbreviated as “L” hereinafter). The Y decoder 3 decodes the lower 2 bits and activates one of the four Y selector control signal lines 31. Four memory cells 41 are connected to each word line 21. When the word line 21 becomes active, the access gates of the four memory cells connected to the word line become conductive, and the data held in the memory cell 41 becomes the bit line 42.
Are output to four pairs of bit lines. The bit line 42 is formed by the precharge transistor circuit 5 and the equalize transistor circuit 6 while the clock signal φ1 is “H”.
Precharging and equalization are performed, and the data of the memory cell 41 connected to the selected word line is output while the clock signal φ1 is "H". The Y selector 32 selects one of four bit line pairs of the bit line pair 42 according to the active Y selector control signal line 31. The output of the Y selector 32 is given to the sense sensitivity changing means 7, sensed by one of the sense amplifiers 71 and 72 having different sensitivities, and finally 1-bit data is output.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0060

[Correction method] Change

[Correction content]

[0060]

According to the semiconductor memory device of the first aspect , when the signal is read to the bit line pair , the word line is connected to the bit line.
The precharge circuit and the equalize circuit are operated only when there is a change in the address to be selected. Therefore, when the address does not change, the precharge and the equalize are not performed, and the current consumption accompanying the precharge and the equalize is reduced. .

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0061

[Correction method] Change

[Correction content]

According to the semiconductor memory device of the second aspect,
Selects a word line when reading signals to a bit line pair
Since the precharge circuit and the equalize circuit are operated only when the address to be changed is changed , the precharge and the equalize are not performed when the address is not changed, and the current consumption due to the precharge and the equalize is reduced. Since the sense sensitivity is changed and amplified in accordance with the presence / absence of an address change at the time of reading a signal to the bit line pair, it is possible to suppress the current consumption due to the higher sensitivity sense than necessary.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0064

[Correction method] Change

[Correction content]

According to the semiconductor memory device of the fifth aspect,
Select the word line when reading the signal to the bit line
The precharge circuit and the equalize circuit are operated only when there is a change in the address. Therefore, when the address does not change, the precharge is not performed, and the current consumption accompanying the precharge is reduced.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0065

[Correction method] Change

[Correction content]

According to the semiconductor memory device of the sixth aspect,
Select the word line when reading the signal to the bit line
The precharge circuit operates only when there is a change in the address, so precharge is not performed when there is no change in the address, the current consumption associated with the precharge is reduced, and the signal is read to the bit line. Since the sense sensitivity is changed and amplified depending on the presence or absence of an address change at that time, it is possible to suppress the current consumption due to the unnecessary high sensitivity sense.

Claims (6)

[Claims] 1. A first decoder for selecting a word line according to an address signal, a second decoder for selecting a bit line pair according to the address signal, a precharge circuit for precharging the bit line pair, and the bit. In a semiconductor memory device including an equalize circuit for equalizing line pairs, an address change detection circuit that detects a change in an address signal decoded by the first decoder, and the precharge when the address change detection circuit detects an address change. A semiconductor memory device including a precharge control circuit and an equalize control circuit for operating the circuit and the equalize circuit. 2. A first decoder for selecting a word line according to an address signal, a second decoder for selecting a bit line pair according to the address signal, a precharge circuit for precharging the bit line pair, and the bit. In a semiconductor memory device including an equalize circuit for equalizing line pairs, an address change detection circuit that detects a change in an address signal decoded by the first decoder, and the precharge when the address change detection circuit detects an address change. A precharge control circuit and an equalize control circuit for operating the circuit and the equalize circuit, and a sense sensitivity for interlocking with the operations of the precharge control circuit and the equalize control circuit and amplifying the signal of the bit line pair by changing the sense sensitivity. A semiconductor memory device including a changing unit. 3. The semiconductor memory device according to claim 2, wherein the sense sensitivity changing means includes two or more sense amplifiers having different sense sensitivities. 4. The semiconductor memory device according to claim 2, wherein the sense sensitivity changing unit includes a sense amplifier that changes the sense sensitivity by increasing or decreasing the number of transistors related to the sense sensitivity. 5. A semiconductor memory device comprising: a first decoder for selecting a word line according to an address signal; a second decoder for selecting a bit line according to the address signal; and a precharge circuit for precharging the bit line. In an address change detection circuit that detects a change in the address signal decoded by the first decoder, and a precharge control circuit that operates the precharge circuit and the address change detection circuit detects the address change. Semiconductor memory device. 6. A semiconductor memory device comprising: a first decoder for selecting a word line according to an address signal; a second decoder for selecting a bit line according to the address signal; and a precharge circuit for precharging the bit line. An address change detection circuit that detects a change in an address signal decoded by the first decoder, a precharge control circuit that operates the precharge circuit when an address change is detected by the address change detection circuit, and the precharge A semiconductor memory device comprising: sense sensitivity changing means for changing the sense sensitivity and amplifying the signal of the bit line in conjunction with the operation of the control circuit.