JPS61144795A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent entrance of capacity coupling noise from a Y address signal line in sensing period and make a sense amplifier highly sensitive by driving a decoder circuit after rising of an activating signal of the sense amplifier. CONSTITUTION:In the sense amplifier 10 of a D-MOSRAM, an RAS' signal becomes from H to L, and an X address buffer 1 is activated, and each signal having Y address time series and sense time series is generated by trigger of rising of an X address signal 2, and one signal is given to a delay circuit 5. An output of an AND gate 5b becomes from L to H when the condition that makes the delay circuit 5 and its output PHI1 from L to H and the condition that makes a CAS' signal from H to L and the condition that makes a slow sense signal PHIS1 of output of a sense amplifier driving circuit 7 from L to H are satisfied. A Y address buffer 4 is activated making the output a trigger.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device (hereinafter referred to as semiconductor memory 5) such as a dynamic MO8/RAM, which is composed of a transistor and a capacitor whose operation timings are adjusted. .

[Conventional technology]

Since the semiconductor memory of the present invention is most often applied to an N-channel dynamic MO8-RAMK, only one conventional example will be explained below.

FIG. 4 is a circuit diagram around a sense amplifier in a conventional dynamic MO8-RAMK consisting of one transistor and one capacity. In the figure, 1 is the X address buffer,
RA S (Row Addre+ss 5trobe
3 is an X decoder which is activated when the ) signal goes from 1H'' to @L'' and generates
Word line (not shown) by address signal 2
c4 has the role of selecting Y address buffer, 5
is a delay circuit, 5a is an AND gate, and CA S (Co
lumn Add, ress 5trobe) is @H″
to 1L", and the output φ of the delay circuit 5 triggered by the X address signal 21C changes from "L" to H".
When both conditions are satisfied, the logical circuit AND
Ge) 5m output φ2. becomes “Pi force) 1H”, and this output φ! 1 is activated after triggering and generates a Y address signal. 6 is a delay circuit triggered by the X address signal 2, which generates an output φ island. T is a sense amplifier drive circuit that is triggered by this output φ, and c8, which generates a slow sense signal φ, and a fast sense signal φ, has a gate that outputs the slow sense signal φ.
sl K connected, drain is sense 7 pump source line φ
, I/C is connected, and the source is connected to the ground (OV) K. 9 is a MOS transistor whose gate is connected to the first sense signal φ, and whose drain is connected to the sense 7 source line φ, and whose source is connected to the ground (OV)K. is a MOS) transistor connected to ground, where MO
S) The channel width of transistor 9 is the same as that of MOS transistor 8.
It is several ten times larger than the channel width of . 1G is a memory cell (not shown) k stored 10" or '
This is a sense amplifier for detecting binary information of 1).t2, and 1) and 12 are bit lines, and the information stored in the memory cells is first transmitted to these bit lines 1).t2.

Thereafter, the signal is transmitted to the sense amplifier IOK via bits 4!1) and 12. 13 and 14 are Y decoders provided near the sense amplifier l0VC;
3 and 14 function as one Y decoder. 1
5 a + 15 b r 15 c is a Y address signal line inputted to the left Y decoder 13 &, and is laid out orthogonally to the bit line 1). Similarly,
16a, 16b, and 16c are Y address signal lines input to the Y decoder 14 on the right side, and cY address signal lines 15a to 15 that are wired orthogonally to the bit line 12.
5e and 16a to 16e are transmission lines for the Y address signal, which is the output of the Y7 address buffer 4;
7 dongsbanghua 4 and Y decoder 13.14~MO8)
The transistors 2G and 21 form a decoder circuit.

17 is the I10 line, 1st is the I10 line, and Y decoder 1
3. When output 19 of 14 is at "H" level (when selected by Y decoder), bit line 1) is connected to I10 line 17 through MOS transistors 2G and 21, and bit line 12 is connected to I10 line 18. - 10,000, when the output of Y decoder 13゜14 is 19 pieces L level (when Y decoder is not selected) K is MOS) Since transistors 20 and 21 are off, bits Itj1) and l10IW1)
It is not electrically connected to the bit line 12 and the "7 stone line 1".
8 is also not electrically connected.

FIG. 5 is a time chart for explaining the operation of the circuit diagram in FIG. 4.

Dynamic M consisting of conventional l transistor and l capacitor
The circuitry surrounding the sensor amplifier 10 of the O8-RAM is configured as described above, and at time t in FIG.

When the RAS signal changes from @H'' to l L, II, this is used as a trigger to activate the X address signal 1 and generate the X address signal 2.
Two independent time series (Y
Each signal is generated having an address time series and a sense time series. One of them is the one that passes through the delay circuit 5,
The address signal 2 is taken over by the bird, and the output φ1 of the delay circuit 5 changes from "L" to @H"K at χ time t+. It is busy until time t2, and since the CAS signal has already changed from IHII to LIIVC, the output of the AND gate 5a φ2. is time t, K”L”
It rises to “H” from

Continuing the process, at time t, using the output φ2° of the KAND gate 5a as a trigger, the Y address buffer 4 is activated and a Y address signal is generated. The above sequence from time t to t is herein referred to as the Y address time sequence.

The other time series passes through the delay circuit 6, and is triggered by the X address signal 2 and the time Ill K delay circuit 6
The output φ becomes "H" from the chip L'. At this time, the word line rises, and a potential difference is generated between the bit line 1) and the bit line 120 depending on the information content of the X memory cell. In Figure 5,
This shows a case where the information of the memory cell connected to the bit line 1) is 0'', and a larger voltage drop occurs than in the case of the bit line 12.

However, the potential difference between this hint line 1) and bit l1j12 is only a few hundred mV at time Sl. At time s, the slow sense signal φ changes from 1L" to 1H", MOS) transistor 8 is turned on. Then, the potential of the sense amplifier source line i starts to drop gradually, and the sense amplifier 10 starts operating. Along with this, the slight potential difference that was occurring between the bit line 1) and the bit line 12 at time s, IfC begins to be amplified. Next busy time, time 1) 3VC worker, first sense signal φB goes from "L" to "H" and turns on MOS) transistor 9. Then, since the channel width of the MOS transistor 9 is large, the sense amplifier source line φ begins to drop rapidly and the sense amplifier 10 is strongly activated. Accordingly, bit 1i1). The potential difference between 12 and 12 is further expanded, and finally, at time a4 VC, bit! 1) 1 becomes OvK. On the other hand, the bit line 12 maintains the 1H" level although there is some voltage drop. The series of periods from time 8I to time 3 triggered by the X address signal 2 is called a sense period. The period from time S to s4 is called the amplification period.Here, the sequence from time S to 84 will be referred to as the sense time sequence.

Generally, the sense amplifier 10 provides high sensitivity.

In order to detect the potential difference appearing between the bit edges 1) and 1), it is important to balance the bit Iw1) and the bit line 12 as much as possible. That is, it is essential to consider making the stray capacitance CIL of the bit line 1) and the stray capacitance C□ of the bit line 12 as equal as possible. Sara K, 59th busy time 8, to 8. In the time period up to.

Since the potential difference between bit l1lj1) and bin) #J12 is very small, it is susceptible to noise mixed in pin) #jl 1, 12 VC (and it is necessary to reduce noise mixed in IK during this time.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory as described above, the following problems occur because the busy coupling capacitance C1 exists between the bit lines 1) and 12 between the Y address signal lines 15&~15e and 16a~16c. arise. In other words, the Y7 address signal remains 1L" or changes from 1L" to "H"K.
Either stand up, so Y7 dress scar line 15
The amount of capacitively coupled noise mixed into the Y address signal lines 16a to 16c is different from the amount of capacitively coupled noise mixed into the Y address signal lines 16a to 16c. As mentioned in the explanation of the operation of conventional semiconductor memory, the Y7 address time series and the sense time series proceed independently, so for example, the 5K as shown in FIG.
The rising point of the Y7 address signal, time t, may overlap during the sense period s@""s@, which is most susceptible to noise.

Therefore, the sense period a, - which is most susceptible to noise
s, K because an imbalance in the amount of capacitive coupling noise occurs due to the coupling capacitance CIK.

There is a problem in that the sensitivity of the sense amplifier 10 may be lowered, and furthermore, the sense amplifier 1o may malfunction.

This invention was made in order to solve this problem, and is designed to prevent capacitive coupling noise from the Y address signal line from entering during the sense period, which is most susceptible to the influence of noise. The aim is to obtain a semiconductor memory that performs the following steps.

[Means for solving problems]

The semiconductor memory according to the present invention is provided with a logic circuit that generates a trigger for driving a decoder circuit after the rise time of a signal that activates a Y address pulse has elapsed, and this logic circuit is connected to a slow sense signal φ, an If first sense signal. Driven by signal φ,8, Y is driven by the output of this logic circuit.
This activates the address buffer.

[Effect]

In this invention, only the sense amplifier is activated during the sense period when it is most susceptible to noise.

After the sensing period has elapsed, the rising point of the KY address signal is set to activate the Y decoder.

〔Example〕

FIG. 1 shows a dynamic MO8-RA consisting of one transistor and one capacitor of a semiconductor memory showing an embodiment of the present invention.
This is a circuit diagram around the sense amplifier in MK, and the symbols 1-
5.6~14.15a~150°16a~16c,
17 to 21 are exactly the same as the conventional device shown in FIG. Conditions for becoming @L" from
``When the conditions K are satisfied together, A which is a logic circuit
KG-sic is assembled so that the output φ2b of ND game) 5b changes from "L" to "H". Then, using the output φxb of the AND gate 5b of this logic circuit as a trigger, the Y7 dress buffer 4 is activated.

FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG.

In the circuit around the sense amplifier 100 in the semiconductor memory configured as described above, the time 1. in FIG. From 1. Operation of Y address time series up to and time 3
The operation of the sense time series from ゜ to 84 is based on the fourth
The operation is the same as that of the conventional example shown in the figure. Even if the output φ1 of the delay circuit 5 becomes "1H"K at time t+I't, A
Since the slow sense signal φ, which is one of the three inputs of the ND gate 5b, remains "", the AND gate 5b
The output of φ,.

remains at "L". Next, at time s2 VC of the sense time series, the slow sense signal φ, I rises from "L" to "H" K, and therefore, at time 12, the output φ2b of the AND gate 5b rises from L" to 1H".

Subsequently, at 1 time t, the output φ2b of AND game) 5b
is triggered, the Y address buffer 74 is activated,
A Y address signal is generated. As is clear from the above explanation of the operation, the Y address time series and the sense time series do not proceed independently in this embodiment, and the slow sense signal φ
, , so that sz<us
It becomes possible to satisfy the condition , and set the time t, which is the rising point of the Y7 address signal, after the sense time Ill to 33, when the sense amplifier 10 is most susceptible to the influence of noise. Therefore, the sense period 81-8. During this period, capacitive coupling noise due to the coupling capacitance tc+ is not generated, and the sensitivity of the sense amplifier 10 is not reduced.

In the above embodiment, the conditions for the delay circuit 50 output φ to change from "L" to "L" and for the CAS signal to change from "L" to "L'"
When the condition that the slow sense signal φ, 1, which is the output of the sense amplifier drive circuit 7, changes from L' to “H” and K is satisfied, the output of the AND gate 5b φ
The logic was set up so that i went from "L" to "H", but instead of the slow sense signal φ,1 which is the output of the sense amplifier drive circuit 7, the fast sense signal φ,2 was used.
It is also possible to configure the output of the AND game (AND game) 5b, which is a logic circuit, to change from "L" to "H"&'C when the condition changes from @L" to "H" ()e Figure 3 is 1 transistor showing another embodiment of this invention.
FIG. 2 is a circuit diagram around a sense amplifier in a dynamic MO8-RAMK having a capacity of 1.

In Figure 3, symbols 1 to 1, 6 to 14, 15a to 15
c, 16 a to 16 c, 17 to 21 are the fourth
This is the same as the conventional one shown in the figure. 5C is AN
The delay circuit 5 and its output φ1 change from “L” to “L” at the D gate.
'', the condition that the CAS signal changes from H'' to 1L'', and the condition that the first sense signal φ,2, which is the output of the sense amplifier drive circuit 7, changes from 1L'' to -H' are all satisfied. When this happens, the output φ of the AND gate 5c.

Since the logic is built and designed so that the signal becomes "L" from the input voltage, the condition of s2<ts is always applied to this embodiment. Therefore, the circuit of this embodiment is also similar to that shown in Fig. 1. You can expect the same effect.

In each of the above embodiments, the case of a dynamic MO8-RAM consisting of one transistor and one capacitor of N channel is shown, but the case of P channel is described.

It goes without saying that the present invention can be applied to the case of CMO8 and also to the case of RAM having other configurations.

〔Effect of the invention〕

As explained above, this invention is provided with a logic circuit that generates a trigger to drive the decoder circuit after the rise of the signal that activates the sense amplifier, so there is a sense period during which the sense amplifier is easily affected by noise. After this, the Y7 address signal is activated, which has the effect of preventing the influence of capacitive coupling noise.

[Brief explanation of drawings]

FIG. 1 shows a dynamic MO8-RA consisting of 1 transistor and 1'll amount in an ICVC according to an embodiment of the present invention.
A circuit diagram around a sense amplifier in MVC. FIG. 2 is a time chart for explaining the operation of the sense amplifier in the ICVC of the present invention shown in FIG. 1, FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a conventional ICVC.
Circuit diagram around sense amplifier in dynamic MO8-RAMVC consisting of 1 transistor and 1 capacitor in K,
FIG. 5 is a time chart for explaining the operation of the conventional device shown in FIG. In the diagram, 1 is the X address buffer, 2 is the X address signal, 3 is the X decoder, 4 is the Y address buffer, 5 is the delay circuit, 5m + 5b + 5c is the AND gate,
6 is a delay circuit, 7 is a sense amplifier drive circuit, 8.9 is M
OS transistor, 10 is a sense amplifier, 1). 12 is the bit line, 13.14 is the Y decoder + 15m+
15b* 15c, 16m+16b, 16c is Y address signal line, 17 is I10 shield, 1B is I10 Iwao, 19
is the output of the Y decoder, and 20.21 is a MOS transistor. In addition, the same symbols in each figure are the same -1! The corresponding portion is shown. Agent Masuo Oiwa (2 others) Figure 2 Figure 5 to s+ 525354 Procedural amendment (spontaneous) 1. Indication of case Patent application No. 267951 1982 2.
Title of the invention Semiconductor storage device 3, relationship to the amended case Patent applicant address 2-3 Marunouchi Sara-chome, Chiyoda-ku, Tokyo Name (601) Representative of Mitsubishi Electric Corporation
゛ μ 4, person Moriya Shiki Address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, the Detailed Description of the Invention column of the specification to be amended, Drawing 6, and Contents of the Amendment (1) ``Sense Amplifier'' in line 2 of page 1 of the specification is amended to ``Sense Amplifier 10''. (2) Correct each of Figures 1, 3, 4, and 5 as shown in the attached sheet. that's all

Claims (2)

[Claims] (1) In a semiconductor memory device having a sense amplifier, a bit line connected to the sense amplifier, and a decoder circuit arranged close to the bit line, after the rise of a signal that activates the sense amplifier, A semiconductor memory device comprising a logic circuit that generates a trigger for driving the decoder circuit. (2) The semiconductor memory device according to claim (1), wherein the signal for activating the sense amplifier is derived from one of the trigger signals of a logic circuit that drives the decoder circuit.