JPH05181574A - External data input circuit - Google Patents

Abstract

PURPOSE:To secure the connection between an external data input circuit and an external device that immediately starts the output of data when a power supply is turned on and at the same time to correct the shift of a packet when the packet data of the optional length are continuously inputted. CONSTITUTION:When both input request and input data valid flags are set in the ON states, an input synchronization control circuit 5 outputs a start signal 20 to a FIFO control circuit 2 to make this circuit 20 start to input the data from an external device. If the data on the packet having a transfer error are shifted in a packet transfer mode, the circuit 5 recognizes the occurrence of a packet step-out and then clears a WC 3 and an RC 4 with the reset signals 23 and 22 respectively. Then the circuit 5 outputs again the signal 20 to the circuit 2 to restart the input of packet when an input synchronization flag 24 is inputted. Thus the shift of the packet is automatically corrected and the packet transfer synchronization is recovered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external data input circuit, and more particularly to a synchronous external data input circuit for inputting a large amount of data such as image data in a continuous packet.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional external data input circuit has a FIFO1 (first-in first-out section) that stores data input from an external device once, and sequentially outputs the data input first, and a reset function. A write counter (WC) 3 that holds a write address according to a WC count request signal, a read counter (RC) 4 that generates a read address according to an RC count signal, an input request, a read address, a write address, and Input valid data flag of
E) 15, read count request 16, write count request 18, read data valid flag 1 from FIFO 1
3 and a FIFO control circuit 2 for outputting 3.

When an input data valid flag 14 is input from an external device, the FIFO control circuit 2 outputs a write enable (WE) 15 and the input data is stored in the FIFO 1
Write to and count up WC3. In this way, the input data 10 is sequentially stored in the FIFO 1.

At this time, when the input request flag 12 is input to the FIFO control circuit 2, the WE 15 is turned off to put it in a read state, data is read from the FIFO 1 and RC4 is counted up. Further, the read data valid flag 13 is output in synchronization with the read data 11.

[0005]

By the way, in the conventional external data input circuit, the input request flag 12 is turned off.
If the input data valid flag 14 is ON at
Since the FIFO 1 overflows because the input data is not read out even though the input data is written to the FO 1, there is a restriction that the input request flag 12 must be turned on and then the input data valid flag 14 must be turned on.

Therefore, there is a problem that an external device that immediately starts outputting data when the power is turned on cannot be connected. Further, when packet data of arbitrary length is continuously input, if the data is missed in the middle, all the subsequent packets will be shifted, and synchronization cannot be restored.

The present invention has been made in view of the above problems, and enables connection to an external device that immediately starts outputting data when the power is turned on, and eliminates a data shift during packet transfer. The purpose of the present invention is to provide an external data input circuit.

[0008]

In order to achieve the above object, an external data input circuit of the present invention has a FIFO that stores data input from an external device once, and sequentially outputs the data from the first input, and a reset function. A write counter that generates a write address according to a write count request signal, and a read counter that has a reset function and generates a read address according to a read count request signal
A FIFO control circuit that outputs a FIFO write enable signal, a read count request signal, a write count request signal, and a read data valid flag from the FIFO based on the input of an input request flag, a start signal, a read address, and a write address, and an input. An input synchronization control circuit for outputting the start signal to the FIFO control circuit and the reset signal of the write counter and the read counter based on the input of the request flag, the input synchronization flag, and the input data valid flag from the outside is provided.

If necessary, the input synchronization control circuit sets both the input request flag and the input data valid flag to O.
When N, a start function that outputs a start signal to the FIFO control circuit and starts a data input operation from an external device,
A synchronization deviation recognition function for recognizing that a packet synchronization deviation has occurred if the input synchronization flag is not ON when the next data is input after the packet length data is input,
At this time, the start signal is turned off to stop writing to the FIFO, the write counter and the read counter are cleared by the reset signal, and when the input synchronization flag is input next, the start signal is output again to the FIFO control circuit to And a restart function for restarting the input of.

[0010]

According to the external data input circuit having the above structure, both the input request flag and the input data valid flag are O.
If N, the input synchronization control circuit can output a start signal to the FIFO control circuit to start the data input operation from the external device. In addition, when a transfer error occurs during packet transfer and the packet data is deviated, the input synchronization control circuit inputs the packet length data, and when the next data is input, the input synchronization flag is not ON. It can be recognized that the synchronization deviation has occurred. At this time, the start signal is turned off to stop writing to the FIFO1, the write counter and the read counter are cleared by the reset signal, and the FIFO control is performed again when the input synchronization flag is input. A start signal can be output to the circuit 2 to restart the packet input. As a result, the packet shift can be automatically corrected and the packet transfer synchronization can be restored.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an external data input circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a FIFO which stores data inputted from an external device once, and which sequentially outputs the data inputted first, 3 has a reset function, and a write address 17 according to a write (WC) count request signal 16. Is a read counter that has a reset function and that generates a read address 19 according to a read (RC) count request signal 18.

A FIFO control circuit 2 includes an input request flag 12, a start signal 20, a read address 19,
Based on the input of the write address 17, a write enable (WE) signal of the FIFO 1 and a read count request signal 1
8, write count request signal 16, FULL signal 21,
The read data valid flag 13 from the FIFO is output.

Reference numeral 5 denotes an input synchronization control circuit, which inputs an input request flag 12, an input synchronization flag 24, an input data valid flag 14 from the outside, and a FULL signal 21 of the FIFO 1 and inputs the start signal 2 to the FIFO control circuit 2.
0, reset signals 23 and 22 for write counter and read counter are output.

That is, the input synchronization control circuit 5 outputs the start signal 20 to the FIFO control circuit 2 to start the data input operation from the external device when both the input request flag 12 and the input data valid flag 14 are ON. A start function, a synchronization deviation recognition function for recognizing that a packet synchronization deviation has occurred when the input synchronization flag 24 is not ON when the next data is input after the packet length data is input, and the start signal 20 at this time. OFF and F
Stop writing to IFO1 and write counter 3
The read counter 4 is cleared by the reset signals 23 and 22, and the start signal 20 is sent to the FIFO control circuit 2 again when the input synchronization flag 24 is input next.
And a restart function for restarting packet input.

Next, the operation of the external data input circuit according to the embodiment will be described. FIFO1, FIFO control circuit 2, W
The functions and operations of C3 and RC4 are the same as those of the conventional circuit. Since the input synchronization control circuit 5 is a feature of this embodiment,
The operation of this will be described.

First, when both the input request flag and the input data valid flag are ON, the input synchronization control circuit 5 causes the FIF to operate.
A start signal is output to the O control circuit 2 to start the data input operation from the external device. As a result, the start of the input operation can be easily synchronized.

Further, the input synchronization flag has a function of restoring the synchronization of packet transfer by detecting the head data of the packet when a transfer error occurs during packet transfer and the packet data is deviated. In packet transfer, the external device turns on the input synchronization flag when the top data of the packet is input.

After the packet length data is input, the input synchronization control circuit 5 recognizes that the packet synchronization shift has occurred if the input synchronization flag 24 is not ON when the next data is input. At this time, the start signal 20 is turned off
Then, writing to the FIFO1 is stopped, and WC3 and RC4 are cleared by the reset signals 23 and 22.

Next, when the input synchronization flag 24 is input, the start signal 20 is output again to the FIFO control circuit 2 to restart the packet input. By the above method, the packet shift can be automatically corrected and the packet transfer synchronization can be restored.

[0021]

As described above, according to the external data input circuit of the present invention, not only the input synchronization control circuit can easily synchronize the start of the input operation, but also the data shift during the packet transfer. Even if the error occurs, there is an effect that the head of the packet data is automatically detected, the shift is eliminated, and the synchronization can be restored.

[Brief description of drawings]

FIG. 1 is a block diagram showing a synchronous external data input circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional external data input circuit.

[Explanation of symbols]

 1 FIFO 2 FIFO Control Circuit 3 Write Counter (WC) 4 Read Counter (RC) 5 Input Synchronous Control Circuit 10 Input Data 11 Read Data 12 Input Request Flag 13 Read Data Request Flag 14 Input Data Valid Flag 15 Write Enable (WE) 16 WC count request signal 17 Write address 18 RC count request signal 19 Read address 20 Start 21 Input prohibition 22 RC reset signal 23 WC reset signal 24 Input synchronization flag

Claims (2)

[Claims] 1. A FIFO that stores data input from an external device once and sequentially outputs the data input first, a write counter that has a reset function and generates a write address according to a write count request signal, and a reset function. A read counter that generates a read address in accordance with a read count request signal, and a write enable signal, a read count request signal, a write count request signal, and a FIF of a FIFO based on the input of an input request flag, a start signal, a read address, and a write address.
FIFO that outputs read data valid flag from O
A control circuit and an input synchronization control circuit for outputting the start signal to the FIFO control circuit, and a reset signal for the write counter and the read counter based on the input of an input request flag, an input synchronization flag, and an input data valid flag from the outside. An external data input circuit characterized in that 2. The input synchronization control circuit, when both an input request flag and an input data valid flag are ON, a FIF
A start function that outputs a start signal to the O control circuit to start the data input operation from an external device, and the packet synchronization if the input synchronization flag is not ON when the next data is input after the packet length data is input. When there is a synchronization shift recognition function that recognizes that a shift has occurred, the start signal is turned off at this time to stop writing to the FIFO, and the write counter and read counter are cleared by a reset signal, and the next input synchronization flag is input. 2. The external data input circuit according to claim 1, further comprising a restart function for outputting a start signal to the FIFO control circuit again and restarting packet input.