JPH11146350A - Video audio decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the decoder by which data adopting the program stream PS method or the transport stream method are decoded with sufficient performance by replacing software. SOLUTION: System clock information of a coder is recovered by detecting a head of a packet on which video image and audio data are multiplexed, filtering only a valid packet required for decoding based on a header pattern of the head of the packet, detecting the packet including the system clock information of the coder and informing a CPU 18 of it when the system clock information is extracted. The CPU 18 attains decoding by software with sufficient performance by reading header information of the valid packet or all valid packets from an FIFO 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video / audio decoding device required for multimedia services such as CATV and satellite digital broadcasting.

[0002]

2. Description of the Related Art In ISO / IECJTC1 / SC29, a compression system and a multiplexing system for video and audio data related thereto are standardized. In particular, the multiplexing method includes a variable-length packet PS (Program Stream) method mainly specified for data of a storage system and a fixed-length packet TS (Transport Stream) method capable of coping with a certain transmission error. is there.

In the PS system, a plurality of programs (one pair of audio data and the like associated with video) are not multiplexed in one stream.
In the S system, a plurality of programs may be multiplexed. Therefore, in the TS system, it is necessary to filter and decode only packets of a specific program.

In the framing of a packet (from the beginning to the end), in the case of the PS system, a unique pattern is defined at the beginning, and can be detected by finding the pattern. However, in the case of the TS system, the head pattern is defined, but its value is not unique. Therefore, it can be recognized as the beginning of the frame only after repeatedly detecting the unique pattern. In the case of the TS system, since the packet is a fixed-length packet, even if an error occurs in the header pattern due to a transmission error or the like, the next packet reception can be expected.

In the decoding device, it is necessary to perform decoding in synchronization with the system clock used at the time of data compression in the encoding device. In both the PS system and the TS system, the system clock information is multiplexed into each packet. However, in the case of the TS, since a plurality of programs are multiplexed, it is necessary to perform filtering from among a plurality of pieces of system clock information.

[0006] In the program data to be decoded, video, audio, data information, and other table information are distinguished from each other by using the PE multiplexed in the PS packet in the case of the PS system.
It is identified by the StreamID of the S packet. The PS packet includes a video PES packet, an audio PES packet, a private PES packet for data transmission,
PSI information, which is table information, is multiplexed.
It can be identified by looking at the StreamID of the ES packet. In the case of the TS system, the identification is made by the PID included in the header of the TS packet. Unique P for each data such as video, audio, data information and table information
An ID is set, and only the set TS packet is filtered to identify the content.

When the PS system and the TS system are compared, there are differences as described above, and it is very difficult to realize all decoding functions satisfying both functions by hardware. Therefore, if the parts different from the common part of both types of processing are arranged and at least different parts are processed by software, it is possible to easily realize both types of decoding.

For example, when decoding by the PS method, one PS packet has a relatively large packet length (up to 6).
Video PES packets and audio PES packets having 4 Kbytes) are multiplexed, and PS packets of another program are not multiplexed. Therefore, the frequency at which the processor performs the system decoding process is low, and the load is not so large.

However, when decoding is performed by the TS method, T
The S-packet length is 188 octets, and it is necessary to read the header information at a high frequency and decode the system, which greatly increases the load on the processor. (For example, in the case of MPEG2, if the transmission rate of one program is 6 Mbps, 2
It is necessary to perform system decoding once every 50 μs. )
In addition, in the case of the TS system, there is a possibility that a packet of another program may be received, and the load is further increased. Also,
In decoding by software, data movement between memories occurs. Therefore, even if a high-performance processor is used, sufficient performance cannot be achieved unless the bus bottleneck of the processor can be solved.

[0010]

The problem to be solved by the present invention is that by replacing software, the PS
It is an object of the present invention to realize a decoding device that can achieve decoding of the TS method or the TS method with sufficient performance.

[0011]

As means for solving the above-mentioned problems, data of a fixed-length packet in which video and audio are multiplexed are received in synchronization with an externally provided clock, and the header pattern of the packet is changed. A means for detecting the head of the fixed-length packet by detecting the data a plurality of times in succession, and at least one
Means for detecting and receiving only valid packets having two header patterns, and detecting a packet including system clock information of the encoding device from the header pattern of the valid packet, extracting system clock information, and
Means for writing the valid packet only to the FIFO using an externally provided clock, means for reading from the FIFO using an internally generated clock, and writing the valid packet to the FIFO. Means for notifying the CPU, means for the CPU reading the valid packet from the FIFO, and reading of all or part of the valid packet from the FIFO in accordance with an instruction from the CPU, and transmitting the remaining information of the packet to the video decoding unit or the audio decoding unit. It has a means for outputting, and a means for reading out all or a part of valid packets from the FIFO and discarding them according to an instruction from the CPU.

Further, input means for receiving a packet in which video and audio are multiplexed and other data via a bus for compound communication, input means for receiving only the fixed length packet, and an instruction from the CPU. And means for selecting and receiving any of the above input means.

Means for setting a header pattern of the above-mentioned valid packet or a packet containing system clock information of the encoding device in accordance with an instruction from the CPU;
It has means for starting and stopping the comparison between the set header pattern and the received packet.

When a valid packet for which packet synchronization has been detected is received, valid packet information and packet header information indicating the beginning of the packet are written into the FIFO, and the CPU transmits the packet information and the packet header information from the FIFO. Has a means for reading out.

In response to an instruction from the CPU, the FIFO
Means for setting the data length of all or some of the buckets to be read from the output unit, and outputting the read data to the video decoding unit or the output to the audio decoding unit;
Means for selecting either PU reading or discarding; means for starting reading from the FIFO;
It has means for notifying the CPU after reading from the IFO is completed.

A means for detecting a packet containing system clock information of the encoding device from the header pattern of the valid packet, extracting the system clock information, and reproducing the system clock of the encoding device, Means for receiving the system clock of the encoding device;
It has means for selecting any of the above system clocks in response to an instruction from U.

In the case where system clock information is extracted from the valid packet and notified to the CPU, means for detecting only a transmission counter value of a finite word length received as the system clock information is provided based on its own receiving clock. Means for holding a reception counter value of a finite word length to be counted up, a transmission lower counter value represented by a prescribed number of lower bits of the transmission counter value, and a lower bit represented by a prescribed number of the reception counter value Means for taking a difference from the reception lower counter value represented by, and, when the system clock information is extracted, the reception clock based on the difference value between the transmission lower counter value and the reception lower counter value. It has means for changing the frequency and regenerating the system clock on the transmitting side.

The means for calculating a difference between the transmission lower-order counter value and the reception lower-order counter value may be configured so that the transmission lower-order counter value or the reception lower-order counter value indicates the transmission lower-order value when the system clock information was received immediately before. In the case of a counter value or a value after an overflow from the reception lower counter value, a means is provided for correcting the transmission lower counter value or the reception lower counter value and then calculating the difference.

The difference between the transmission lower counter value and the reception lower counter value is calculated by means for calculating the difference between the transmission lower counter value and the reception lower counter value. As a result, the difference value is greater than or equal to a specified value. In this case, there is a means for ignoring the difference value.

By using the present invention, the head of a packet can be detected from a packet in which video and audio are multiplexed, and only valid packets necessary for decoding can be filtered from the header pattern at the head of the packet. Detects packets containing clock information,
By notifying the CPU at the time of extracting the system clock information, the system clock information of the encoding device can be reproduced. The CPU reads the header information of the valid packet or all of the valid packet from the FIFO to execute the software. Can be achieved with sufficient performance.

When a packet in which video and audio are multiplexed is input from a dedicated parallel input port, the load on the general-purpose bus and the local bus is reduced, and the hardware of the input port connected to the general-purpose bus is also reduced. it can.

Further, according to an instruction from the CPU, a header pattern of the valid packet or a packet including system clock information of the encoding device can be set, and comparison of the set header pattern with a received packet is started and stopped. By having the means, it is possible to suppress the reception of invalid packets that occur in an abnormal state or the like when the input line is not stable.

Also, packet header information indicating the beginning of the packet is written into the FIFO along with the valid packet, and
Since the PU has a means for reading from the FIFO, the CP
U can easily confirm the position of the header.

In response to an instruction from the CPU, the FIFO
Means for setting the data length of all or a part of the packet read from the PDU, and outputting the read data to the video decoding unit or the output to the audio decoding unit;
Means for selecting either PU reading or discarding; means for starting reading from the FIFO;
By having a means for notifying the CPU after reading from the IFO, the CPU reads only the header information of the packet, and after determining whether the data is video data or audio data, all the packet information is read. There is no need to read, and the CPU load is greatly reduced.

The CPU has means for reproducing a system clock from the header of the valid packet and means for directly receiving the system clock of the encoding device from the outside.
Has means for selecting any one of the above system clocks in response to an instruction from, the synchronization of the system clock is realized even when the input packet does not include normal system clock information.

When extracting system clock information from the valid packet and notifying the CPU of the extracted information, means for detecting only a transmission counter value having a finite word length received as system clock information and based on its own receiving clock. Means for holding a reception counter value of a finite word length to be counted up, a transmission lower counter value represented by a prescribed number of lower bits of the transmission counter value, and a lower bit represented by a prescribed number of the reception counter value Means for calculating a difference between the reception lower counter value represented by a symbol and the reception clock based on a difference value between the transmission lower counter value and the reception lower counter value when the system clock information is extracted. By reducing the frequency of the clock and having a means to regenerate the system clock on the transmission side, the number of registers that latch the counter can be reduced, Fine comparison mitigation of software processing that is possible.

The transmission lower counter value or the reception lower counter value may be obtained by calculating a difference between the transmission lower counter value and the reception lower counter value. In the case of a counter value or a value after overflow from the reception lower counter value, the word length of the counter to be compared is limited by having a means for correcting the transmission lower counter value or the reception lower counter value and then taking a difference. However, an accurate counter value difference can be detected.

The difference between the transmission lower counter value and the reception lower counter value is calculated by means for calculating the difference between the transmission lower counter value and the reception lower counter value. As a result, the difference value is equal to or greater than a specified value. In this case, by providing means for ignoring the difference value, sudden difference value abnormality can be avoided.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

As shown in FIG. 1, a general-purpose bus interface 10 connects a general-purpose bus 0 to a local bus 1, and transmits video and audio information from a storage device or an input device (not shown) on the general-purpose bus. It has a function of inputting to the input stream control 12. Input stream control 12
Can input video and audio information from the dedicated parallel interface 11 and the local bus 1, and can select one of them by an instruction from the CPU 18. The input packet is subjected to packet synchronization detection and filtering processing, and is written to the FIFO 13.

The packet written in the FIFO 13 is
First, only the header information is read by the CPU 18,
It is determined whether the data is video data, audio data, or table information. The remaining information of the packet is sent to the video decoding circuit 14 for video information, and to the audio decoding circuit 16 for audio information.
The data is directly output from the FO by the DMA function, and is input to FIFOs 15 and 17 connected to the respective DMAs.

The video decoding circuit 14 is an STC which is incremented by the system clock reproduced by the decoding device.
It has a (System Time Clock) counter, and when it matches the display time information included in the video data, outputs a digital signal read from the FIFO 15 and decoded. Then, via the video / digital-analog conversion circuit 22, the analog interface circuit 2
4 is output.

The audio decoding circuit 16 has an STC (System Time Clock) in the video decoding circuit 14.
k) Referring to the counter, if it matches the display time information included in the audio data, a digital signal read from the FIFO 17 and decoded is output. Then, the signal is output to the analog interface circuit 24 via the audio / digital-analog conversion circuit 23.

The VCXO 26 for reproducing the system clock of the encoding device is controlled by the CPU 18 via the VCXO interface circuit 25. The CPU 18
A register existing in the CXO interface circuit 25 is set, and its value is digital-to-analog converted to VCXO2.
6 is output.

The system clock reproduced by the VCXO 26 and the system clock directly input from the outside are input to the clock control circuit 27, and the CPU
Select one of them.

The selected system clock is output to the video decoding circuit 14 and furthermore, the clock control circuit 27
And the phase is compared with the clock obtained by dividing the output of the audio VCXO 29. The output of the phase comparison circuit 28 is input to the audio VCXO 29, and synchronization between the system clock and the audio clock is realized. The clock obtained by dividing the audio clock is input to the audio decoding circuit 16 via the audio / digital-analog conversion circuit 23.

The local data bus 3 and the address bus 4 to which the CPU is connected include the data bus 1 connected to the general-purpose bus 0, the address bus 2 and the bidirectional buffer 10
The local buses 3 and 4 are not affected even when a packet is transferred from the general-purpose bus to the input stream control.

The CPU is connected to the local buses 4 and 3 via buffers 101 and 103, respectively. The buses include an SRAM 19 and a ROM 20, and a local bus control for generating an address decode signal and performing bus ready control for the CPU. Circuit 21 is connected.

FIG. 2 shows a detailed block diagram of the input stream control 11 in order to explain the features of the present invention in detail. I
The NBLK unit 201 is a dedicated parallel interface 1
1 and data from the local bus 1 and select FR
Output to C section 202. When the FRC unit 202 receives a packet, it performs packet synchronization detection, valid packet filtering, and system clock information extraction, and outputs only a valid packet to the FIFOBLK unit 203. FI
In the FOBLK unit 203, reading and writing of the FIFO 13,
Data is output from the PU in the specified direction. here,
Since writing and reading of the FIFO 13 can be performed asynchronously, a clock existing inside the decoding device can be used as a FIFO reading clock. Also, CPUB
The LK 204 provides a CPU interface.

To explain the details of the packet synchronization control,
FIG. 3 shows a state transition diagram of synchronization detection when a TS packet is input.

In the case of a TS packet input, a hunting state occurs after a reset, and byte
When "0x47" is detected, the state becomes the pre-synchronization state. In the pre-synchronization state, “0x” is set for each TS packet interval (188 bytes).
47 "is extracted continuously N-1 times, and then synchronized, the following 1
A portion between 88 bytes is determined as a TS packet. In addition, sync in the pre-synchronization state If no byte can be detected, the state returns to the hunting state. In a synchronized state, sync from a predetermined place at least n times continuously byte "0x47"
If is not detected, the operation returns to the hunting state. Here, the number of stages for establishing synchronization (N) and the number of stages for which synchronization is lost (n) are set by the CPU writing to a register for input stream control.

In order to filter a received packet, in the case of a TS packet, a PID is extracted from a predetermined field in a header of the received packet. Extracted PI
D is compared with a register value set in advance by the CPU, and if different, the corresponding TS packet is discarded. However,
A packet having a PID of 0x0000 is a specific packet, and is always discarded and input to the FIFO. When the filtered packet is written to the FIFO, C
An interrupt signal is issued to the PU, and the corresponding status flag of the internal register is turned on.

In the PID value for filtering the packet, only 0x0000 is enabled in the reset state, and the other packets can be received later by additionally setting a new effective PID value from the CPU. Further, there is a flag for validating / invalidating the set PID value, and this flag setting can be controlled by the CPU.

When a packet that has been filtered and passed is written to the FIFO, the head information of the packet is also written to the FIFO. For example, when writing a packet in 8-bit parallel, the data width of the FIFO must be 1 bit.
It may be increased to 9 bits. Thus, if the CPU can read the header information when reading data from the FIFO, it can be easily confirmed whether or not the header information is the head.

When the system clock information is included in the received packet after being filtered, the system clock information is extracted from the packet, latched in an internal register, and notified to the CPU by interruption.

The packet written in the FIFO is a CP
U, first, only the header information is read.
It is output directly from the FO by the DMA function. The DMA function is
The CPU starts by writing the transfer size and the transfer direction to the input stream control register and turning on a flag for activating the DMA function. After completion, the CPU is notified by an interrupt. Here, as the transfer direction, any one of the video decoding circuit 14, the audio decoding circuit 16, the CPU reading, and no output direction (discard) can be selected.

In the case of a PS packet input, the head of the packet is a 32-bit unique pattern (0x000001).
BA). Therefore, the header pattern need not be counted in the pre-synchronization state as shown in FIG.
In the filtering process, the stream included in the PES packet is used. There is a method using id, but PS
In the case of a packet, a plurality of pieces of program information are not multiplexed in principle, and even if the CPU reads the header information to make a determination, the load on the CPU is not so large.

When the input stream control 12 detects a packet including system clock information by packet filtering, it interrupts the CPU. CPU
Reads the system clock information stored in the register of the input stream control 12 and starts a PLL process for reproducing the system clock.

FIG. 4 is a functional block diagram of the PLL process for explaining the PLL process.

In the PLL process, the system clock information (time stamp value) extracted from the received packet by software is compared with its own counter value, the difference is obtained, and the result is processed by a digital filter 302 having LPF characteristics. . The output result of the filter is input to the digital-analog conversion circuit 303. Here, the counter 30
5 is counted up by the output frequency of the VCXO, and the phase comparison of the PLL is realized by comparing the counter value with the time stamp value of the received packet by the counter comparison 301. When a packet containing the time stamp value is first received, the received time stamp value
Is loaded into the counter 305 via.

The VCXO 304 outputs a free-running frequency when no signal is input, but when a signal is input to the digital-analog conversion circuit 303, a frequency corresponding to the value is output from the VCXO 304. The obtained frequency is a frequency at which the system clock of the encoding device is reproduced. This series of processing is fed back as a count-up cycle of the counter 305 to be subjected to phase comparison, and the free-running frequency of the VCXO 304 gradually increases with time. From the system clock frequency of the encoding device.

FIG. 5 shows the time stamp included in the packet as clock information and the field format of the counter of the decoding device.

When the decoding apparatus reproduces the system clock of the encoding apparatus, the time stamp value and the counter value as the phase information are represented by a long finite word length of the x-bit 401. However, all bits of these phase information
It is not necessary to compare the phases by looking at. Assuming that the transmission cycle of the timestamp value is a (sec) and the maximum jitter amount is b (sec), and the maximum number of missing packets is N, the word length (the number of bits) used in the filtering process is max (a × N × f _sys , b × N × f _sys ) <2 ^N−1 The minimum value of N (y-bit 402) is sufficient. That is, when the phase comparison value is obtained from the time stamp value and the counter value, filtering may be performed by looking only at the lower y-bit 402. (Fsys: system clock frequency) However, the time stamp value of a packet received via a network may fluctuate due to jitter. In that case, the timestamp value may be the value after overflowing and returning to the initial value, while the counter value may be the value before overflowing. Since large jitter has occurred, normal clock recovery cannot be realized. For this reason, the time stamp value and the counter value hold the values of one past sample at the time of the phase comparison trigger, and compare them with the past sample values before performing the phase comparison, and if the values can be recognized as the values after the overflow (for example, (When the value becomes smaller than the value of), the value is corrected by the amount of overflow, and the phase comparison is performed.

FIG. 6 shows a software processing flow that occurs when a time stamp is received among the software processing in the PLL processing.

Although not explicitly shown in this processing flow, first, in the initialization processing, a coefficient (timer for filtering) and a memory (filter delay unit) for storing past signals are initialized.

In the interrupt processing that occurs when the time stamp information is received, when the CPU receives the interrupt signal, it determines whether it is the first reception of the packet including the time stamp value or the reception of the second and subsequent packets. Make a determination. This is because, in the case of the first packet, the jitter cannot be obtained because the counter value has not been initialized. (Step 1) If the first packet including the time stamp value is received,
The time stamp value is extracted from the header information of the received packet, loaded into the counter 305, and the counter value is initialized to the received time stamp value. At this time, the lower x bits of the time stamp value and the counter value for one sample in the past are held as described above. Further, the filter delay unit is initialized. (Steps 8 to 10) If the second and subsequent packets including the time stamp value are received, the time stamp value is similarly extracted from the header information of the received packet. At this time, the lower-order xbit value of the time stamp value and the counter value is compared with a value stored as one sample in the past, and it is checked whether or not the overflow has occurred. Also, the lower-order xbit value of the time stamp value and the counter value before the correction is held as one past sample. (Steps 2 and 3) The phase comparison is performed by taking the difference between the lower xbit value of the time stamp value and the counter value to obtain the jitter. At this time, if the jitter is larger than the specified value, it is ignored as abnormal jitter without performing the subsequent filtering process. (Steps 4 and 5) If the jitter obtained by the phase comparison is within the specified value, filtering is performed by the LPF 302 and the result is output to the digital-analog conversion circuit 303. The output result to the digital-analog conversion circuit 303 is VC
This is reflected on the output frequency of the XO 304 and is fed back to the count-up cycle of the counter 305 to be compared with the phase, so that the system clock of the encoding device is reproduced with the lapse of time. (Steps 6 and 7)

[0058]

According to the invention described above, even in the case of performing both the decoding of the PS system and the decoding of the TS system, a decoding device with sufficient performance can be realized by limiting the development scale of the hardware and switching the software. Become.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a decoding device.

FIG. 2 is an internal block diagram of input stream control.

FIG. 3 is a state transition diagram of packet synchronization detection.

FIG. 4 is a functional block diagram of a PLL process.

FIG. 5 is a format example of a time stamp and a read register field of a counter of a decoding device.

FIG. 6 is a software processing flow that occurs when a time stamp is received.

[Explanation of symbols]

 0 ... General purpose bus 1 ... Local bus 2 ... Address bus 2 3 ... Data bus 4 ... Address bus 10 ... General purpose bus interface 11 ... Parallel interface 12 ... Input stream control 13 ... FIFO 14 ... Video decoding circuit 15, 17 ... FIFO 16 ... Audio decoding circuit 18 CPU 19 SRAM 20 ROM 21 Local bus control circuit 22 Video / digital-analog conversion circuit 23 Audio / digital-analog conversion circuit 24 Analog interface circuit 25 VCXO interface circuit 26 VCXO 27 ... Clock control circuit 28 ... Phase comparison circuit 29 ... Audio VCXO 100,102 ... Bidirectional buffer 101,103 ... Buffer

Claims (1)

[Claims] 1. A means for receiving data of a packet in which video and audio are multiplexed and detecting the beginning of a packet in synchronization with an externally provided clock, and at least one header pattern from a header pattern at the beginning of the packet. Means for detecting and receiving only valid packets having the following, and means for detecting a packet including system clock information of the encoding device from the header pattern of the valid packet, extracting system clock information, and notifying the CPU of the extracted information. Means for writing only the valid packet to the FIFO using an externally provided clock and reading from the FIFO using an internally generated clock; and writing the valid packet to the FIFO by the CPU.
Means for reading the valid packet from the FIFO, and means for reading all or part of the valid packet from the FIFO and outputting the remaining information of the packet to the video decoding unit or the audio decoding unit according to an instruction from the CPU. And a means for reading out all or a part of valid packets from the FIFO according to an instruction from the CPU and discarding the remaining information of the packets.