JP3801043B2 - Data receiving apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transmitting apparatus and method for transmitting image data and audio data to a LAN (Local Area Network) such as Ethernet or Fast Ethernet, and a data receiving apparatus for receiving and decoding data transmitted over the network, and Regarding the method.
[0002]
[Prior art]
As shown in FIG. 9, the network image data transmission system is configured by connecting an image data transmitting device (hereinafter referred to as “server”) 101 and an image data receiving device (hereinafter referred to as “client”) 102 via an Ethernet 100. Is done. The server 101 encodes the input video signal using MPEG (Motion Picture Expert Group) 2, converts this data into an Ethernet packet, and sends it to the Ethernet 100. The client 102 decodes the received data according to the reverse procedure of the server 101, displays the reproduced image on the monitor 103, and outputs the reproduced sound.
[0003]
FIG. 10 shows a circuit configuration of the server 101 shown in FIG. The server 101 includes an MPEG encoder circuit 111 that compresses an input video signal in MPEG2, an Ethernet circuit 112 that sends compressed data (transport stream, hereinafter referred to as TS) to the Ethernet 100, and a CPU (Central Processing Unit) that controls the entire apparatus. 113, a DRAM (Dynamic Random Access Memory) 114 for storing data to be processed by the CPU 113, and the like.
[0004]
Among them, the MPEG encoder circuit 111 mainly includes an A / D converter (including a synchronization signal separation circuit and a synchronization circuit) 121, an MPEG2 encoder LSI 122, a FIFO (First In First Out) memory 123, and a bus control circuit 124. Consists of.
[0005]
Here, a process until the input video signal is transmitted to the Ethernet 100 will be briefly described. In FIG. 10, an input video signal is converted into digital data by an A / D converter 121, compressed by an MPEG2 encoder LSI 122, and output in a transport stream format. This data is temporarily held in the FIFO memory 123, read from the FIFO memory 123 under software control of the CPU 113, passes through the bus control circuit 124, and is written to the DRAM 114 via the CPU data bus 115. The data read from the DRAM 114 is sent to the Ethernet circuit 112 with header information of UDP (User Datagram Protocol) or IP (Internet Protocol) added, and is sent out on the Ethernet 100 for each Ethernet packet IPCT.
[0006]
Next, the operation of writing the transport stream output from the MPEG2 encoder LSI 122 to the FIFO memory 123 and reading the written data will be described.
[0007]
FIG. 13 shows the timing of each signal in the server 101. The transport stream (TSDATA shown in FIG. 13B) output from the MPEG2 encoder LSI 122 may be output continuously or in bursts (intermittently) while being interrupted. FIG. 13 shows a case where the transport stream is output in bursts while being interrupted. Many of the MPEG2 encoder LSIs provided by LSI manufacturers output the VALID signal (FIG. 1 (a)) and the SYNC signal (FIG. 1 (b)) in synchronization with the data when outputting the data. . The VALID signal is an active signal during a period in which data is valid, and a high level is output during a period in which data A, B, and C in the figure are output. The SYNC signal is a signal that becomes a high level at the first byte of a TS (transport stream) packet composed of 188 bytes. A, B, and C shown in FIG. 13B indicate a state where a plurality of TS packets are output.
[0008]
The bus control circuit 124 of FIG. 10 performs write control of the FIFO memory 123 in accordance with the VALID signal and SYNC signal output from the MPEG2 encoder LSI 122, reads data from the FIFO memory 123 according to a command of the CPU 113, and receives the CPU 113 Adjust to.
[0009]
A write enable signal (hereinafter referred to as “WE signal”) and a read enable signal (hereinafter referred to as “RE signal”) output from the bus control circuit 124 are connected to the WE terminal and the RE terminal of the FIFO memory 123, respectively. A write / read operation of the FIFO memory 123 is performed according to the signal.
[0010]
As shown in FIG. 13, when the VALID signal becomes high level, the bus control circuit 124 activates the WE signal (high level in the figure) and writes data to the FIFO memory 123. At this time, the write counter of the bus control circuit 124 counts the number of bytes of the written data (see the count operation period TCO in FIG. 13D). When the VALID signal becomes low level, the bus control circuit 124 sets the WE signal to low level to stop the write operation, stop the count operation, and hold the current count value (the count holding period in FIG. 4D). TCH).
[0011]
When 1460 bytes (the meaning of the value will be described later) is written in the FIFO memory 123, the write counter of the bus control circuit 124 becomes 1460 bytes, and the MPEG interrupt signal MIRQ is output ((f) in the figure, times t1, t2). ). The MPEG interrupt signal MIRQ is input to the hardware interrupt terminal of the CPU 113 and requests the CPU 113 for interrupt processing. When an interrupt occurs, an interrupt processing routine that operates on the CPU 113 is executed to instruct the bus control circuit 124 to read the FIFO memory 123. In response to the instruction from the CPU 113, the bus control circuit 124 sets the RE signal to a high level and reads data from the FIFO memory 123. Thereafter, software processing by the CPU 113 is performed.
[0012]
Next, a method for generating and transmitting an Ethernet packet will be described.
In the conventional server, in order not to exceed the maximum length (1518 bytes) of the Ethernet packet, data equivalent to 1500 bytes is transmitted as one Ethernet packet. Therefore, in consideration of adding a header such as UDP / IP, the data area is set to 1460 bytes.
[0013]
Data read from the FIFO memory 123 is temporarily written in the DRAM 114 by software such as an interrupt processing routine that operates on the CPU 113. As shown in FIG. 11, an 8-byte UDP header and a 20-byte IP header are added to this data and sent to the Ethernet circuit 112. In the Ethernet circuit 112, a 14-byte Ethernet header is further added to this data, and one packet corresponding to 1500 bytes (1502 bytes) is completed. This is transmitted to the Ethernet 100 at the timing shown in FIG. The first packet is composed of A and B of the transport stream TSDATA, and the next packet is composed of the rest of B and C. Thus, the conventional server stores the transport stream TSDATA output from the MPEG2 encoder LSI 122 in an Ethernet packet in units of 1460 bytes and sends it out.
[0014]
On the other hand, the client 102 is composed of the Ethernet circuit 132 and the MPEG decoder circuit 131 as described above. Among these, the MPEG decoder circuit 131 is mainly composed of an MPEG2 decoder LSI and a memory (not shown). Here, the description will focus on the clock synchronization system of the MPEG2 decoder LSI.
[0015]
In the MPEG2 standard, transmission via a network such as ATM (Asynchronous Transfer Mode) is assumed, and the MPEG2 decoder (hereinafter referred to as “decoder”) on the receiving side is used on the transmitting side even in a transmission path in which a clock or control signal cannot be directly transmitted. A mechanism for synchronizing with an MPEG2 encoder (hereinafter referred to as “encoder”) is considered. This is to transmit a stream with a time stamp, and when the stream structure is a transport stream, it is called a program clock reference (hereinafter referred to as “PCR”). In addition to the payload, the TS packet has an area called an adaptation field, and PCR is added to the optional field. This is time information calculated from the system clock at the time of encoding by the encoder, and the transmission interval is defined as 100 msec or less in the standard.
[0016]
In the decoder circuit 131, this PCR is extracted from the received stream, and the system clock of the decoder itself can be synchronized with the system clock on the encoder side by a PLL (Phase Locked Loop) circuit as shown in FIG. The operation of the PLL circuit is as follows.
[0017]
FIG. 12 shows the configuration of the PLL circuit built in the MPEG2 decoder LSI. The STC (System Time Clock) in the figure is calculated by counting the 27 MHz system clock of the decoder itself by the STC counter 144. The STC counter 144 has the same configuration as the reference counter on the encoder side, and the initial PCR value extracted from the received stream is loaded to determine the initial value of the counter 144. Thereafter, the counting operation is continued in the closed loop of the PLL circuit. The comparator 141 in the closed loop compares the PCR and the current value of the STC at the time when the PCR arrives at the decoder. A voltage corresponding to the comparison result (error) is supplied to the 27 MHz VCXO (voltage controlled crystal oscillator) 143 through the low pass filter 142, and the frequency 27 MHz of the clock signal CL27M is adjusted.
[0018]
In this way, the decoder circuit 131 can match the system clock frequency of the encoder by finely adjusting the clock based on the PCR added by the encoder.
[0019]
[Problems to be solved by the invention]
As described above, the server 101 transmits each Ethernet packet corresponding to 1500 bytes. FIG. 13H shows the timing at this time. However, of course, there is a delay time TD before the data transmitted from the encoder (server side) 111 arrives at the decoder (client side) 131. If the delay time TD is constant, the client 102 receives data at the timing (i) of FIG. The client 102 extracts a 188-byte TS packet from the Ethernet packet received at this timing and passes it to the decoder 131. Here, when attention is paid to the arrival time of TS packets (time interval of TS packets), the reception timing shown in (i) of the figure is different from the timing output from encoder LSI 122 of server 101 ((b) of the figure). Yes. If the time interval of the TS packet changes, the arrival time interval of the PCR added in the TS packet also changes.
[0020]
In the PLL circuit mounted on the decoder LSI, the PCR and the STC are compared at the time when the PCR arrives. Therefore, if there is a deviation in the packet time interval, the error in the comparison result increases. As a result, the PLL circuit is adjusted to an incorrect frequency, and the system clock of the decoder 131 is not synchronized with the system clock of the encoder 111. If this state continues for a while, the buffer provided in the client 102 overflows or underflows, causing a problem that the decoded image is disturbed.
[0021]
As described above, the data transmission between the server and the client has a delay time, and the actual PCR arrival time includes this delay time. In the PLL circuit built in the decoder LSI of the client 102, the PCR and STC are compared at the time when the PCR arrives at the decoder 131, so that the delay time between the server and the client is required to be constant.
[0022]
However, in a bus-type transmission line such as Ethernet, this delay time is not always constant and has some jitter. In such a transmission line, if the arrival time of the PCR, that is, the arrival time of the TS packet fluctuates due to jitter, an error between the PCR and the STC in the comparator 141 of the PLL circuit occurs. As a result, the PLL circuit is adjusted to an incorrect frequency, and the system clock of the decoder 131 is not synchronized with the system clock of the encoder 111. If this state continues for a while, the buffer provided in the client 102 overflows or underflows, and the decoded image stops or skips.
[0024]
  The present invention has been made in consideration of the above points.A data receiving device capable of absorbing jitter in a transmission path even when there is a gap in packet intervals in packet stream format data received via a networkAnd methodsTo provideEyesTarget.
[0026]
  UpNoteClaims to achieve1The invention described in claim 1 is a packet stream composed of packets storing data subjected to information compression processing transmitted via a network, receiving a packet stream into which time reference information is inserted at a predetermined time interval, In a data receiving apparatus for decoding a received packet stream, storage means for storing the received packet stream, and time reference information included in the packet streamA jitter detection signal and a delay status signal based on a change in a delay time generated in the transmission line by comparing the difference with a preset threshold value.DetectInspectionMeans of exiting,The testDetected by exit meansWhen the jitter detection signal is at a high level and the delay status signal is at a low level, the read clock of the storage means is switched to a frequency higher than a standard frequency to increase the reading speed, while the jitter detection signal and Read clock control for adjusting the delay time generated in the transmission path by switching the read clock of the storage means to a frequency lower than the standard frequency and lowering the read speed when both of the delay status signals become high levelWith means,Reading data by the read clock control meansThe adjusted packet stream is decoded.
[0028]
ContractClaim2The invention described in claim 1 is a packet stream composed of packets storing data subjected to information compression processing transmitted via a network, receiving a packet stream into which time reference information is inserted at a predetermined time interval, In a data reception method for decoding a received packet stream, the received packet stream is stored in a storage means, and time reference information included in the packet streamA jitter detection signal and a delay status signal based on a change in a delay time generated in the transmission line by comparing the difference with a preset threshold value.Detected and detectedWhen the jitter detection signal is at a high level and the delay status signal is at a low level, the read clock of the storage means is switched to a frequency higher than a standard frequency to increase the reading speed, while the jitter detection signal and When both of the delay status signals are at a high level, the delay time generated in the transmission line is reduced by switching the read clock of the storage means to a frequency lower than the standard frequency to reduce the read speed.AdjustRead the dataThe adjusted packet stream is decoded.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a data transmission apparatus according to an embodiment of the present invention. The configuration shown in FIG. 1 is the same as the configuration of the conventional data transmission apparatus shown in FIG. That is, the server 1 shown in FIG. 1 includes an MPEG encoder circuit 11 that compresses an input video signal in MPEG2, an Ethernet circuit 12 that transmits compressed data (transport stream) to the Ethernet 100, and a CPU (Central Processing Unit) 13, DRAM (Dynamic Random Access Memory) 14 that temporarily stores data to be processed, and the like.
[0030]
Among them, the MPEG encoder circuit 11 mainly includes an A / D converter (including a synchronization signal separation circuit and a synchronization circuit) 21, an MPEG2 encoder LSI 12, a FIFO (First In First Out) memory 23, a bus control circuit 24, and the like. Consists of.
[0031]
The conventional server 101 shown in FIG. 10 transmits every Ethernet packet corresponding to 1500 bytes. For this reason, the transport stream (TS) output from the encoder LSI 122 is processed every 1460 bytes. As a result, the time interval of the TS packets is lost, causing the PLL circuit of the client to malfunction. Therefore, in this embodiment, data is handled in units of TS packets (188 bytes), and an Ethernet packet is generated every period when the VALID signal is at a high level.
[0032]
In the server 1 shown in FIG. 1, the operation of the bus control circuit 24 is different from that of the path control circuit 124 shown in FIG. Therefore, a method for generating and transmitting an Ethernet packet will be described while explaining the hardware operation centered on the bus control circuit 24.
[0033]
FIG. 2 is a timing chart showing the data timing of the server 1. TSDATA in FIG. 6B shows a state in which the transport stream is output from the MPEG2 encoder LSI 22 in a burst rather than continuously. The VALID signal in FIG. 9A is a signal that is active (high level in the figure) during a period in which data is valid, and the SYNC signal in FIG. 10C is the first byte of a TS packet composed of 188 bytes. The signal becomes high level. TSDATA packet groups A, B, and C represent a state in which a plurality of TS packets are output.
[0034]
When the VALID signal becomes high level, the TS packet group A is output from the MPEG2 encoder LSI 22 at the timing shown in FIG. In the bus control circuit 24, while the VALID signal is at a high level, a write enable signal (hereinafter referred to as “WE signal”) is made active (high level in the figure) and this data is written into the FIFO memory 23. At this time, in the bus control circuit 24, the write counter counts the number of bytes of the written data, and this operation is shown in the count operation period TCO in FIG.
[0035]
The bus control circuit 24 sets the interrupt request signal MIRQ to a high level when the value of the write counter reaches a preset value (for example, 188 bytes). This interrupt request signal MIRQ is connected to the hardware interrupt terminal of the CPU 13 and requests the CPU 13 for interrupt processing. When an interrupt occurs, an interrupt processing routine (see FIG. 3A) operating on the CPU 13 is executed, and the bus control circuit 24 activates a read enable signal (hereinafter referred to as “RE signal”) according to an instruction from the CPU 13 (high level). ) To read data from the FIFO memory 23. At this time, the signal obtained by delaying the VALID signal by 188 bytes is used for the RE signal, so that the FIFO memory 23 is read while maintaining the time interval of the TS packets.
[0036]
On the other hand, when the VALID signal becomes low level, the WE signal is changed to low level to stop the write operation, and the write counter is reset to prepare for the next VALID signal (reset period TCR in FIG. 2D).
The packet group A read from the FIFO memory 23 is sent with an 8-byte UDP header and a 20-byte IP header to the Ethernet circuit 12 as shown in FIG. The Ethernet circuit 12 adds a 14-byte Ethernet header to this data and transmits it as an Ethernet packet on the network 100. Even if the packet group A is less than 1460 bytes, an Ethernet packet is generated from the data and transmitted. When the packet group A is 1460 bytes or more, a plurality of Ethernet packets are generated and transmitted.
[0037]
Next, when the VALID signal becomes high level, the TS packet group B is output from the encoder LSI 22, and an Ethernet packet is generated and transmitted by the packet group B in the same procedure.
Although the transmission time may be shifted in the Ethernet circuit 12 when the packet is transmitted by the above operation, the transmission timing shown in FIG. 2H is the same as the timing output from the encoder LSI 22 (FIG. 2B). Almost equal. Therefore, the TS packet time interval is not greatly shifted during transmission.
[0038]
Further, when there is no jitter in the delay time between the server and the client, the packet reception timing is the timing shown in FIG. Since the client can take out TS packets every 188 bytes from this reception timing, the TS packets can be passed to the decoder LSI while maintaining the PCR arrival time interval. As a result, the malfunction of the PLL circuit built in the decoder LSI can be prevented, and the phenomenon that the system clock of the decoder is not synchronized with the system clock on the encoder side can be avoided. Therefore, it is possible to minimize the disturbance of the decoded image.
[0039]
Next, the operation of software in the CPU 13 will be described.
The software running on the CPU 13 mainly performs a read operation of the FIFO memory 23 and an Ethernet packet generation. Here, the actual operation of the software will be described with reference to the flowchart shown in FIG.
[0040]
When the VALID signal goes high and 188 bytes of data are written to the FIFO memory 23, the interrupt signal MIRQ goes high and the interrupt processing routine (MPEG interrupt routine in FIG. 3A) is executed.
In step S11, it is checked whether or not the RE signal is at a high level. If the RE signal is at a high level, a read operation is executed (step S12). If the level is low, the read operation is completed, and the process proceeds to step S13.
[0041]
In step S12, the bus control circuit 24 is instructed to perform a read operation of the FIFO memory 23. In response to this instruction, data is read from the FIFO memory 23 by the bus control circuit 24 and written in the MPEG area secured on the DRAM 14. Thereafter, the process returns to step S11.
[0042]
In step S13, since all the data written during the period in which the VALID signal is at a high level has been read, the MPEG transmission application (FIG. 5B) is called and the MPEG interrupt routine is terminated.
Next, the MPEG transmission application ((b) in the figure) called by the MPEG interrupt routine is started.
[0043]
In step S21, 1460 bytes of data are read from the MPEG area of the DRAM 14. Read all if less than 1460 bytes.
In step S22, an 8-byte UDP header and a 20-byte IP header are added to this data.
[0044]
In step S23, this data is written in the data area of the Ethernet circuit 12, and a transmission start procedure is performed.
Thereafter, hardware processing by the Ethernet circuit 12 is performed. Further, a 14-byte Ethernet header is added to this data to generate a 1502-byte packet. This is sent to the Ethernet 100 as one Ethernet packet.
[0045]
In step S24, it is checked whether or not there is data written in the MPEG area of the DRAM 14, and if data remains, the process returns to step S21 to execute the processes in steps S21 to S23 until there is no more data in the MPEG area. Repeat the generation and transmission of Ethernet packets.
[0046]
When the answer to step S24 is negative (NO) and all the Ethernet packets are transmitted, the MPEG transmission application is terminated.
As described above, the generation and transmission of the Ethernet packet is performed at the timing of the signal obtained by delaying the VALID signal for a certain time, thereby minimizing the time interval difference between the TS packets. As a result, the client can suppress the shift in the arrival time of the PCR, so that the malfunction of the PLL circuit built in the decoder can be prevented.
[0047]
FIG. 4 is a block diagram showing a circuit configuration of the data receiving apparatus according to the first embodiment of the present invention. The data receiving apparatus, that is, the client 2 includes an Ethernet circuit 32 that receives a transmitted packet, an MPEG decoder circuit 31 that decodes data received from the Ethernet circuit 32, a CPU 33 that controls the entire circuit, and data to be processed And a DRAM 34 for temporarily storing.
[0048]
Among these, the MPEG decoder circuit 31 includes a bus control circuit 41, a FIFO memory 42, an MPEG2 decoder LSI 43, a jitter detection circuit 44, and a read clock control circuit 45. First, Ethernet, IP, and UDP protocol headers are removed from the Ethernet packet received by the Ethernet circuit 32 and stored in the DRAM 34. The bus control circuit 41 reads data from the DRAM 34 and writes it to the FIFO memory 42. The data read from the FIFO memory 42 is input to the MPEG2 decoder LSI 43, decoded, and output as a video signal.
[0049]
Next, a detection method when jitter occurs in the transmission line (Ethernet 100) and a method for adjusting data to be passed to the decoder will be described.
[0050]
FIGS. 5A and 5B show the timing relationship between the Ethernet packet at the time of transmission and the received Ethernet packet. Data A is received after the delay time TDa has elapsed, and the next data B is the transmission path. Since jitter has occurred, the signal is received after the delay time TDb has elapsed. When this data B is enlarged and viewed in units of TS packets, the arrival time of the PCR added in the packet is delayed as compared with the original TS packet, as shown in FIGS. Yes. If such a state continues for a while, the system clock of the decoder is not synchronized with the encoder side as mentioned in the problem.
[0051]
Therefore, in this embodiment, a jitter detection circuit 44 and a read clock control circuit 45 are provided to adjust the timing of data passed to the decoder LSI 43.
First, the jitter detection circuit 44 extracts the first PCR (FIG. 6C) from the received stream TS1. The jitter detection circuit 44 includes a counter similar to the STC counter shown in FIG. 12 and counts the 27 MHz clock CL27M input from the decoder LSI 43 to generate an STC. Next, the generated STC is compared with the first PCR extracted from the stream. This comparison result (difference between STC and PCR) is compared with a preset threshold value. As this threshold value, an error value of STC and PCR generated in an environment where there is no jitter in the transmission path is set. That is, it can be seen that when the comparison result between the STC and the PCR greatly deviates from the threshold value, jitter has occurred in the transmission path.
[0052]
When detecting the jitter, the jitter detection circuit 44 outputs a jitter detection signal SJ to the read clock control circuit 45. The jitter detection signal SJ is usually at a low level, but becomes a high level when jitter is detected. Further, simultaneously with the signal SJ, a delay status signal SD is output in accordance with the delay amount of PCR. The delay status signal SD is a signal that is at a low level when the extracted PCR is behind the STC and at a high level when it is ahead of the STC. In addition, the jitter detection circuit 44 receives data read from the FIFO memory 42, and extracts the jitter-corrected PCR from this data.
[0053]
Next, the actual operation of the apparatus shown in FIG. 4 will be described.
The STC shown in FIG. 6B represents the STC value calculated by counting the 27 MHz clock in the jitter detection circuit 44. The first PCR shown in FIG. 6C shows the PCR value extracted from the received stream TS1, and the second PCR shown in FIG. 10D is the PCR value extracted from the stream TS2 read from the FIFO memory 24. . Here, the STC and PCR values are shown as simple integers, but the actual values are different.
[0054]
When several packets are received, the effect of the PLL circuit built in the decoder LSI 43 appears, and the frequencies of the system clocks of the encoder and decoder gradually become equal. At this time, the first PCR extracted from the stream has a value close to STC. However, when jitter occurs in the transmission path, the arrival time of the first PCR is delayed, and the STC counter continues counting during that time, so the extracted first PCR is delayed from the STC value. This state is represented by the x period shown in FIG. 6C. When the extracted first PCR is 10, the current value of STC is 80. At this time, the difference between the STC and the first PCR is 70, which exceeds the threshold value (for example, the setting value is 50), so that it is detected that jitter has occurred.
[0055]
When jitter is detected in this way, the jitter detection signal SJ becomes a high level and the delay status signal SD becomes a low level. The read clock control circuit 45 having obtained this information switches the read clock to a frequency higher than the standard frequency (for example, twice the frequency) and outputs it, as shown in FIG. As a result, the data read from the FIFO memory 42 is twice as fast as the normal speed, and the transfer rate of data passed to the decoder LSI 43 is also increased. Therefore, the second PCR extracted from the data TS2 also proceeds as 11, 12, 13, 14,... At twice the speed, and eventually catches up with the STC value and absorbs jitter. When the values of the second PCR and STC match, the read clock is switched to the standard frequency to return to the normal transfer rate.
[0056]
In this way, by changing the frequency of the read clock of the FIFO memory 42, large jitter can be removed from the data passed to the decoder LSI 43. Also, here, the read clock has been described with a frequency twice as high as the standard, but if this is set to 4 times, 8 times,..., Jitter can be absorbed in a shorter time.
[0057]
By the above operation, it is possible to avoid a phenomenon in which the PLL circuit with a built-in decoder malfunctions due to jitter in the transmission path. As a result, the problem that the system clock of the decoder is not synchronized with the encoder side can be solved.
So far, the case where the delay time of the transmission path is increased has been described. However, the delay time between the server and the client may be suddenly shortened due to a change in the path of the transmission path. In such a case, the extracted first PCR advances beyond the current value of STC. At this time, both the jitter detection signal SJ and the delay status signal SD are at a high level, and the read clock control circuit 45 sets the read clock of the FIFO memory 42 at a frequency lower than the standard (for example, 1/2 times, 1/4 times, etc.). ), The data is read from the FIFO memory 42 at a transfer rate lower than normal, and is input to the decoder LSI 43. Thus, even when the delay time is shortened, the malfunction of the PLL circuit can be prevented by adjusting the transfer rate.
[0058]
(Second Embodiment)
In the present embodiment, the server 1 corresponds to the case where the transport stream is continuously output from the MPEG2 encoder LSI. The circuit configuration is the same as that of the first embodiment, but the operation of the bus control circuit 24 is different. Therefore, an Ethernet packet generation and transmission method will be described while explaining the hardware operation centered on the bus control circuit 24.
[0059]
First, the transmission unit of the Ethernet packet in this embodiment will be described.
In order not to malfunction the PLL circuit on the client side, it is necessary to maintain the time interval of TS packets from the transmission stage. Therefore, in the present embodiment, one Ethernet packet is created from seven pieces of data (1316 bytes) of a TS packet composed of 188 bytes.
[0060]
FIG. 7 shows the data timing of the server and the client of this embodiment.
TSDATA in FIG. 6A represents the state of TS packets continuously output from the MPEG2 encoder LSI 22 without interruption. Data is divided into units of 1316 bytes, and A, B, C, D, E,. It is called.
[0061]
Next, the read operation of the FIFO memory 23 by the bus control circuit 24 will be described.
The VALID signal (not shown) is always in an active state (high level) because data is always output from the MPEG2 encoder LSI 22. Further, the SYNC signal shown in FIG. 7B is a signal that becomes a high level at the first byte of the 188-byte TS packet, and is also output without interruption.
[0062]
While the VALID signal is at a high level, the bus control circuit 24 makes a WE signal (not shown) active (high level) and writes data into the FIFO memory 23. Since the VALID signal is always high, the WE signal is also high and writing is always performed.
[0063]
At this time, the bus control circuit 24 counts the number of bytes of data written by the write counter, and the write counter counts from 0 to 1315 and returns to 0 again as shown in FIG. do. When the count value reaches 1315, the bus control circuit 24 sets the interrupt request signal MIRQ ((d) in the figure) to a high level. The interrupt request signal MIRQ is connected to the hardware interrupt terminal of the CPU 14 and requests the CPU 14 for interrupt processing. When an interrupt occurs, an interrupt processing routine (FIG. 8A) that runs on the CPU 14 is executed, and the bus control circuit 24 activates the RE signal (FIG. 7E) in response to an instruction from the CPU 14 (FIG. 7E). Then, 1316 bytes of data are read from the FIFO memory 23. The read clock of the FIFO memory 23 uses a clock having a frequency higher than that of the write clock (for example, a frequency twice as high as that of the write clock), and performs reading at a high speed with respect to the write side. This is to allow the CPU 14 and the Ethernet circuit 12 to take sufficient time to add each protocol header such as UDP before the next 1316 bytes are read.
[0064]
The CPU 14 adds an 8-byte UDP header and a 20-byte IP header to the 1316-byte data read from the FIFO memory 23 and passes this to the Ethernet circuit 12. The Ethernet circuit 12 adds a 14-byte Ethernet header to this data and sends it out as an Ethernet packet onto the network.
[0065]
By the above operation, as shown in FIG. 7F, an Ethernet packet can be transmitted for each TS packet group A, B, C... Output from the encoder LSI 22. However, since the frequency of the read clock of the FIFO memory 23 is doubled, there is an interval between data to be transmitted. Therefore, the arrival time of the packet (PCR decoder arrival time) is shifted by the amount of data interval. Therefore, this deviation is corrected by using the data receiving apparatus (client) shown in FIG. 4 described in the first embodiment.
[0066]
When packets are transmitted by the Ethernet circuit 12, the transmission timing may be slightly deviated due to reasons such as network conditions and presence / absence of received packets. In addition, the packet interval may be vacated for the reasons described above. FIG. 7G shows the timing of the Ethernet packets A, B, C... At the time of reception, and shows a state in which the packet interval is free. Further, in a transmission line such as Ethernet, jitter may occur in the delay time between the server and the client, and the arrival times of data B and D in FIG. 5G are delayed, and jitters indicated by Δa and Δb respectively. Has occurred.
[0067]
Therefore, using the data receiving apparatus (client) shown in FIG. 4, the transmission timing shift and the transmission path jitter are corrected. In the client of FIG. 4, as already described, the received data is temporarily held in the FIFO memory 42, and the transfer frequency of the data input to the decoder LSI 43 is adjusted by changing the clock frequency on the reading side. FIG. 7 (h) shows this state, and the transfer rate is controlled as follows.
[0068]
Since the data A is concentrated in the first half part, the arrival time is earlier, and the first PCR extracted from the received data is advanced from the current value of the STC in the comparator of the jitter detection circuit 44. In this case, the read clock of the FIFO memory 42 is switched to a low frequency, and data is transferred to the decoder LSI 43 at a low transfer rate (white arrow a). Eventually, when the second PCR extracted from the read data matches the STC and the deviation in arrival time is corrected, the clock is returned to the original standard frequency.
[0069]
In the next data B, since the arrival time of the packet is delayed due to the occurrence of jitter, the first PCR is delayed from the current value of the STC. In this case, the read clock is switched to a high frequency and input to the decoder LSI 43 at a high transfer rate (black arrow b1). Eventually, the second PCR matches the STC, but the data B is also concentrated in the first half of the data B, so the second PCR proceeds from the middle. Therefore, the transfer rate is switched to a low transfer rate (white arrow b2) from the middle. Similarly for the next data C and D, the transfer rate is controlled as indicated by the arrows shown in FIG.
[0070]
As described above, the deviation of the transmission time of the Ethernet packet can correct the timing of data together with the jitter of the transmission line at the stage before being input to the decoder LSI 43 by using the client of FIG. As a result, the malfunction of the PLL circuit built in the decoder LSI 43 can be prevented, and the phenomenon that the system clock of the decoder is not synchronized with the encoder side can be avoided. Therefore, it is possible to minimize the disturbance of the decoded image.
[0071]
Next, the software operation in this embodiment will be described with reference to the flowchart shown in FIG.
When 1316 bytes of data are written in the FIFO memory 23, the interrupt request signal MIRQ becomes high level, and the interrupt processing routine (MPEG interrupt routine of FIG. 8A) is executed.
[0072]
In step S31, the bus control circuit 24 is instructed to perform a read operation of the FIFO memory 23. In response to this instruction, the bus control circuit 24 reads out 1316 bytes (7 TS packets) of data from the FIFO memory 23 and writes it in the MPEG area secured on the DRAM 14.
[0073]
In step S2, an MPEG transmission application (FIG. 5B) is called to end the MPEG interrupt routine.
The called MPEG transmission application is then started.
In step S41, 1316-byte data is read from the MPEG area of the DRAM.
[0074]
In step S42, an 8-byte UDP header and a 20-byte IP header are added to this data.
In step S43, this data is written in the data area of the Ethernet circuit 12, and a transmission start procedure is performed.
[0075]
Thereafter, hardware processing by the Ethernet circuit 12 is performed. With this hardware processing, a 14-byte Ethernet header is further added to this data, resulting in a 1358-byte packet. This is sent to the Ethernet as one packet.
[0076]
In the embodiment described above, image data has been described as an example, but audio data is similarly processed.
[0078]
【The invention's effect】
As detailed aboveClaim1Or2The received packet stream is stored in the storage means, and the time reference information included in the received packet streamAnd a delay status signal based on a change in delay time generated in the transmission line by comparing the difference with a preset threshold value.Is detected. And detectedWhen the jitter detection signal is at a high level and the delay status signal is at a low level, the read clock of the storage means is switched to a frequency higher than the standard frequency to increase the reading speed, while the jitter detection signal and the delay status signal are Delay time generated on the transmission line by switching the read clock of the storage means to a frequency lower than the standard frequency and lowering the read speed when both become high levelsIs adjusted,Reading the dataIs decoded. Therefore, even when there is a time lag in the packet interval in the received packet stream, the time lag can be absorbed and disturbance of the decoded signal can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data transmission apparatus according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining data processing timing in the apparatus shown in FIG. 1;
3 is a flowchart of processing (first embodiment) executed by the CPU shown in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a data receiving apparatus according to an embodiment of the present invention.
FIG. 5 is a timing chart for explaining a timing shift of a program time base reference value (PCR) due to jitter generated on the network.
6 is a timing chart for explaining data processing in the apparatus shown in FIG. 4;
FIG. 7 is a timing chart for explaining the timing of data processing in the second embodiment of the present invention;
8 is a flowchart of processing (second embodiment) executed by the CPU shown in FIG. 1; FIG.
FIG. 9 is a block diagram showing a configuration of a general network image data transmission system.
10 is a block diagram showing a configuration of the image data transmitting apparatus shown in FIG.
FIG. 11 is a diagram for explaining the addition of a header according to a communication protocol.
FIG. 12 is a block diagram showing a configuration of a phase-locked loop circuit that generates a system clock based on a program time reference reference value (PCR).
13 is a timing chart for explaining the timing of data processing in the apparatus shown in FIG.
[Explanation of symbols]
  1 Image data transmitterPlace
  2 Image data receiverPlace
  11 MPEG encoder circuit
  12 Ethernet timesRoad
  13 CPU
  14 DRAM
  22 MPEG2 encoder LSI
  23 FIFO memoRe
  24 Bus control timesRoad
  31 MPEG decoder circuit
  32 Ethernet circuit
  33 CPU
  34 DRAM
  41 Bus control circuit
  42 FIFO memory (storage means)
  43 MPEG2 Decoder LSI
  44 Jitter detection circuit(InspectionOut method)
  45 Read clock control circuit (Read clock controlmeans)

Claims (2)

A packet stream consisting of packets storing information-compressed data transmitted over a network, receiving a packet stream in which time reference information is inserted at predetermined time intervals, and decoding the received packet stream In the data receiving device
Storage means for storing the received packet stream;
Jitter detection based on a change in delay time generated in a transmission line by obtaining a difference between time reference information included in the packet stream and a value obtained by counting a system time clock of a decoder circuit and comparing the difference with a preset threshold value and detection means that detect the signal and the delay situation signal,
When the jitter detection signal detected by the detection means is at a high level and the delay status signal is at a low level, the read clock of the storage means is switched to a frequency higher than the standard frequency to increase the read speed. On the other hand, when both the jitter detection signal and the delay status signal are at a high level, the read clock of the storage means is switched to a frequency lower than the standard frequency to reduce the reading speed, and is generated in the transmission line. Read clock control means to adjust the delay time ,
A data receiving apparatus for decoding a packet stream whose data read is adjusted by the read clock control means . A packet stream consisting of packets storing information-compressed data transmitted over a network, receiving a packet stream in which time reference information is inserted at predetermined time intervals, and decoding the received packet stream In the data receiving method
Storing the received packet stream in storage means;
Find the difference between the time reference information contained in the packet stream and the value counted by the system time clock of the decoder circuit,
Detecting the jitter detection signal and the delay status signal based on a change in the delay time generated in the transmission path by comparing the difference with a preset threshold ;
When the detected jitter detection signal is at a high level and the delay status signal is at a low level, the read clock of the storage means is switched to a frequency higher than a standard frequency to increase the read speed, while the jitter When both the detection signal and the delay status signal are at a high level, the delay time generated in the transmission path is adjusted by switching the read clock of the storage means to a frequency lower than the standard frequency and reducing the read speed. ,
A data receiving method, comprising: decoding a packet stream adjusted to read out the data.

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