JPH11308203A - Clock reproduction system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a simple signal receiver that receives a packet signal including time information added to absorb network jitter and time information added to reproduce a clock so as to recover the clock without affecting the network jitter. SOLUTION: A program clock reference(PCR) extracted by an MPEG 2 TS demultiplexer 7 is corrected from difference information between a value indicated by a cycle timer 5 at a time point when a source packet header elimination/time stamp extract device 12 transfers data to the post-stage MPEG 2 TS demultiplexer 7 and a time stamp extracted by the source packet header elimination/time stamp extract device 12. Through the processing, the effect of network jitter is not affected on clock reproduction loops 13, 7, 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus provided in a packet signal receiving apparatus for reproducing a clock necessary for restoring a received packet.

[0002]

2. Description of the Related Art FIG. 4 shows, for example, IEEE1394, ISO / IEC1381.
8-1, -2 and 3, HD DIGITAL VCR CONFERENCE PART4 Sp
ecifications of MPEG DATA Transmission for Consume
FIG. 2 is a block diagram illustrating a configuration of a conventional signal receiving device configured with devices conforming to the r-UseDigital Interface, which is a device for receiving an MPEG2 transport stream on a high-speed serial bus IEEE1394 bus.

In FIG. 1, reference numeral 1 denotes an IEEE 1394 bus having a high-speed transfer band but containing jitter, 2 denotes an IEEE 1394 interface for receiving a packet transmitted on the IEEE 1394 bus 1,
Reference numeral 3 denotes a FIFO memory for buffering an MPEG2 transport stream, which is a payload of a received packet, for reconstructing the same, and 4 denotes a time stamp extracting apparatus for extracting a time stamp indicating a timing at which the reconstructed payload is output to a subsequent stage. 5 is local 24.576MHz
A cycle timer that counts up with the clock of
The cycle timer 5 is calibrated based on the absolute time information detected by the IEEE1394 interface 2 at regular intervals.

Reference numeral 6 denotes an output timing control device for notifying the time stamp extracting device 4 of a timing at which the value of the time stamp extracted by the time stamp extracting device 4 matches the value of the cycle timer 5, and 7 an MPEG2 transport stream demultiplexer. (Hereinafter referred to as “MPEG2 TS demultiplexer”) extracts a program clock reference (PCR) included in the MPEG2 transport stream in order to reproduce a 27 MHz system clock.

[0005] Upon receiving the transfer notification from the output timing control device 6, the time stamp extraction device 4 outputs the reconstructed MPEG2 transport stream to the MPEG2 TS demultiplexer 7. Reference numeral 8 denotes a local counter, which is incremented by a clock recovered 27 MHz system clock. Reference numeral 9 denotes a VCXO controller, which uses a PCR and a local counter 8 to reproduce a 27 MHz system clock.
The VCXO 10 is controlled on the basis of the information on the value of the clock signal to realize clock recovery. The MPEG2 data is transmitted from the MPEG2TS demultiplexer 7 to the MPEG2 A / V decoder 1
Transferred to 1.

In the above system, the payload is buffered by the time stamp extracting device 4 until the notification that the timing specified by the time stamp has been reached by the output timing control device 6, so that the IEEE1394 bus can be used. The above jitter can be absorbed, and the clock can be accurately reproduced without affecting the reproduction of the 27 MHz system clock at the subsequent stage.

[0007]

In the conventional processing as described above, the output timing control device notifies the timing of transferring the MPEG2 transport stream to the MPEG2 TS demultiplexer. In order to detect the timing, it is necessary to always compare the value of the cycle timer with the value of the time stamp extracted by the time stamp extracting device. When this processing is realized by software, the comparison operation must be continuously performed, so that the load required for this processing increases, which greatly affects the performance of other software processing.

Further, when the result of the comparison operation matches, if data is not instantaneously transferred to the MPEG2 TS demultiplexer, the clock recovery at 27 MHz is affected, and a high-speed CPU is required. On the other hand, when the output timing control device is realized by hardware, an extra 32-bit comparison operation circuit is required. Furthermore, an extra buffer is required because the data must be held in the time stamp extraction device until the value of the cycle timer becomes equal to the value of the time stamp.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a clock reproducing apparatus capable of executing accurate clock reproduction with a simple configuration regardless of whether it is configured by software or hardware. With the goal.

[0010]

A clock recovery apparatus according to the present invention is a clock recovery apparatus for receiving a packet signal via a transmission line having jitter, wherein the payload of the packet is extracted. Means for detecting transmission line absolute time information of the transmission line from the packet, absolute time clocking means for periodically adjusting the time with the transmission line absolute time information, and accurately detecting data contained in the payload. Means for extracting data transfer reference time information included in the payload required for reproduction, and extracting clock reproduction reference time information required for reproducing a clock for accurately reproducing data included in the payload Means for detecting the absolute time at which the payload was transferred to the clock reproduction reference time information extracting means. Output means, control signal generating means for reproducing a clock necessary for accurately reproducing the data from the transfer time information, the data transfer reference time information, and the clock reproduction reference time information, and a reproduced clock. The local time counting means is counted up by.

The control signal generating means generates a control signal by correcting the clock reproduction reference time information from the transfer time information from the transfer time detection means and the data transfer reference time information.

Further, in the control signal generating means,
The control signal is generated by correcting the counter value from the local time counting means based on the transfer time information from the transfer time detecting means and the data transfer reference time information.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described with reference to the drawings showing the embodiments. Embodiment 1 FIG. The communication system includes a transmitting device and a receiving device. In order to transfer the MPEG2 transport stream at high speed in real time from the transmitting device, an IEEE13
94 Transmission via bus 1 For this purpose, a signal is transmitted in the format shown in FIG. When transmitting an MPEG2 transport stream over the IEEE1394 bus, a source packet that specifies at what timing the packet should be transferred to the receiving MPEG2 TS demultiplexer on the receiving side in order to absorb jitter on the IEEE1394 bus A time stamp called a header (SPH) is added to the beginning of each packet of the MPEG2 transport stream to form a source packet.

Further, in order to effectively use the bandwidth of the IEEE1394 bus, the source packet is divided into a plurality according to the transfer rate, and a header is added to form the IEEE1394 packet. Further, on the IEEE1394 bus, a packet carrying absolute time information on the bus, called a cycle start packet, is transmitted every 125 μs. The MPEG2 transport stream is composed of 188 bytes per packet as shown in FIG. 6, and a program clock reference (PC) is used to enable the receiving side to correctly reproduce the system clock on the transmitting side and to reproduce the MPEG2 stream correctly.
R).

FIG. 1 shows a receiving apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an IEEE1394 input packet signal having an MPEG2 transport stream as a payload. 2 is an IEEE1394 interface for extracting a payload from an IEEE1394 packet structure, 3 is a FIFO memory for reconstructing a divided MPEG2 transport stream as a payload, 12 is a source packet header removal / time stamp extraction device, and extracts SPH. Then, the MPEG-2 transport stream is transferred to the subsequent MPEG2 TS demultiplexer.

Reference numeral 7 denotes an MPEG2 TS demultiplexer, which is a PCR
Is extracted and the MPEG2 stream is transferred to the MPEG2 A / V decoder 11. Reference numeral 5 denotes a cycle timer which counts the absolute time of the IEEE 1394 which is adjusted every 125 μs based on the absolute time information from the cycle start packet detected by the IEEE 1394 interface 2. Reference numeral 13 denotes a cycle timer and a time stamp holding device, which holds the SPH extracted by the source packet header removing / time stamp extracting device 12, and furthermore, a source packet header removing / time stamp extracting device 1.
2 holds the cycle timer value when the MPEG2 transport stream is transferred to the MPEG2 TS demultiplexer 7.

Reference numeral 8 denotes a local counter for clock recovery counted by the clock-regenerated 27 MHz system clock, 10 denotes a 27 MHz VCXO, 9 denotes a VCXO controller for controlling the VCXO 10, and 14 denotes a PCR correction / difference calculator. ,
The PCR is corrected from each information from the cycle timer and the time stamp holding device 13 and the PCR extracted from the MPEG2 TS demultiplexer 7, the difference between the counter value of the local counter 8 is obtained and transferred to the VCXO controller 9, and the 27 MHz system Phased lock loop (PLL) for clock recovery
Is configured.

The source packet header removing / time stamp extracting device 12 transfers the MPEG2 transport stream to the MPEG2 TS demultiplexer 7 immediately without buffering until the time represented by SPH as in the prior art.
Therefore, the MPE input to the MPEG2 TS demultiplexer 7
The G2 transport stream contains jitter that has been transmitted through the 1394 bus without being removed. For this reason, the PCR extracted by the MPEG2 TS demultiplexer 7 also contains jitter, and if this is used as it is for clock recovery as a reference, erroneous clock recovery will occur.

Therefore, means for compensating the jitter is required. The MPEG2 transport stream is input to the MPEG2 TS demultiplexer 7 without performing time management and buffering processing for jitter absorption at the preceding stage. Therefore, the extracted PCR value is extracted earlier than the time when it should arrive.

In the prior art, the VCXO controller 9 in FIG. 4 compares the local counter value with the extracted PCR value, and controls the frequency generated by the 27 MHz VCXO 10 according to the difference value. If the VCXO controller 9 performs the same processing as in the prior art using the PCR extracted earlier as it is, the PCR value is extracted earlier than the timing at which it should be detected, so the PCR value is larger than the local counter value. Should be 27 MHz, the local counter is incremented by 27 MHz.
Control for increasing the output frequency of the zVCXO 10 will be performed.

However, the fact is that the system clock frequency of 27 MHz is not actually low, but the reason is that the MPEG2 transport stream was input to the MPEG2 TS demultiplexer 7 earlier than the originally arrived timing without buffering. In order to compensate for this problem, the PCR correction / difference calculator 14 shown in FIG. 1 calculates how quickly the data has been extracted, and adds the corresponding value to the PCR value to correct the PCR value. it can.

In this process, the PCR correction / difference calculating device 14 performs PCR correction as follows. In FIG. 2, δ is 139
Maximum delay time on 4 buses, t _i is 188 bytes of MPEG
4 byte timestamp on transport packet
(T _stmpi = t _i + δ), the time when a 192 byte source packet is transmitted on the IEEE1394 bus, t _cyci is the time when one transport packet is reconstructed on the receiving side and transferred to the MPEG demultiplexer, t _ji is the transmission jitter of the 1394 bus.

The PCR correction / difference calculator 14 performs PCR correction according to the amount of jitter according to the following equation. Corrected PCR _i value
PCR _cori , PCR _i value and PCR correction / difference calculator 14
Time converted values of the PCR _cori values corrected in
_PCRi, and t _PCR _ _cori, make the following correction. _{t PCR _ cori = t PCRi +} t ji ........................... (1) where t _ji is _{t jt} = t cyci -t _i ........................... than 2 (2) Become. Since T _stmpi is a value obtained by adding the maximum delay time δ to the transmission time t _i , T _stmpi = t _i + δ... (3) Therefore, from equations (2) and (3), t _jt = t _cyci − (T _stmpi −δ) _......

The PCR correction / difference calculating device 14 obtains the respective change amounts ΔPCR and ΔLM of the PCR value and the local counter value which are temporally adjacent to each other, and the VCXO control device 9 controls the control voltage according to the error amount. Generate a value. In this calculation, corrected PCR values are used instead of PCR. So time conversion value of ΔPCR _cori, the _{t PCR _ cori (1),} (4)
When calculated by _{using, Δt PCR _ cori = t PCR} _ cori -t PCR _ cori-1 = {t PCRi + t cyci - (T stmpi -δ)} - {t PCRi-1 + t cyci-1 - (T stmpi _{-1 -δ)} = (t PCRi} -t PCRi-1) + (t cyci -t cyci-1) - (T stmpi -T stmpi-1) = Δt PCRi + Δt cyc -ΔT stmp ............ (5 ).

Therefore, the PCR correction / difference calculating device 14 obtains the time conversion value ΔtPCR of ΔPCR from the PCR value from the MPEG2 TS demultiplexer 7 as shown in Expression (5), and obtains the Δt _cyc from the cycle timer / time stamp holding device 13. , Δ
T _stmp is calculated and substituted into equation (5) to determine Δt _{PCR — cori} .

Further, the difference between the local counter value and the corrected PCR value is determined by the PCR correction / difference calculation
VCXO control voltage V according to equation (6) in controller 9
Generate _ctrl . V _ctrl = G (Δt _{PCR — cor} −Δt _{LMC i} ) (6) Here, G is a gain, and Δt _LMC is a time conversion value of a local counter value. With the control voltage generated according to the equation (6), the 27 MHz VCXO 10 can accurately reproduce the system clock.

With such a configuration, MPEG2 TS
There is no need to monitor the timing at which the MPEG2 transport stream is transferred to the demultiplexer 7, and there is no need for means for successively comparing the value of the SPH and the value of the cycle timer, which was required in the prior art. Therefore, in the case of using software, the process of constantly comparing the SPH with the cycle timer value becomes unnecessary, and a high-speed CPU becomes unnecessary. On the other hand, even in the case of a hardware configuration, an extra comparison operation circuit becomes unnecessary, and an extra buffer becomes unnecessary.

Embodiment 2 In FIG. 3, the PCR correction of FIG.
LMC correction / difference calculator 1 instead of difference calculator 14
5 is a receiving apparatus. In the source packet header removing / time stamp extracting device 12 shown in FIG. 3, the MPEG2 transport stream is transferred to the MPEG2 TS demultiplexer 7 immediately without buffering until the time represented by SPH as in the prior art. For this reason, the MPEG2 transport stream input to the MPEG2 TS demultiplexer 7 does not remove jitter due to transmission through the 1394 bus. For this reason, the PCR extracted by the MPEG2 TS demultiplexer 7 also contains jitter, and if this is used as it is as a reference for clock recovery, erroneous clock recovery will occur.

Therefore, means for compensating for this jitter is required. The MPEG2 TS demultiplexer 7 receives the MPEG2 transport stream without performing time management and buffering processing for jitter absorption at the preceding stage. Therefore, the extracted PCR value is extracted earlier than the time when it should arrive. In the conventional technology, the VC shown in FIG.
Local counter value and extracted PC in XO controller 9
The value of R is compared, and the frequency generated by the 27 MHz VCXO 10 is controlled according to the difference value.

If the same processing as in the prior art is performed by the VCXO controller 9 using the PCR extracted earlier as it is, the PCR value becomes
Since it is extracted earlier than it should be detected, it should be larger than the local counter value.Therefore, it is determined that the 27 MHz clock frequency for incrementing the local counter is slow, and the 27 MHz VCXO
Control for raising the output frequency of No. 10 will be performed.

However, in practice, the system clock frequency of 27 MHz is not low, but the reason is that the MPEG2 transport stream is input to the MPEG2 TS demultiplexer 7 earlier than the original arrival timing without buffering. In order to compensate for this problem, the LMC correction / difference calculator 15 shown in FIG. 3 calculates how quickly the data has been extracted, and corrects the local counter value by subtracting the local counter value by the calculated value. Can respond.

In this process, the LMC correction / difference calculating device 15 performs local counter correction as follows. The following correction is performed by _setting the time converted value of the corrected time measurement counter value to t _LMCcori and the time converted value of the time stamp value to t _stmpi . t _LMCcori = t _LMCi -t _ji (7) (7) Substituting (4) into equation _{t LMCcori} = t _LMCi -t cyci - a _{(T stmp -δ) ............... (8} ).

The LMC correction / difference calculating device 15 shown in FIG. 3 obtains the error between the amounts of change ΔPCR and ΔLMC of the PCR value and the local counter value which are temporally adjacent to each other, and the VCXO control device 9 calculates the error amount. A corresponding control voltage is generated. In this calculation, the corrected LMC value is used instead of the LMC. Therefore, _when the time conversion value of Δt _LMCcori , Δt _{LMC — cori} , is calculated using equation (8), Δt _{LMC — cori} = t _{LMC — cori} −t _{LMC — cori−1} = ｛t _LMCi −t _cyci + (T _stmpi −δ)｝ − {t _LMCi-1 −t _cyci-1 + (T _stmpi-1 −δ)} = (t _LMCi −t _LMCi−1 ) − (t _cyci −t _cyci-1 ) + (T _stmpi − T _stmpi-1 ) = Δt _{LMCi −Δt cyc} −ΔT _stmp (9)

Therefore, the time conversion value Δt _LMC of ΔLMC is calculated from the local counter value, Δt _cyc and ΔT _stmp are calculated from the cycle timer / time stamp holding device 13 in FIG. 3 and substituted into the above equation to obtain Δt _{LMC — cori} . .

Further, the difference between the local counter value and the corrected PCR value is obtained by the LMC correction / difference calculating device 15, and the VCXO control voltage V is obtained by the VCXO control device 9 according to the equation (10).
Generate _ctrl . V _ctrl = G (Δt _{PCR −Δt LMC — cori} ) (10) where G is a gain and Δt _LMC is a time conversion value of a local counter value. The 27 MHz VCXO 10 can accurately reproduce the system clock by the control voltage generated according to the equation (10).

With such a structure, MPEG2 TS
There is no need to monitor the timing at which the MPEG2 transport stream is transferred to the demultiplexer 7, and there is no need for means for successively comparing the value of the SPH and the value of the cycle timer required in the prior art. Therefore, in the case of using software, the process of constantly comparing the SPH with the cycle timer value becomes unnecessary, and a high-speed CPU becomes unnecessary. On the other hand, even in the case of a hardware configuration, an extra comparison operation circuit becomes unnecessary, and an extra buffer becomes unnecessary.

[0037]

Since the present invention is configured as described above, it is not necessary to monitor the timing at which the MPEG2 transport stream is transferred to the MPEG2 TS demultiplexer. There is no need for a means for successively comparing the values of the cycle timer. For this reason, if software is used, there is no need to constantly compare the SPH with the cycle timer value.
U becomes unnecessary. On the other hand, even in the case of a hardware configuration, an extra comparison operation circuit becomes unnecessary, and an extra buffer becomes unnecessary. Thus, clock reproduction can be accurately realized with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a method of transmitting and receiving an MPEG2 transport packet according to the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a conventional signal receiving device.

FIG. 5 is a configuration diagram of an IEEE1394 packet having a payload of an MPEG-2 transport stream input to a packet signal receiving device.

FIG. 6 is a format diagram of an MPEG2 transport packet.

[Explanation of symbols]

1 IEEE1394 bus, 2 IEEE1394 interface, 3
FIFO memory, 4 time stamp extraction device, 5 cycle timer, 6 output timing control device, 7 MPEG2 TS
Demultiplexer, 8 local counters, 9 VCXO
Control device, 10 27 MHz VCXO, 11 MPEG2 A / V decoder, 12 source packet header removal / time stamp extraction device, 13 cycle timer, time stamp holding device, 14 PCR correction / difference calculation device, 15 LMC correction /
Difference calculator.

Claims (3)

[Claims] 1. A clock recovery apparatus for receiving a packet signal transmitted through a transmission path having jitter, comprising: means for extracting a payload of the packet; and transmission path absolute time information of the transmission path from the packet. , An absolute time clock means for periodically adjusting the time based on the transmission path absolute time information, and a data transfer reference included in the payload necessary for accurately reproducing the data included in the payload. Means for extracting time information; means for extracting clock reproduction reference time information necessary for reproducing a clock for accurately reproducing data included in the payload; and extracting the payload from the clock reproduction reference time information. Transfer time detecting means for detecting an absolute time transferred to the means, the transfer time information, the data transfer reference time Control signal generating means for reproducing a clock necessary for accurately reproducing the data from the information and the clock reproduction reference time information, and local time counting means counting up with the reproduced clock. A clock recovery device characterized by the above-mentioned. 2. A control signal generating means for generating a control signal by correcting clock reproduction reference time information from transfer time information from a transfer time detection means and data transfer reference time information. 2. The clock recovery device according to 1. 3. A control signal generating means for generating a control signal by correcting a counter value from a local time clock means based on transfer time information from a transfer time detecting means and data transfer reference time information. The clock recovery device according to claim 1.