JP2003198619A - Data transmitter and method therefor, and data receiver and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain disturbance of a decoded signal which is caused by shift of a packet interval, when a packet form of data which is produced as a packet stream is converted and the data are transmitted via a network. <P>SOLUTION: A transport stream composed of TS packets is outputted from an MPEG2 encoder LSI22. The TS packet is accommodated in Ethernet (registered trade mark) packet whose size is larger than the TS packet, and sent out to a network. An interval of the TS packet and an interval of time reference information (PCR) which are included in a packet stream of the Ethernet packet are made nearly equal to an interval of the TS packet and an interval of PCR which are included in the transport stream, respectively. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a LAN (Local Area Network) such as Ethernet or Fast Ethernet.
The present invention relates to a data transmitting apparatus and method for transmitting image data and audio data to k), and a data receiving apparatus and method for receiving and decoding data transmitted on a network.

[0002]

2. Description of the Related Art In a network image data transmission system, as shown in FIG. 9, an image data transmitting device (hereinafter referred to as "server") 101 and an image data receiving device (hereinafter referred to as "client") 102 are connected to an Ethernet 100.
It is configured to be connected via. In the server 101, the input video signal is converted into MPEG (Motion Picture Expert).
Group) 2 performs an encoding process, converts this data into an Ethernet packet, and sends it to the Ethernet 100. The client 102 decodes the received data, displays the reproduced image on the monitor 103, and outputs the reproduced sound, in the reverse procedure of the server 101.

FIG. 10 shows a circuit configuration of the server 101 shown in FIG. The server 101 is an MPEG encoder circuit 1 that compresses an input video signal with MPEG2.
11, compressed data (transport stream,
An Ethernet circuit 112 that sends out TS to the Ethernet 100, and a CPU (CentralPro) that controls the entire device
cessing unit) 113, a DRAM (Dynamic Random Acc) that stores data to be processed by the CPU 113.
ess Memory) 114 and the like.

Of these, the MPEG encoder circuit 111
Mainly includes an A / D converter (including a sync signal separation circuit and a sync circuit) 121 and an MPEG2 encoder LSI 122.
And a FIFO (First In First Out) memory 123,
And a bus control circuit 124.

Now, a process until the input video signal is transmitted to the Ethernet 100 will be briefly described.
In FIG. 10, an input video signal is converted into digital data by an A / D converter 121, and then MPEG.
The two-encoder LSI 122 compresses and outputs in a transport stream format. This data is temporarily held in the FIFO memory 123, read out from the FIFO memory 123 by software control of the CPU 113, passes through the bus control circuit 124, and is written in the DRAM 114 via the CPU data bus 115. The data read from the DRAM 114 is UDP
(User Datagram Protocol) and IP (Internet Protoco
l) Header information is added to the Ethernet circuit 112
And is sent to the Ethernet 100 for each Ethernet packet IPCT.

Next, the MPEG2 encoder LSI 122
The operation of writing the transport stream output from the memory to the FIFO memory 123 and reading the written data will be described.

FIG. 13 shows the timing of each signal in the server 101. The transport stream (TSDATA shown in FIG. 13B) output from the MPEG2 encoder LSI 122 may be continuously output or may be intermittently output in bursts (intermittently). FIG. 13 shows a case where the transport stream is output in bursts with breaks. Most of the MPEG2 encoder LSIs provided by each LSI maker output a VALID signal (FIG. 7A) and a SYNC signal (FIG. 2B) in synchronization with the data when outputting the data. . The VALID signal is
This signal is active during the period when the data is valid, and the high level is output during the period when the data A, B, and C in the figure are output. The SYNC signal is a signal having a high level at the first byte of a TS (transport stream) packet composed of 188 bytes. A shown in FIG. 13 (b)
Symbols B, C indicate that a plurality of TS packets are output.

The bus control circuit 124 shown in FIG.
VA output from the MPEG2 encoder LSI 122
FIFO memory 1 according to the LID signal or the SYNC signal
23, write control is performed, data is read from the FIFO memory 123 by an instruction from the CPU 113, and the CPU 1
Adjust the timing so that 13 can be received.

The write enable signal (hereinafter referred to as "WE signal") and the read enable signal (hereinafter referred to as "RE signal") output from the bus control circuit 124 are
The signals are connected to the WE terminal and the RE terminal of the FIFO memory 123, respectively.
23 write / read operations are performed.

As shown in FIG. 13, when the VALID signal becomes high level, the bus control circuit 124 causes the WE
The signal is activated (high level in the figure) to write data in the FIFO memory 123. At this time, the write counter of the bus control circuit 124 counts the number of bytes of written data (see the counting operation period TCO in FIG. 13D). When the VALID signal becomes low level, the bus control circuit 124 sets the WE signal to low level to stop the write operation, suspend the count operation, and hold the current count value (the count holding period in FIG. 7D). TCH).

When 1460 bytes (the meaning of the value will be described later) are written in the FIFO memory 123, the write counter of the bus control circuit 124 becomes 1460 bytes, and the MPEG interrupt signal MIRQ is output ((f) in the figure, time). t1, t2). The MPEG interrupt signal MIRQ is input to the hardware interrupt terminal of the CPU 113 and requests the CPU 113 for interrupt processing. When an interrupt occurs, an interrupt processing routine that operates on the CPU 113 is executed, and the bus control circuit 124 is instructed to read the FIFO memory 123. The bus control circuit 124 which has received the instruction from the CPU 113 sets the RE signal to the high level and reads the data from the FIFO memory 123. After that, software processing by the CPU 113 is performed.

Next, a method of generating and transmitting an Ethernet packet will be described. In the conventional server, 1500 bytes worth of data is transmitted as one Ethernet packet so as not to exceed the maximum length of the Ethernet packet (1518 bytes). Therefore, considering the addition of a header such as UDP / IP, the data area is set to 1
It is set to 460 bytes.

Software such as an interrupt processing routine operating on the CPU 113 allows the FIFO memory 12 to operate.
The data read from No. 3 is once written in the DRAM 114. As shown in FIG. 11, an 8-byte UDP header and a 20-byte IP header are added to this data and sent to the Ethernet circuit 112. In the Ethernet circuit 112, a 14-byte Ethernet header is further added to this data, and 1500 bytes equivalent (15
One packet of 02 bytes) is completed. This is shown in FIG.
It is transmitted to the Ethernet 100 at the timing shown in (h). The first packet is composed of A and B of the transport stream TSDATA, and the second packet is B.
It consists of the rest of C and C. As described above, the conventional server stores the transport stream TSDATA output from the MPEG2 encoder LSI 122 in an Ethernet packet in units of 1460 bytes and sends it out.

On the other hand, the client 102 is composed of the Ethernet circuit 132 and the MPEG decoder circuit 131, as described above. Of these, the MPEG decoder circuit 131 is mainly composed of an MPEG2 decoder LSI and a memory (not shown). Here, MPEG2
A description will be given focusing on the clock synchronization system of the decoder LSI.

According to the MPEG2 standard, ATM (Asynchronous)
Nous Transfer Mode) is assumed to be used for network transmission, and even on a transmission path where clocks and control signals cannot be directly transmitted, the MPEG2 decoder on the receiving side (hereinafter referred to as “decoder”) is the MPEG2 encoder on the transmitting side (hereinafter “encoder” ")) To synchronize. That is, a time stamp is added to the stream for transmission, and when the stream structure is a transport stream, a program clock reference reference value (Program Clock Reference, hereinafter “PC
R ”). The TS packet has an area called an adaptation field in addition to the payload, and PCR is added to the optional field in this area. This is time information calculated by the encoder from the system clock at the time of encoding, and the transmission interval is 100
It is defined by the standard as msec or less.

The decoder circuit 131 extracts this PCR from the received stream and outputs P as shown in FIG.
The system clock of the decoder itself can be synchronized with the system clock of the encoder by the LL (Phase Locked Loop) circuit. The operation of the PLL circuit is as follows.

FIG. 12 shows the configuration of a PLL circuit incorporated in the MPEG2 decoder LSI. S in the figure
TC (System Time Clock) is 27M of the decoder itself
It is calculated by counting the system clock of Hz with the STC counter 144. The STC counter 144 has the same configuration as the reference counter on the encoder side, and the value of the PCR extracted first from the received stream is loaded to determine the initial value of the counter 144. After that, the counting operation is continued in the closed loop of the PLL circuit. At the time when the PCR arrives at the decoder, the comparator 141 in the closed loop compares the PCR with the current value of STC. A voltage corresponding to the comparison result (error amount) is passed through the low-pass filter 142 to generate 27 MHz VCXO.
The voltage control crystal oscillator 143 is supplied to adjust the frequency 27 MHz of the clock signal CL27M.

As described above, the decoder circuit 131 can match the system clock frequency of the encoder by finely adjusting the clock based on the PCR added by the encoder.

[0019]

As described above, in the server 101, transmission is performed for each Ethernet packet corresponding to 1500 bytes. FIG. 13 (h) shows the timing at this time. However, the delay time TD naturally exists before the data transmitted from the encoder (server side) 111 reaches the decoder (client side) 131. If this delay time T
If D is constant, the client 102
Data will be received at the timing of (i) in FIG. On the client 102,
1 from the Ethernet packet received at this timing
Take out 88-byte TS packet and decoder 131
Will be passed to. Here, focusing on the arrival time of TS packets (time interval of TS packets), FIG.
The reception timing shown in is the encoder L of the server 101.
The timing is different from the timing output from SI 122 ((b) in the figure). If the time interval of the TS packet changes, the arrival time interval of the PCR added in the TS packet also changes.

In the PLL circuit mounted on the decoder LSI, the PCR and the STC are compared at the time when the PCR arrives. Therefore, if the packet time interval is deviated, the error of the comparison result increases. As a result, the PLL circuit is adjusted to the wrong frequency, and the decoder 13
The system clock of 1 is not synchronized with the system clock of the encoder 111. If this state continues for a while,
The buffer provided in the client 102 causes overflow or underflow, which causes a problem that the decoded image is disturbed.

As already mentioned, there is a delay time in the data transmission between the server and the client, and the actual PC
The arrival time of R also includes this delay time.
PL built into the decoder LSI of the client 102
Since the L circuit compares the PCR with the STC at the time when the PCR arrives at the decoder 131, it is required that the delay time between the server and the client is constant.

However, in a bus type transmission line such as Ethernet, this delay time is not always constant and has some jitter. In such a transmission line, P
If the arrival time of CR, that is, the arrival time of TS packet fluctuates due to jitter, an error between PCR and STC in the comparator 141 of the PLL circuit will occur. as a result,
The PLL circuit is adjusted to the wrong frequency, and the system clock of the decoder 131 does not synchronize with the system clock of the encoder 111. If this state continues for a while, the buffer provided in the client 102 overflows or underflows, and the decoded image stops or skips.

The present invention has been made in consideration of the above points, and when the packet format of data generated as a packet stream is converted and the data is transmitted via the network, the packet stream is not generated when the packet stream is generated. A first object of the present invention is to provide a data transmission device that suppresses the time gap of packet intervals at the transmission timing.

Further, the present invention provides a data receiving device capable of absorbing the jitter of the transmission line even in the case where there is a packet interval deviation in the packet stream type data received via the network.
The purpose of.

[0025]

In order to achieve the first object, the invention according to claim 1 performs an information compression process on input data, stores the data in a first packet, and at a predetermined time. The information compression means for storing the time reference information at the time interval of and outputting it as the first packet stream, and the first packet stream output from the information compression means are the first packet having a packet size larger than that of the first packet. In the data transmitting apparatus, the data transmitting means stores the packet in the second packet, and secondly transmits the packet stream to the network.
The first packet is stored in the second packet while maintaining the interval between the first packets included in the first packet stream, and is sent to the network as the second packet stream. To do.

In order to achieve the above-mentioned second object, the invention described in claim 2 is a packet stream composed of packets storing information-compressed data to be transmitted through a network, the packet stream having a predetermined time interval. In the data receiving device for receiving the packet stream in which the time reference information is inserted and decoding the received packet stream, a storage unit for storing the received packet stream, and time reference information included in the packet stream Based on the time lag detection means for detecting the time lag of the intervals of the packets included in the packet stream, and the time lag detected by the time lag detection means,
And a packet interval adjusting unit that adjusts the packet interval by changing a read clock of the storage unit, and the packet stream whose packet interval is adjusted by the packet interval adjusting unit is decoded.

In order to achieve the first object, the invention according to claim 3 performs the information compression processing on the input data, stores the data in the first packet, and sets the time reference at a predetermined time interval. First by storing information
Information compression step for generating a packet stream of
The data transmission method comprising the step of storing the generated first packet stream in a second packet having a packet size larger than the first packet and secondly transmitting the packet as a packet stream to a network. In the sending step, the first packet is stored in the second packet while maintaining the interval between the first packets included in the first packet stream, and sent to the network as the second packet stream. It is characterized by

In order to achieve the above-mentioned second object, the invention according to claim 4 is a packet stream composed of packets storing information-compressed data transmitted via a network, the packet stream having a predetermined time interval. In the data receiving method of receiving the packet stream in which the time reference information is inserted, and decoding the received packet stream, the received packet stream is stored in the storage means, and the time reference information included in the packet stream is stored. Based on the detected time lag of the packet intervals included in the packet stream, the packet interval is adjusted by changing the read clock of the storage means according to the detected time lag, and the packet interval is adjusted. Is performed to decode the adjusted packet stream.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing the configuration of a data transmitting apparatus according to an embodiment of the present invention. The configuration shown in FIG. 1 is similar to that of the conventional data transmission device shown in FIG. That is, the server 1 shown in FIG. 1 includes an MPEG encoder circuit 11 that compresses an input video signal with MPEG2, an Ethernet circuit 12 that sends compressed data (transport stream) to the Ethernet 100, and a CPU (Central (Central)) that controls the entire apparatus. Processing
Unit) 13, D for temporarily storing data to be processed
It is configured by a RAM (Dynamic Random Access Memory) 14 and the like.

Of these, the MPEG encoder circuit 11 is
Mainly an A / D converter (including a sync signal separation circuit and a sync circuit) 21, an MPEG2 encoder LSI 12, an FI
It is composed of an FO (First In First Out) memory 23 and a bus control circuit 24.

In the conventional server 101 shown in FIG.
Transmission was performed for each Ethernet packet corresponding to 500 bytes. Therefore, the transport stream (TS) output from the encoder LSI 122 is 1460.
The processing is performed for each byte, and as a result, the time interval of the TS packet is destroyed, causing the PLL circuit of the client to malfunction. Therefore, in this embodiment, the TS
Data is handled in units of packets (188 bytes), and V
An Ethernet packet is generated every time the ALID signal becomes high level.

In the server 1 shown in FIG. 1, the operation of the bus control circuit 24 is different from that of the path control circuit 124 shown in FIG. Therefore, while explaining the hardware operation centering on the bus control circuit 24,
A method of generating and transmitting an Ethernet packet will be described.

FIG. 2 is a timing chart showing the data timing of the server 1. TSDAT shown in FIG.
A shows a state in which the transport stream is output from the MPEG2 encoder LSI 22 in bursts rather than continuously. The VALID signal in FIG. 10A is a signal that becomes active (high level in the figure) while the data is valid, and the SYNC signal in FIG.
It is a signal that becomes a high level at the first byte of a TS packet composed of 188 bytes. Packet groups A, B, and C of TSDATA represent a state in which a plurality of TS packets are output.

When the VALID signal goes high, MP
The TS packet group A is output from the EG2 encoder LSI 22 at the timing shown in FIG. In the bus control circuit 24, while the VALID signal is at the high level, the write enable signal (hereinafter referred to as “WE signal”) is activated (at the high level in the drawing) and the data is written in the FIFO memory 23. At this time, in the bus control circuit 24, the write counter counts the number of bytes of the written data, and this operation is shown in FIG.
Is shown in the counting operation period TCO.

The bus control circuit 24 sets the interrupt request signal MIRQ to a high level when the value of the write counter reaches a preset value (for example, 188 bytes). The interrupt request signal MIRQ is connected to the hardware interrupt terminal of the CPU 13,
Request interrupt processing. When an interrupt occurs, an interrupt processing routine (see FIG. 3A) that operates on the CPU 13 is executed, and the bus control circuit 24 activates a read enable signal (hereinafter referred to as “RE signal”) (high level) by an instruction from the CPU 13. ) To read data from the FIFO memory 23. At this time, V
By using a signal obtained by delaying the ALID signal by 188 bytes as the RE signal, the FIFO memory 23 is read while maintaining the time interval of the TS packet.

On the other hand, when the VALID signal becomes low level, the WE signal is made low level to stop the write operation,
The write counter is reset to prepare for the next VALID signal (reset period TCR in FIG. 2D). The packet group A read from the FIFO memory 23 is, as shown in FIG. 11, an 8-byte UDP header and a 20-byte IP header.
A header is added and sent to the Ethernet circuit 12.
The Ethernet circuit 12 adds a 14-byte Ethernet header to this data and transmits it as an Ethernet packet on the network 100. Even if the packet group A is less than 1460 bytes, an Ethernet packet is generated from the data and transmitted. When the packet group A is 1460 bytes or more, a plurality of Ethernet packets are generated and transmitted.

Next, when the VALID signal becomes high level,
The TS packet group B is output from the encoder LSI 22, and the Ethernet packet is generated and transmitted by the packet group B by the same procedure. Although the transmission time may be shifted in the Ethernet circuit 12 when transmitting a packet by the above operation, the transmission timing shown in FIG. 2 (h) is different from the timing output from the encoder LSI 22 (FIG. 2 (b)). Are almost equal. Therefore, the time intervals of TS packets are not greatly shifted during transmission.

Further, when there is no jitter in the delay time between the server and the client, the timing of receiving the packet is the timing shown in (i) of FIG. Since the client can extract the TS packet every 188 bytes from this reception timing, the TS packet can be passed to the decoder LSI while maintaining the PCR arrival time interval. As a result, a malfunction of the PLL circuit built in the decoder LSI can be prevented, and a phenomenon in which the decoder system clock is not synchronized with the encoder system clock can be avoided. Therefore, the disorder of the decoded image can be minimized.

Next, the operation of the software in the CPU 13 will be described. The software operating on the CPU 13 mainly performs the read operation of the FIFO memory 23 and the generation of Ethernet packets. Here, the actual operation of the software will be described with reference to the flowchart shown in FIG.

The VALID signal goes high and the FIF
When 188 bytes of data are written in the O memory 23, the interrupt signal MIRQ becomes high level, and the interrupt processing routine (MPEG interrupt routine of FIG. 3A) is executed. In step S11, it is checked whether the RE signal is at high level, and if it is at high level, a read operation is executed (step S12). If it is at the low level, the read operation has been completed, and the process proceeds to step S13.

In step S12, the bus control circuit 24 is instructed to read the FIFO memory 23. This command causes the bus control circuit 24 to perform FI.
Data is read from the FO memory 23, and the DRAM 14
It is written in the MPEG area secured above. After that, the process returns to step S11.

In step S13, all the data written during the period when the VALID signal is at the high level are read out, so that the MPEG transmission application (FIG. 9B) is performed.
To end the MPEG interrupt routine.
Next, the MPEG transmission application called by the MPEG interrupt routine ((b) in the figure) is started.

In step S21, the MP of the DRAM 14 is
Read 1460 bytes of data from the EG area. 14
If less than 60 bytes, read all. In step S22, this data has an 8-byte UDP header and 2
A 0-byte IP header is added.

In step S23, this data is written in the data area of the Ethernet circuit 12 and a transmission start procedure is performed. After that, the hardware processing is performed by the Ethernet circuit 12. Furthermore, a 14-byte Ethernet header is added to this data to generate a 1502-byte packet. This is sent to the Ethernet 100 as one Ethernet packet.

In step S24, the MP of the DRAM 14 is
It is checked whether or not there is data written in the EG area. If there is data remaining, the process returns to step S21, and the processes of steps S21 to S23 are executed until there is no data in the MPEG area to generate an Ethernet packet. Repeat the transmission.

If the answer to step S24 is negative (NO) and all Ethernet packets have been transmitted, MP
Terminate the EG transmission application. Thus, V
By generating and transmitting an Ethernet packet at the timing of a signal obtained by delaying the ALID signal for a fixed time,
It is possible to minimize the deviation of the time intervals of TS packets. As a result, the client can suppress the deviation of the PCR arrival time, and thus can prevent the malfunction of the PLL circuit built in the decoder.

FIG. 4 is a block diagram showing the circuit configuration of the data receiving apparatus according to the first embodiment of the present invention.
The data receiving device, that is, the client 2 has an Ethernet circuit 32 for receiving the transmitted packet, an MPEG decoder circuit 31 for decoding the data received from the Ethernet circuit 32, and a C for controlling the entire circuit.
PU 33 and DR for temporarily storing data to be processed
And AM34.

Of these, the MPEG decoder circuit 31 is
A bus control circuit 41, a FIFO memory 42,
MPEG2 decoder LSI 43 and jitter detection circuit 44
And a read clock control circuit 45. First, the Ethernet packet received by the Ethernet circuit 32 has the Ethernet, IP, and UDP protocol headers removed, and is stored in the DRAM 34. The bus control circuit 41 reads data from the DRAM 34 and writes it in the FIFO memory 42.
The data read from the FIFO memory 42 is the MPE
It is input to the G2 decoder LSI 43, decoded and output as a video signal.

Next, a method of detecting when jitter occurs on the transmission path (Ethernet 100) and a method of adjusting data to be passed to the decoder will be described.

FIGS. 5A and 5B show the timing relationship between the Ethernet packet at the time of transmission and the received Ethernet packet. Data A is received after the delay time TDa has elapsed, and the next data B is Since the jitter has occurred in the transmission path, the signal is received after the delay time TDb has elapsed. When this data B is enlarged and viewed in TS packet units, the arrival time of the PCR added in the packet is delayed as compared with the original TS packet, as shown in FIGS. There is. If such a state continues for a while, the system clock of the decoder will not be synchronized with the encoder side, as mentioned in the problem.

Therefore, in the present embodiment, the jitter detection circuit 4
4 and a read clock control circuit 45 are provided to adjust the timing of data passed to the decoder LSI 43.
First, in the jitter detection circuit 44, the received stream T
The first PCR (FIG. 6 (c)) is extracted from S1. The jitter detection circuit 44 includes a counter similar to the STC counter shown in FIG. 12, and counts the 27 MHz clock CL27M input from the decoder LSI 43 to ST.
Generate C. Next, the generated STC is compared with the first PCR extracted from the stream. The comparison result (difference between STC and PCR) is compared with a preset threshold value. An error value between STC and PCR that occurs in an environment where there is no jitter on the transmission path is set to this threshold value. That is, when the comparison result of STC and PCR largely deviates from the threshold value, it can be understood that jitter has occurred in the transmission path.

When the jitter detecting circuit 44 detects the jitter, it outputs the jitter detecting signal SJ to the read clock control circuit 45. The jitter detection signal SJ is normally low level, but becomes high level when the jitter is detected.
At the same time as this signal SJ, depending on the amount of PCR delay,
The delay status signal SD is output. Delay status signal SD
Is a signal that is at a low level when the extracted PCR is behind the STC, and is at a high level when the extracted PCR is ahead of the STC. In addition to this, the jitter detection circuit 44 includes a FIF.
The data read from the O memory 42 is input, and the PCR after the jitter correction is extracted from this data.

Next, the actual operation of the device shown in FIG. 4 will be described. The STC shown in FIG. 6B is a jitter detection circuit 44.
S calculated by counting 27 MHz clock in
It represents the value of TC. First PCR shown in FIG.
Indicates the value of the PCR extracted from the reception stream TS1, and the second PCR shown in FIG.
PCR extracted from stream TS2 read from No. 4
Is the value of. The STC and PCR values are shown here as simple integers, but the actual values are different.

When some packets are received, the effect of the PLL circuit built in the decoder LSI 43 appears, and the system clock frequencies of the encoder and the decoder gradually become equal. At this time, the first PCR extracted from the stream has a value close to STC. However, when jitter occurs in the transmission line, the arrival time of the first PCR is delayed, and the STC counter continues to count during that time, so that the extracted first PCR lags behind the STC value. This state is represented by the × period shown in FIG. 6 (c),
When the extracted first PCR is 10, the current value of STC is 80
Has become. At this time, the difference between STC and the first PCR is 70
Since the threshold value is exceeded (the set value is, for example, 50), it is detected that jitter is occurring.

When the jitter is detected in this way, the jitter detection signal SJ becomes high level and the delay status signal SD becomes low level. The read clock control circuit 45 which has obtained this information switches the read clock to a frequency higher than the standard frequency (for example, twice the frequency) and outputs the read clock, as shown in FIG. As a result, the data read from the FIFO memory 42 becomes twice as fast as usual, and the transfer rate of the data passed to the decoder LSI 43 also increases. Therefore, the second PC extracted from this data TS2
R also progresses to 11, 12, 13, 14, ... At twice the speed, and eventually catches up with the STC value and can absorb the jitter. When the values of the second PCR and STC match, the read clock is switched to the standard frequency to restore the normal transfer rate.

In this way, by changing the frequency of the read clock of the FIFO memory 42, the decoder LS
Large jitter can be removed from the data passed to I43. Further, although the read clock has been described as being twice as high as the standard frequency, the jitter can be absorbed in a shorter time by setting the frequency to be 4 times, 8 times, ....

By the above operation, it is possible to avoid the phenomenon that the PLL circuit built in the decoder malfunctions due to the jitter of the transmission path. As a result, the problem that the system clock of the decoder is not synchronized with the encoder side can be solved. Up to now, the case where the delay time of the transmission path becomes long has been described, but the delay time between the server and the client may suddenly become short due to the change of the path of the transmission path. In such a case, the extracted first PCR will advance the current value of STC. At this time, the jitter detection signal SJ and the delay status signal SD both become high level, and the read clock control circuit 45 sets the read clock of the FIFO memory 42 to a frequency lower than the standard (for example, 1/2 times, 1 times).
/ 4 times, etc.) to read the data from the FIFO memory 42 at a transfer rate lower than usual and input it to the decoder LSI 43. Thus, even if the delay time becomes short, the malfunction of the PLL circuit can be prevented by adjusting the transfer rate.

(Second Embodiment) In the present embodiment, the server 1 is adapted to the case where the transport stream is continuously output from the MPEG2 encoder LSI. The circuit configuration is the same as that of the first embodiment, but the operation of the bus control circuit 24 is different. Therefore, the hardware operation centering on the bus control circuit 24 will be described, and the method for generating and transmitting the Ethernet packet will be described.

First, the transmission unit of the Ethernet packet in this embodiment will be described. In order to prevent the PLL circuit on the client side from malfunctioning, it is necessary to maintain the time interval of TS packets from the transmission stage. Therefore, in this embodiment, one Ethernet packet is created from seven TS packet data (1316 bytes) each including 188 bytes.

FIG. 7 shows the data timing of the server and the client of this embodiment. TSDATA in FIG. 3A is an MPEG2 encoder LSI.
22 shows the state of TS packets that are continuously output from No. 22, and the data is divided into 1316-byte units and called A, B, C, D, E, ...

Next, F by the bus control circuit 24
The read operation of the IFO memory 23 will be described. VALI
The D signal (not shown) is an MPEG2 encoder LSI2.
Since data is always output from 2, the active state (high level) is always maintained. In addition, the SYN shown in FIG.
The C signal is a signal which becomes a high level at the head byte of the 188-byte TS packet, and is also output without interruption.

The bus control circuit 24 uses the VALID
While the signal is at the high level, the WE signal (not shown) is activated (at the high level) to write the data in the FIFO memory 23. Since the VALID signal is always high,
The WE signal also becomes high level, and writing is always performed.

At this time, in the bus control circuit 24,
The number of bytes of data written by the write counter is counted, and the write counter counts from 0 to 1315 and then returns to 0 as shown in FIG. When the count value reaches 1315, the bus control circuit 24 sets the interrupt request signal MIRQ ((d) in the figure) to a high level. This interrupt request signal MI
The RQ is connected to the hardware interrupt terminal of the CPU 14 and requests the CPU 14 for interrupt processing. When an interrupt occurs, the interrupt processing routine (FIG. 8A) that operates on the CPU 14 is executed, and the CPU
The command 14 causes the bus control circuit 24 to activate (high level) the RE signal (FIG. 7E),
Data of 1316 bytes is read from the IFO memory 23. The read clock of the FIFO memory 23 uses a clock having a high frequency (for example, twice the frequency of the write clock) with respect to the write clock, and reads at a high speed on the write side. This is the next 1
This is to allow the CPU 14 and the Ethernet circuit 12 enough time to add each protocol header such as UDP before reading 316 bytes.

The CPU 14 adds an 8-byte UDP header and a 20-byte IP header to the 1316-byte data read from the FIFO memory 23, and passes this to the Ethernet circuit 12. In the Ethernet circuit 12,
A 14-byte Ethernet header is added to this data and sent out on the network as an Ethernet packet.

By the above operation, as shown in FIG. 7F, an Ethernet packet can be transmitted for each TS packet group A, B, C ... Output from the encoder LSI 22. However, since the frequency of the read clock of the FIFO memory 23 is doubled, the data to be transmitted has an interval. Therefore, the arrival time of the packet (the arrival time of the decoder of the PCR) is as much as the data interval is left.
Will be shifted. Therefore, the shift is corrected by using the data receiving device (client) shown in FIG. 4 described in the first embodiment.

When a packet is transmitted by the Ethernet circuit 12, the transmission timing may be slightly deviated due to the state of the network or the presence / absence of a received packet.
In addition, the packet interval may become vacant for the reasons described above. FIG. 7 (g) shows the timing of the Ethernet packets A, B, C, ... At the time of reception, and shows a state where the packet intervals are open. Further, in a transmission line such as Ethernet, jitter may occur in the delay time between the server and the client, the arrival time of the data B and D in FIG. 9 (g) is delayed, and the jitters indicated by Δa and Δb respectively. Has occurred.

Therefore, the data receiving apparatus (client) shown in FIG. 4 is used to correct the transmission timing deviation and the transmission line jitter. In the client shown in FIG. 4, the received data is temporarily stored in the FIFO memory 42 as described above.
Hold, and change the clock frequency on the read side,
The transfer rate of data input to the decoder LSI 43 is adjusted. FIG. 7 (h) shows such a situation, and the transfer rate is controlled as follows.

The arrival time of the data A is earlier because the data is concentrated in the first half, and the first PCR extracted from the received data is S in the comparator of the jitter detection circuit 44.
It is ahead of the current value of TC. In this case, the read clock of the FIFO memory 42 is switched to a low frequency, and the decoder LSI 4 is operated at a low transfer rate (white arrow a).
Pass the data to 3. Eventually, when the second PCR extracted from the read data matches the STC and the deviation of the arrival time is corrected, the clock is returned to the original standard frequency clock.

In the next data B, the arrival time of the packet is delayed due to the occurrence of jitter, so that the first PCR is delayed from the current value of STC. In this case, the read clock is switched to a high frequency and input to the decoder LSI 43 at a high transfer rate (black arrow b1). Eventually second
Although the PCR and STC match, the data B is also concentrated in the first half of the data, so that the second PCR progresses from the middle. Therefore, the transfer rate is switched to a low transfer rate (white arrow b2) from the middle. Similarly, for the next data C and D, the transfer rate is controlled as shown by the arrow in FIG.

As described above, by using the client shown in FIG. 4, the shift in the transmission time of the Ethernet packet can be corrected before the data is input to the decoder LSI 43, together with the jitter on the transmission line and the data timing. . As a result, the P built in the decoder LSI 43 is
A malfunction of the LL circuit can be prevented, and a phenomenon that the system clock of the decoder is not synchronized with the encoder side can be avoided. Therefore, the disorder of the decoded image can be minimized.

Next, the software operation in this embodiment will be described with reference to the flow chart shown in FIG. When 1316 bytes of data are written in the FIFO memory 23, the interrupt request signal MIRQ becomes high level, and the interrupt processing routine (M in FIG. 8A).
PEG interrupt routine) is executed.

In step S31, the bus control circuit 24 is instructed to read the FIFO memory 23. According to this instruction, the bus control circuit 24 reads 1316 bytes (7 TS packets) of data from the FIFO memory 23 and writes the data in the secured MPEG area on the DRAM 14.

In step S2, the MPEG transmission application ((b) in the figure) is called to end the MPEG interrupt routine. The called MPEG transmission application is then started. In step S41,
Data of 1316 bytes is read from the MPEG area of the DRAM 14.

In step S42, an 8-byte UDP header and a 20-byte IP header are added to this data. In step S43, this data is written in the data area of the Ethernet circuit 12, and a transmission start procedure is performed.

After that, the hardware processing is performed by the Ethernet circuit 12. By this hardware processing, a 14-byte Ethernet header is further added to this data to form a 1358-byte packet. This is sent out on the Ethernet as one packet.

In the above-mentioned embodiment, the image data is described as an example, but the audio data is processed in the same manner.

[0077]

As described above in detail, according to the invention described in claim 1 or 3, the input data is subjected to the information compression processing, the data is stored in the first packet, and the predetermined data is stored. Time reference information is stored at time intervals to generate a first packet stream. Then, the generated first packet stream is stored in a second packet having a larger packet size than the first packet, and secondly sent to the network as a packet stream. Further, the first packet is stored in the second packet while maintaining the interval between the first packets included in the first packet stream, and is sent to the network as the second packet stream. Therefore, it is possible to suppress the time lag of the packet interval at the second packet stream transmission timing, and to prevent the disturbance of the decoded signal due to the time lag of the packet interval from occurring on the receiving device side.

According to the invention described in claim 2 or 4,
The received packet stream is stored in the storage means, and the time difference between the intervals of the packets included in the packet stream is detected based on the time reference information included in the received packet stream. Then, by changing the read clock of the storage means according to the detected time lag, the packet interval is adjusted, and the packet stream with the adjusted packet interval is decoded. Therefore, even if there is a time lag in the packet interval in the received packet stream, it is possible to absorb the time lag and suppress the disturbance of the decoded signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the timing of data processing in the device shown in FIG.

FIG. 3 is a flowchart of a process (first embodiment) executed by the CPU shown in FIG.

FIG. 4 is a block diagram showing a configuration of a data receiving device according to an embodiment of the present invention.

FIG. 5 is a timing chart for explaining a timing shift of a program time reference value (PCR) due to jitter occurring on a network.

6 is a timing chart for explaining data processing in the device shown in FIG.

FIG. 7 is a timing chart for explaining the timing of data processing in the second embodiment of the present invention.

8 is a flowchart of a process (second embodiment) executed by the CPU shown in FIG.

FIG. 9 is a block diagram showing a configuration of a general network image data transmission system.

10 is a block diagram showing a configuration of the image data transmitting apparatus shown in FIG.

FIG. 11 is a diagram for explaining addition of a header according to a communication protocol.

FIG. 12 is a block diagram showing a configuration of a phase locked loop circuit that generates a system clock based on a program time reference value (PCR).

13 is a timing chart for explaining the timing of data processing in the device shown in FIG.

[Explanation of symbols]

1 Image Data Transmission Device (Server) 2 Image Data Reception Device (Client) 11 MPEG Encoder Circuit 12 Ethernet Circuit (Data Transmission Means) 13 CPU (Data Transmission Means) 14 DRAM (Data Transmission Means) 22 MPEG2 Encoder LSI (Information Compression Means) ) 23 FIFO memory (data transmission means) 24 bus control circuit (data transmission means) 31 MPEG decoder circuit 32 Ethernet circuit 33 CPU 34 DRAM 41 bus control circuit 42 FIFO memory (storage means) 43 MPEG2 decoder LSI 44 jitter detection circuit (time) Deviation detecting means) 45 Read clock control circuit (packet interval adjusting means)

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5C063 AB03 AB05 AC01 DA01 DA13                 5K028 AA03 CC06 EE03 KK01 KK32                       MM16 SS05 SS24                 5K030 GA12 HB02 HB15 JA05 KA19                       LA07 LC02 MB08                 5K033 AA05 BA15 CB08 CB15 DB10

Claims (4)

[Claims] 1. An information compression means for performing an information compression process on input data, storing the data in a first packet, storing time reference information at a predetermined time interval, and outputting it as a first packet stream. And a data sending means for storing the first packet stream output from the information compressing means in a second packet having a packet size larger than the first packet, and secondly sending it to the network as a packet stream. In the data transmission device, the data transmission means stores the first packet in the second packet while maintaining the interval between the first packets included in the first packet stream, A data transmission device for transmitting the packet stream to a network as a packet stream. 2. A packet stream comprising packets storing information-compressed data transmitted via a network, the packet stream having time reference information inserted at predetermined time intervals, and receiving the packet stream. In the data receiving device for decoding the packet stream, the storage unit for storing the received packet stream, and the time difference between the intervals of the packets included in the packet stream based on the time reference information included in the packet stream. And a packet interval adjusting unit that adjusts the packet interval by changing the read clock of the storage unit according to the time difference detected by the time difference detecting unit. Packet stream whose packet interval is adjusted by the adjusting means A data receiving device, characterized in that it performs decoding of a system. 3. An information compression process is applied to input data, the data is stored in a first packet, and the time reference information is stored at a predetermined time interval.
Information compression step for generating a packet stream of
A data transmission method comprising the step of storing the generated first packet stream in a second packet having a packet size larger than that of the first packet and secondly transmitting the packet as a packet stream to a network. In the sending step, the first packet is stored in the second packet while maintaining the interval between the first packets included in the first packet stream,
A data transmitting method, wherein the data is transmitted to the network as the second packet stream. 4. A packet stream comprising packets storing information-compressed data transmitted via a network, the packet stream having time reference information inserted at predetermined time intervals, and receiving the packet stream. In the data receiving method of decoding the packet stream, the received packet stream is stored in a storage unit, and a time difference between intervals of packets included in the packet stream is calculated based on time reference information included in the packet stream. The packet interval is detected, and the packet interval is adjusted by changing the read clock of the storage unit according to the detected time lag, and the packet stream with the adjusted packet interval is decoded. Data reception method.