JP3086675B2 - Method and apparatus for automatically adjusting sampling clock phase - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a closed caption signal superimposed on a television signal, XDS (Extended).
The present invention relates to a method and apparatus for automatically adjusting the phase of a sampling clock when sampling digital data signals such as data service, PDC, and VPS.

[0002]

2. Description of the Related Art In order to correctly obtain a digital data signal input from the outside to a device, it is necessary to set the phase of a sampling clock corresponding to the target digital data. However, in the past, there was no function to change the state of the sampling clock once it was set, so that when a digital data signal with a different phase was received, data could not be acquired normally. Was. In particular, a digital data signal superimposed on a television signal which is becoming popular in recent years may use different types of signals depending on individual channels, in other words, broadcasting stations, and use the same type of signal. The phase is slightly different.

[0003]

As described above, when a conventional television broadcast is received, the phase of the digital data signal superimposed on the television signal is not always constant depending on the broadcasting station or even in each region. For this reason, there is a problem that there is a possibility that normal reception is not possible.

The present invention has been made in view of the above circumstances, and is intended for a case where the phase of a digital data signal superimposed on a television signal is slightly shifted depending on a broadcasting station or between regions. Another object of the present invention is to provide a method and an apparatus for automatically adjusting the phase of a sampling clock that can be received normally.

[0005]

Automatic phase adjusting method of the sampling clock according to the SUMMARY OF THE INVENTION The present invention, in the automatic phase adjusting method of a sampling clock of the digital data to be transmitted is superimposed on the television signal, said digital data
A first step of setting the sampling phase of the
A second step of capturing the constant number of times where a signal containing digital data at a set phase by stage, a third step of counting the number of occurrences of an error of the captured signals, the number of occurrences of counted errors "0 If "Ru der
In a fourth step of determining the sampling clock phase of the digital data the phase that is set, Cow
If the number of occurrences of cement the error is not "0", set
The phase which is changed and returns to the second step.
Step and the second, third and fifth steps are repeated a predetermined number of times.
The minimum value of the number of occurrences of the error counted during recovery
And a second, third and fifth steps for storing
Error occurs while the loop is repeated a predetermined number of times.
If the number of births does not become "0",
Set the phase when the small value is obtained to the sampling clock phase
And a seventh step of deciding .

In the automatic phase adjustment method of the sampling clock according to the present invention, a signal containing digital data is fetched a predetermined number of times at different phases within a horizontal synchronization period of a predetermined line, and the fetched signal is subjected to a parity check. is has been counted number of occurrences of a parity error for each same phase, the phase values <br/> Oh Ru phase value found first if found in the number of occurrences of a parity error "0"<br/> digital data If there is no phase in which the number of occurrences of the parity error is "0", the phase in which the occurrence of the parity error is the least is determined as the sampling clock of the digital data.

Further, according to the present invention, there is provided an automatic phase adjusting device for a sampling clock, wherein the phase setting means for sequentially setting different phases is provided in the automatic phase adjusting device for a sampling clock for digital data transmitted by being superimposed on a television signal. Signal input means for inputting a signal containing the digital data at each phase set by the phase setting means, and presence or absence of an error for each of the signals input by the signal input means at the same phase a predetermined number of times , An error counting means for counting the number of occurrences of errors detected by the checking means for each phase set by the phase setting means, and a count number by the error counting means being "0". If it is, the sampling click of the digital data the phase that is set Tsu determined as click of a phase, wherein when the count number by the error counter is not "0" is allowed to change the setting phase of the phase setting means, wherein the phase of occurrence number of errors is minimized value digital Sampling clock determining means for determining the phase of the data sampling clock.

In the automatic sampling clock phase adjusting apparatus according to the present invention, the phase setting means sequentially sets different phases within the horizontal synchronization period of a predetermined line, and sets each phase by the phase setting means. Signals including digital data are respectively input to the signal input means, and the signals input by the signal input means at the same phase a predetermined number of times are subjected to parity check by the parity check means to detect the presence or absence of a parity error. the number of occurrences of the detected parity errors are counted by a parity error counter in each set each phase by the phase setting means, the count by the parity error counter <br/> is "0" der Ru phase value If you find
The phase values found in the first is determined as a sampling clock of the digital data by sampling clock determination means, generation of a parity error if the count <br/> betting amount by a parity error counter was not "0" is most The less phase is determined as the sampling clock of the digital data by the sampling clock determining means.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments. In the following embodiment, the data of the XDS (Extended Data Service) signal
The circuit configuration and software processing for processing (hereinafter referred to as XDS data) will be described.

FIG. 3A is a schematic diagram of the format of XDS data. The XDS signal is EIA (Electronic Industries As
sociation) -608, the data is superimposed on line 21 of the vertical synchronization signal of the even field of the video signal,
The data transmitted at one time is a 1-bit start bit SB
And 17 bits. Therefore, the body of XDS data is
16 bits (2 bytes), the first 7 bits of the first byte B1 and the second byte B2 are data bits DB1 and DB2 each representing one character, and the last bit of each byte is a parity of odd parity. Bits PB1 and PB2 are set. Then, as shown in the schematic diagram of FIG. 3A, the XDS data is a horizontal synchronization signal Hsync corresponding to the line 21.
Will exist within the period.

In the following embodiments, the XDS signal as described above is processed, but the method and the apparatus for automatically adjusting the sampling clock of the present invention are capable of performing a parity check by being superimposed on a television signal. signal,
For example, signals that can be parity-checked like XDS data, such as U.S. closed caption signals,
S (Video Programming System), PDC (program Delivery
Control services) It can be applied to signals that can be checked for data errors in packet units such as signals.

FIG. 1 is a block diagram showing an example of the configuration of a circuit used for implementing the automatic phase adjustment method of a sampling clock according to the present invention, which is incorporated in a television set, VTR, or the like.

The television signal is received by an antenna 110 and input to a tuner 11. The tuner 11 selects a television signal having a frequency corresponding to one channel specified by an operation panel or the like (not shown) and supplies the television signal to the sync separation circuit 12 and the slicer 18. The synchronization separation circuit 12 separates the horizontal synchronization signal Hsync and supplies it to the counter 13. counter
Reference numeral 13 is reset for each one cycle of the horizontal synchronization signal Hsync.

The counter 13 has a frequency of 14.31818 MHz from the oscillator 14.
Clock CK1 is supplied. The oscillation frequency of the oscillator 14 is set to four times the 3.58 MHz which is the chroma frequency of the NTSC system. Each time the horizontal synchronization signal Hsync is supplied from the synchronization separation circuit 12, the counter 13 has its own count value.
The CV is reset, and the clock CK1 of 14.31818 MHz that the oscillator 14 oscillates is counted up. The count value CV of the counter 13 is given to the comparator 15. Data to be compared with the count value CV given from the counter 13 is given to the comparator 15 from a register 17 functioning as a phase setting means.

In the register 17, a period T from the horizontal synchronization signal Hsync to the start of data sampling, in other words, a clock number TC of 14.31818 MHz corresponding to the phase is set. During this period T, specifically, the number of clocks TC is the CPU
It can be set arbitrarily by the control of 10. Therefore, the comparator
15 corresponds to the period T set in the register 17.
The number of clocks 1818MHz TC is compared with the count value CV of the counter 13, and when they match, a trigger signal is sent to the oscillator 16.
Give TS. The oscillator 16 receives a trigger signal from the comparator 15 described above.
When the TS is supplied, the oscillation of the clock CK2 of 503.524 kHz is started, and 16 clocks are supplied as the shift clock to the shift register 19 functioning as the signal input means.

As described above, the tuner 11 selects a television signal having a frequency corresponding to one specified channel and supplies it to the slicer 18, but the slicer 18 slices the supplied signal at a predetermined threshold. By X
The signal including the DS data is extracted and supplied to the shift register 19. The shift register 19 is a 16-bit shift register, and has a frequency of 503.524 k provided from the oscillator 16 described above.
Hz clock CK2 is 1 bit period of XDS data 1.986
μs (1.986 μs period is 503.524 kHz). Therefore, the shift register 19 receives the signal X from the slicer 18.
A signal including DS data is fetched one bit at a time in synchronization with a clock CK2 of 503.524 kHz for 16 clocks supplied from the oscillator 16, for a total of 16 bits of data. The 16-bit data taken into the shift register 19 is
Parity check is performed by the CPU 10 and the XDS data is synchronized.

The CPU 10 functions not only as a parity check unit, a parity error count unit, and a sampling clock determination unit, but also as a central control unit.

Next, as described above, the shift register 19
CPU10 for synchronizing XDS data based on parity check of 16-bit data taken into CPU10 from
Will be described with reference to the flowchart of FIG.

Factors for acquiring XDS data, for example, XD
When it becomes necessary to obtain time information from the S data, the CPU 10 executes processing for synchronizing XDS data according to the following processing procedure.

First, the CPU 10 initializes the number of errors E.
(Step S11). The initial value of the error count E is not good if larger than the predetermined number of times to count the number of parity errors, which will be described later. Next, the CPU 10 initializes the phase (step
S12). This is because the number of clocks TC set in the register 17 from the CPU 10 is set to the earliest timing at which the first bit of the data bit DB1 of the XDS data can exist during one cycle of the horizontal synchronization signal Hsync (P1 in FIG. 3B). This is for setting so as to correspond to the period up to the timing indicated by.

When the initial value of the phase is set as the number of clocks TC in the register 17 as described above, the data extracted by the slicer 18 and supplied to the shift register 19 is output during one period of the horizontal synchronization signal Hsync. From the earliest timing, 16-bit data is taken into the shift register 19 and latched. The 16-bit data latched by the shift register 19 is taken into the CPU 10 and a parity check is performed.

The CPU 10 repeats the above process a predetermined number of times, counts the number of parity errors EC in the currently set phase (step S13), and checks whether or not the result is "0" (step S13). S14). Here, if the number EC of parity errors is “0” (“in step S14,
YES "), the CPU 10 immediately determines the currently set phase as the optimum phase (step S19).
If the current number EC of parity errors is not “0” (“NO” in step S14), the CPU 10 determines whether the number EC of parity errors in the currently set phase is the minimum, that is, the number of errors E It is checked whether it is smaller than (Step S15).

The result of the determination in step S15 is "YES".
If so, the CPU 10 temporarily stores the number of parity errors and the currently set phase value, in other words, the phase value corresponding to the minimum number of parity errors (step S16). After completion of the process in step S16 and when the determination result in step S15 is "NO", the CPU 10 checks whether or not the phase has been changed in the entire range where the XDS data can exist. (Step S17).

If the decision result in the step S17 is "NO", the CPU 10 shifts the phase by a predetermined width, for example, the number of clocks TC shifted by one clock of the clock CK1 of 14.31818 MHz output from the oscillator 14. The setting phase value is changed to the next value (the timing indicated by P2 in FIG. 3B) by setting the value in the register 17 (step S18).

As described above, steps S13 to S18
The CPU 10 counts the number of parity errors in a state where individual phase values are set while sequentially shifting the phase values. By such processing, if a phase value in which the number of parity errors is “0” is found, the CPU 10 determines the phase value as an optimal phase value, and finds a phase value in which the number of parity errors is “0”. If not, find the phase value with the minimum number of parity errors and determine it as the optimal phase value
(Step S17).

In the above embodiment, the XDS signal is to be received. However, the method and the apparatus for automatically adjusting the phase of the sampling clock according to the present invention are superimposed on the television signal and can be subjected to a parity check, for example, a US closed signal. As with XDS data such as caption signals, VPS (Video Prog
ramming System), PDC (program Delivery Control serv)
ices) For signals such as signals that can be checked for data errors in packet units, the number of bits in the shift register 19, the frequency of the oscillation clock of the oscillator 16, and the CPU 10
It can of course be applied by appropriately setting the setting values with.

[0027]

As described in detail above, according to the method and apparatus for automatically adjusting the phase of a sampling clock according to the present invention, the phase of a closed caption signal such as an XDS, PDC, or VPS signal superimposed on a television signal is adjusted. Since data can be captured after being adjusted optimally, data can be appropriately acquired even when there is a phase shift. Further, when the apparatus of the present invention is incorporated in a television set or VTR, it becomes possible to optimally adjust and acquire the phase of a closed caption signal that slightly differs depending on the individual broadcasting station or region.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a configuration of a circuit used for implementing an automatic phase adjustment method of a sampling clock according to the present invention.

FIG. 2 is a flowchart showing a processing procedure by a CPU of the automatic sampling clock phase adjusting device according to the present invention.

FIG. 3 is a schematic diagram showing a format of XDS data and a start position of a sampling clock thereof.

[Explanation of symbols]

 10 CPU 13 Counter 14 Oscillator (14.31818MHz) 15 Comparator 16 Oscillator (503.524kHz) 17 Register 18 Slicer 19 Shift register

Claims (2)

(57) [Claims] 1. A method for automatically adjusting a sampling clock of digital data transmitted by being superimposed on a television signal, wherein a first sampling phase of the digital data is set.
Steps and, a second step of capturing a constant number of times where the signal containing the digital data in the set phase by the first step, a third for counting the number of occurrences of error accepted signal
And the step, if the occurrence count of the number of times the error is "0" Ru der,
A fourth step of determining the set phase as the phase of the sampling clock of the digital data; and, if the number of times of occurrence of the counted error is not “0” ,
Change the set phase and return to the second step
The fifth step and the second, third and fifth steps are repeatedly executed a predetermined number of times.
The minimum number of occurrences of errors counted during
The sixth step and the second, third and fifth steps are repeatedly executed a predetermined number of times.
The number of occurrences of the counted error is not "0"
The set phase when the stored minimum value is obtained.
7. A method for automatically adjusting the phase of a sampling clock, comprising: a seventh step of determining the phase of the sampling clock. 2. An automatic phase adjusting device for a sampling clock for digital data transmitted by being superimposed on a television signal, comprising: a phase setting means for sequentially setting different phases; and each phase set by the phase setting means. A signal input means for inputting a signal containing the digital data respectively; a check means for detecting the presence or absence of an error in each of the signals input by the signal input means at the same phase a predetermined number of times; The number of occurrences of the error
An error counting unit that counts for each phase set by the phase setting unit; and a count number by the error counting unit is “0”.
In this case, the set phase is determined as the phase of the sampling clock of the digital data, and when the count number by the error counting means is not “0”,
Changes the phase set by the phase setting means , and an error occurs.
An automatic phase adjusting device for sampling clocks , comprising: sampling clock determining means for determining the phase having the minimum value as the phase of the sampling clock of the digital data.