JPH05175823A - Level converting circuit - Google Patents

Abstract

PURPOSE:To increase the degree of integration and to reduce the power consumption with a relatively simple circuit constitution consisting of a small number of elements. CONSTITUTION:A PMOS 20 and a bipolar transistor TR 21 constitute a current switch which switches a supply current, and an input signal V1 at the MOS or BiM0S level is inputted to the PMOS 20. Then, the current switch is differentially operated, and an output TR 40 is driven by the collector potential of the TR 21, and an output signal V0 at the ECL level is outputted from the emitter of the TR 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a BiMOS integrated circuit in which a bipolar transistor and a MOS transistor are mixed, and the ECL (Emitter Coupled Logi) is calculated from the MOS or BiMOS signal level.
c) The present invention relates to a level conversion circuit that performs level conversion to a signal level.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one as described in JP-A-63-313916.

The level conversion circuit described in this document is
This is a level conversion circuit for converting the level of a MOS or BiMOS signal into an ECL signal, and its configuration will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing a configuration example of a conventional level conversion circuit.

This level conversion circuit is composed of MOS or Bi.
This is a circuit for converting the level of a MOS level input signal V _I into an ECL level output signal V _O , and is a P channel type MO.
It has an input bias potential setting circuit composed of an S transistor (hereinafter referred to as PMOS) 1, a resistor (or diode) 2 and a constant current source 3. The output side of the input bias potential setting circuit is connected to an emitter follower circuit including an NPN transistor 4 and a constant current source 5, and the output side thereof is connected to an ECL basic circuit.

The ECL basic circuit is connected to a current switch composed of NPN transistors 6 and 7 for switching the power supply current by the differential between the emitter potential of the transistor 4 and the ECL reference potential V _r, and the collector side of the transistor 7. It is composed of a resistor 8, a constant current source 9 commonly connected to the emitters of the transistors 6 and 7, and an output stage. The output stage is composed of an emitter follower circuit including an NPN transistor 10 and a constant current source 11. In FIG. 2, V _CC is a high-potential power source potential, and V _EE is a low-potential power source potential.

In this level conversion circuit, MOS or B
The iMOS level input signal V _I is received by the PMOS 1 to generate a current signal. This current signal drives the current switch composed of the transistors 6 and 7 through the transistor 4 of the emitter follower circuit, and the collector potential of the transistor 7 controls the base of the transistor 10 at the output stage. Thereby, from the emitter of the transistor 10,
An ECL level output signal V _O can be output.

[0008]

However, the level conversion circuit having the above structure has the following problems.

The conventional level conversion circuit has a BiMOS integrated circuit configuration which utilizes the high speed of the bipolar transistor, the low power consumption of the MOS transistor, and the high integration, but the high integration of the integrated circuit device, Further, from the demand for low power consumption, further high integration and low power consumption of the level conversion circuit are required. However, in the conventional level conversion circuit, at least three elements, that is, the PMOS 1, the resistor (or diode) 2 and the transistor 4 are required as an element for generating an input signal to the current switch composed of the transistors 6 and 7. Becomes
Furthermore, two constant current sources 3 and 5 for operating these three elements are also required. Therefore, the presence of at least three elements 1, 2, 4 and a constant current source 3, 5 for generating the input signal to the current switch makes the device highly integrated when the level conversion circuit is mounted on the integrated circuit device. It is a major factor that hinders reduction in power consumption and power consumption, and it is difficult to solve it with a relatively simple circuit configuration using a small number of elements.

SUMMARY OF THE INVENTION The present invention has the problems that the above-mentioned conventional technique has, with a relatively simple circuit configuration using a small number of elements.
(EN) Provided is a level conversion circuit which solves the problem that it is difficult to improve higher integration and lower power consumption.

[0011]

In order to solve the above-mentioned problems, the present invention comprises a BiMOS integrated circuit in which a bipolar transistor and a MOS transistor are combined.
In a level conversion circuit for converting a level from an OS or BiMOS signal level to an ECL signal level, a source is connected to a power supply potential, a drain is connected to a constant current source, and a PMOS gate-controlled by the MOS or BiMOS signal level, A current switch is composed of a bipolar transistor whose base is connected to the ECL reference potential, one of the emitter and collector is connected to the drain of the PMOS, and the other is connected to the output stage.

[0012]

According to the present invention, since the level conversion circuit is constructed as described above, the PMOS forming the current switch is formed.
However, since the gate is directly controlled by the MOS or BiMOS signal level, the number of circuit elements of the input circuit for generating the input signal to the current switch and the simplification of the circuit configuration can be achieved. Therefore, the above problem can be solved.

[0013]

1 is a BiM showing a first embodiment of the present invention.
It is a circuit diagram of a level conversion circuit configured by an OS integrated circuit.

This level conversion circuit includes a current switch composed of a PMOS 20 and an NPN transistor 21 for switching a power supply current flowing between a high power supply potential V _CC and a low power supply potential V _EE . PMOS 20
_{Has the} source at the power supply potential V _CC and the gate at the MOS or B
Each is connected to the input signal V _I of the iMOS level. The transistor 21 has a collector connected to the power supply potential V _CC via the load resistor 22, a base connected to the ECL reference potential V _r , and an emitter connected to the drain of the PMOS 20. The drain of the PMOS 20 and the emitter of the transistor 21 are connected to the power supply potential V _EE via the constant current source 23. The collector of the transistor 21 is connected to the output stage that outputs the ECL level output signal V _O.

The output stage is composed of an emitter follower circuit composed of an NPN transistor 40 and a constant current source 41. The collector of the transistor 40 has a power supply potential V _CC.
The bases are connected to the collectors of the transistors 21, respectively, and the output signal V _O is output from the emitters. The emitter of the transistor 40 is connected to the power supply potential V _EE via the constant current source 41.

Next, the operation will be described.

First, when the MOS or BiMOS level input signal V _I is at "H" level, the PMOS 20 is turned off. At this time, the emitter potential of the transistor 21 becomes lower than that when the PMOS 20 is on, and the transistor 21 has a sufficient base-emitter voltage V.
_BE is secured and the transistor 21 is turned on. The emitter current of the transistor 21 supplied to the constant current source 23 is supplied from the power supply potential V _CC through the load resistor 22. Due to the voltage drop of the resistor 22, the transistor 40
Is base controlled. At this time, the emitter potential of the transistor 40 is a value obtained by subtracting the voltage drop due to the base-emitter voltage V _BE of the transistor 40 and the voltage drop due to the load resistor 22 from the power supply potential V _CC, so that the transistor 40 An “L” level output signal V _O is output from the emitter.

When the input signal V _I becomes "L" level, P
The MOS 20 is turned on, and the drain potential of the PMOS 20, that is, the emitter potential of the transistor 21 changes to the P level.
It will be higher than when the MOS 20 is off. As a result, a sufficient base-emitter voltage V _BE is not secured in the transistor 21, and the transistor 21 turns off.
Only the base current to the transistor 40 flows through the load resistor 22, and the voltage drop due to the load resistor 22 is smaller than that when the transistor 21 is on. The emitter potential of the transistor 40 follows this, and becomes a potential closer to the power supply potential V _CC than when outputting the "L" level, and the emitter of the transistor 40 is "H".
The level output signal V _O is output.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows the second embodiment, and the same elements as those in the first embodiment are designated by the same reference numerals.

The difference between the second embodiment and the first embodiment is that the NPN transistor 21 is replaced by the NMOS 200. In the NMOS 200, the drain is connected to the power supply potential V _CC via the load resistor 22, the source is connected to the drain of the PMOS 20, and the gate is PMOS.
Commonly connected to 20 gates.

Next, the operation will be described.

First, when the MOS or BiMOS level input signal V _I is at "H" level, the PMOS 20 is in the off state and the NMOS 200 is in the on state.

NMOS 200 supplied to constant current source 23
The source current I _MNIS, load resistance than the power supply potential V _CC 22
Supplied through. In the load resistance 22, the NMOS 20
And the drain current I _MNID to 0, the voltage drop caused by the base current I _QIB to the transistor 40. The base of the transistor 40 is controlled by this voltage drop. At this time, the emitter potential of the transistor 40 becomes a value obtained by subtracting the voltage drop due to the base-emitter voltage V _BE of the transistor 40 and the voltage drop due to the load resistor 22 from the power supply potential V _CC.
An "L" level output signal V _O is output from the 0 emitter.

When the input signal V _I becomes "L" level, P
The MOS 20 is turned on, the NMOS 200 is turned off, the drain current I _MNID of the _{NMOS 200} does not flow through the load resistor 22, and the base current I to the transistor 40 is not supplied.
Only _QIB flows. Therefore, the voltage drop due to the load resistance 22 is smaller than when the NMOS 40 is on. The emitter potential of the transistor 40 also follows this, and becomes a potential closer to the power supply potential V _CC than when outputting the "L" level, and the emitter of the transistor 40 outputs the "H" level output signal V _O. Is output.

The present invention has the following advantages.

The three elements for generating the input signal to the current switch in the conventional circuit are removed, and the current switch is replaced by the PMOS 20 and the transistor 21 or NM.
The input signal V _I is directly input to the gate of the PMOS 20. Therefore, along with the removal of the three elements for generating the input signal to the conventional current switch, the two constant current sources can also be removed, and only two constant current sources 23 and 41 in total are required as the level conversion circuit. is there.

Therefore, the level conversion from the MOS or BiMOS signal level to the ECL signal level can be performed with a very simple circuit configuration with a small number of elements, and the pattern area for circuit formation can be reduced and the power consumption can be reduced. Further, since the number of elements used is smaller than that of the conventional level conversion circuit, level conversion can be performed at high speed. Therefore, by mounting the level conversion circuit of this embodiment, it is possible to realize a BiMOS integrated circuit device with high integration and low power consumption and high speed.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following.

(A) In FIG. 1, the NPN-type transistor 21 forming the current switch is replaced with a PNP-type transistor, and the polarity of the ECL reference potential V _r is changed accordingly. , The effect is obtained.

(B) Although the output stage of FIG. 1 is composed of an emitter follower circuit composed of an NPN transistor 40 and a constant current source 41, it may be composed of other circuits. For example,
In order to increase the load driving force, the transistor 40 may be composed of a Darlington transistor circuit including a plurality of stages of transistors. Furthermore, NPN type transistor 4
0 may be replaced with a PNP transistor.

(C) Further, in FIG. 3, the conductivity types of the PMOS 20 and the NMOS 200 forming the current switch are reversed, and the PMOS 20 is changed to the NMOS, and the NMOS 20.
It is also possible for 0 to be a PMOS.

[0032]

As described in detail above, according to the present invention, a current switch is constituted by a PMOS and a bipolar transistor, and a MOS is directly connected to the gate of the PMOS.
Alternatively, since the BiMOS signal is input, the number of elements used for generating an input signal to the current switch and the number of constant current sources used can be reduced, the circuit configuration can be simplified, and a pattern for forming a circuit can be obtained. It is possible to reduce the area and power consumption. Furthermore, the level conversion can be performed at high speed by reducing the number of elements used. Therefore, a high-density BiMOS integrated circuit device with high integration and low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a level conversion circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional level conversion circuit.

FIG. 3 is a circuit diagram of a level conversion circuit showing a second embodiment of the present invention.

[Explanation of symbols]

20 PMOS 21,40 NPN-type transistor 22 a load resistor 23 and 41 output signals V _r ECL reference potential of the input signal V _O ECL level of the constant current source V _I CMOS or BiMOS level

Claims (2)

[Claims] 1. A MOS transistor level signal to EC
A level conversion circuit for converting to an L level signal, comprising: a first electrode, a second electrode and a gate electrode, the first electrode being connected to a high potential power source, and the MOS transistor level signal being inputted to the gate electrode. A MOS transistor, one end of which is connected to the second electrode of the MOS transistor and the other end of which is connected to a low potential power source, and one of the emitter and collector is connected to one end of the constant current source. One of the other is connected to the high-potential power supply via a load resistor and a base is given a reference potential, and a base is controlled by a potential appearing between the load resistor and the first bipolar transistor. A second bipolar transistor having a collector connected to the high-potential power supply and an emitter outputting the ECL level signal And a second bipolar transistor for performing the level conversion circuit. 2. A MOS transistor level signal to EC
A level conversion circuit for converting to an L level signal, comprising a first electrode, a second electrode, and a gate electrode, the first electrode being connected to a high potential power source, and the MOS transistor level signal being input to the gate electrode. A constant current source having one end connected to the second electrode of the first MOS transistor and the other end connected to a low potential power source; and a first electrode connected to one end of the constant current source. A second M having a conductivity type opposite to that of the first MOS transistor, two electrodes of which are connected to the high potential power source through a load resistor and a gate electrode of which is connected to a gate electrode of the first MOS transistor.
An OS transistor, and a bipolar transistor whose base is controlled by a potential appearing between the load resistor and the second MOS transistor, the collector being connected to the high potential power supply and the emitter outputting the ECL level signal. A level conversion circuit comprising: