JPH05175228A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form an insulated gate type field-effect transistor wherein field inversion is restrained and punch through breakdown voltage is improved, by using an electric field shielding member under a gate electrode, and forming high resistance regions on both sides of a field insulating film. CONSTITUTION:The drain region 40 of an insulated gate type field-effect transistor in an element region 32 of a semiconductor substrate 31 is constituted as an LDD structure around which a low concentration impurity region 39 is arranged. The element region 32 is surrounded by a field oxide film 33, which is surrounded by a guard ring region. The peripheral part of the guard ring region is a low concentration impurity region 41. Since the low concentration impurity regions 39, 41 exist on both sides of a field oxide film 33, punch through which is generated on the interface with the substrate under the field oxide film 33 can be restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage insulated gate field effect transistor, and more particularly to a high breakdown voltage semiconductor device applied to a large liquid crystal driver LSI.

[0002]

2. Description of the Related Art FIG. 5 is a plan view of a conventional semiconductor device and shows the structure of a high breakdown voltage insulated gate field effect transistor.

An insulated gate field effect transistor 12 is formed on a semiconductor substrate 11. Gate electrodes 13-1, 13-2
A source region 14 and a drain region 15 are formed on the surface of the substrate 11 with a space therebetween.
-1,15-2 are formed. This allows the source region 14
Transistors Tr1 and Tr2 with a common current path
Are configured.

A field insulating film 16 is formed on the substrate 11 so as to surround the entire insulated gate field effect transistor 12. Substrate 11 outside field insulating film 16
On the surface, a guard ring region 17 having the same conductivity type as that of the substrate 11 and having a relatively high concentration of impurities introduced is formed. Each gate wiring 18 is made of, for example, aluminum, and each contact hole is formed on the interlayer insulating film (not shown).
The gate electrodes 13-1 and 13-2 are connected via 19 respectively.

According to the conventional inter-element wiring, when a high potential is applied to the gate wiring, the field insulating film under the gate wiring is formed.
A field inversion phenomenon occurs at the interface between 16 and the base 11. For example, when the transistor Tr1 is off, the transistor T
When a high voltage (30 V or more) is applied between the gate and drain of r2, the high electric field inverts the field and channel regions under the gate wiring 18-2 and the gate electrode 13-2 of the transistor Tr2, and the drain region The high voltage applied to 15-2 causes a punch-through state between the drain region 15-2 and the guard ring region 17 which is a different kind of impurity.

[0006]

As described above, in the conventional case, under the field insulating film, the field inversion is performed at the place where the gate wiring to which a high voltage is applied crosses over the field insulating film separating the drain region and the impurity region. There is a defect that a phenomenon that breaks down or generates a leakage current, which deteriorates the reliability of the semiconductor device, occurs. This invention was made in consideration of the above circumstances,
An object of the invention is to provide a semiconductor device having high breakdown voltage and high reliability.

[0007]

According to another aspect of the present invention, there is provided a semiconductor device comprising: an insulating gate field effect transistor formed on a semiconductor substrate; and a field insulating film which surrounds the insulated gate field effect transistor and separates it from other element regions. An impurity region provided on the surface of the semiconductor substrate so as to surround the outside of the field insulating film, and the gate electrode of the insulated gate field effect transistor is connected to another element region. And an electric field shield member provided between the gate wiring and a field insulating film below the gate wiring. Further, instead of providing the electric field shield member, the LDD structure is adopted, and the guard ring region surrounding the outside of the field insulating film is constituted by surrounding the low resistance region with the high resistance region.

[0008]

According to the present invention, the field inversion is suppressed by the electric field shield member and by forming the high resistance region (low concentration impurity region) on both sides of the field insulating film,
Improve punch-through breakdown voltage.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, showing the structure of a high breakdown voltage insulated gate field effect transistor. The same parts as those in FIG. 5 are designated by the same reference numerals. In this invention, since the gate electrodes 13-1 and 13-2 of the insulated gate field effect transistor 12 are connected to other element regions, the gate wiring 18 (18-1, 18-2) is formed.
-2) provides an electric field shield member 21 between the gate wiring 18 and the field insulating film 16 below the gate wiring 18 at a position where the field insulating film 16 and the guard ring region 17 are crossed over. The electric field shield member 21 is made of, for example, polysilicon and takes a potential from the substrate 11.

According to this structure, by providing the electric field shield member 21, the high electric field from the gate wiring 18 is almost completely cut off. As a result, the carriers under the field insulating film 16 under the gate wiring 18 are always kept in a stable state. As a result, field inversion that occurs at the interface with the substrate under the field insulating film 16 is suppressed, and the punch-through breakdown voltage is improved.

FIG. 2 is a characteristic curve of the drain current ID with respect to the drain-source voltage of the series transistors Tr1 and Tr2 shown in FIG. Conventional FIG. 5 indicated by a broken line
2 has a higher breakdown voltage than the case of FIG.

Further, as a second embodiment of the present invention,
Instead of not providing the electric field shield member 21 as shown in FIG.
A structure in which the insulated gate field effect transistor has an LDD structure, and in the guard ring region surrounding the outside of the field insulating film, a high-concentration low-concentration impurity diffusion region is surrounded by a low-resistance high-concentration impurity diffusion region. To This semiconductor device will be described below with reference to FIGS. In addition, in FIGS. 3 and 4, (a)
Is a plan view and (b) is a sectional view taken along line aa.

First, as shown in FIGS. 3A and 3B, a thick oxide film (field oxide film) 33 is formed on the semiconductor substrate 31 around the element region 32 by a selective oxidation method. A thin oxide film 34 having the same film thickness as the element region 32 is formed on the outer periphery of the field oxide film 33. This portion becomes the guard ring area 35. Then, the gate electrode 38 is formed on the device region 32.
Will be formed.

Next, as shown in FIGS. 4 (a) and 4 (b), a method of using a gate electrode as a mask and a method of patterning a resist film by a known method are used, and a high conductivity type opposite to the substrate 31 is used. A high-concentration impurity region 36 is formed by selectively introducing a high-concentration impurity into the source and drain regions.
Next, a high-concentration impurity having the same conductivity type as that of the base 31 is selectively introduced into a portion of the guard ring region 35 excluding the peripheral edge. Thereby, the high concentration impurity region 37 is formed. Then, a low concentration impurity region 39 having a lower impurity concentration than that of the high concentration impurity region 36 is formed. As a result, the drain region 40 having the LDD structure is formed. Next, around the high-concentration impurity region 37, a low-concentration impurity region having a lower impurity concentration than that is formed.
A guard ring region 35, which is surrounded by 41 and whose peripheral portion is composed of a low-concentration impurity, is formed. Each gate wiring 42 is made of, for example, aluminum, and each gate electrode is formed through each contact hole 43 formed on the interlayer insulating film (not shown).
38 connected respectively.

According to this structure, since the low concentration impurity regions 39 and 41 are present on both sides of the field oxide film 33,
Field inversion that occurs at the interface with the substrate under the field oxide film 33 is suppressed. As a result, the punch-through breakdown voltage is improved, and the breakdown voltage of the series transistor can be improved as in the case of FIG. Although the low resistance region is formed by the high concentration impurity regions 36 and 37 in the configuration of the second embodiment, a silicide region may be used instead.

[0017]

As described above, according to the present invention,
A high-reliability semiconductor device that suppresses field inversion and improves punch-through breakdown voltage can be provided by the electric field shield member and by forming the high resistance regions on both sides of the field insulating film.

[Brief description of drawings]

FIG. 1 is a plan view showing the configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a characteristic curve of drain current ID with respect to a drain-source voltage of the series transistor in FIG.

3A and 3B are views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention, FIG. 3A is a plan view, and FIG.
Is a cross-sectional view taken along line aa of FIG.

FIG. 4 is a configuration of a semiconductor device according to a second embodiment of the present invention, in which (a) is a plan view and (b) is a- in (a).
Sectional drawing which follows the a line.

FIG. 5 is a plan view showing the configuration of a conventional high breakdown voltage insulated gate field effect transistor.

[Explanation of symbols]

11, 31 ... Semiconductor substrate, 12 ... Insulated gate field effect transistor, 13-1, 13-2, 38 ... Gate electrode, 14 ... Source region, 15-1, 15-2 ... Drain region, 16 ... Field insulating film , 17, 35 ... Guard ring area, 18, 42 ... Gate wiring,
19, 43 ... Contact hole, 21 ... Electric field shield member, 32
... Element region, 33 ... Field oxide film, 34 ... Oxide film, 36,
37 ... High-concentration impurity regions, 39, 41 ... Low-concentration impurity regions.

Claims (2)

[Claims] 1. An insulated gate field effect transistor formed on a semiconductor substrate, a field insulating film that surrounds the insulated gate field effect transistor and separates from other element regions, and surrounds the outside of the field insulating film. An impurity region provided on the surface of the semiconductor substrate, a gate wiring extending over the field insulating film and the impurity region so that the gate electrode of the insulated gate field effect transistor is connected to another element region, and the gate A semiconductor device, comprising: an electric field shield member provided between a wiring and a field insulating film below the gate wiring. 2. An insulated gate field effect transistor having an LDD structure formed on a semiconductor substrate, a field insulating film surrounding the insulated gate field effect transistor and separated from other element regions, and a field insulating film comprising: A guard ring region, which is provided on the surface of the semiconductor substrate so as to surround the outside and surrounds a low resistance region with a high resistance region, and a gate electrode of the insulated gate field effect transistor are connected to other element regions. And a gate wiring extending over the field insulating film and the impurity region.