JPH0517294A - Production of substrate for monolithic liquid crystal display element - Google Patents

Production of substrate for monolithic liquid crystal display element

Info

Publication number
JPH0517294A
JPH0517294A JP17416691A JP17416691A JPH0517294A JP H0517294 A JPH0517294 A JP H0517294A JP 17416691 A JP17416691 A JP 17416691A JP 17416691 A JP17416691 A JP 17416691A JP H0517294 A JPH0517294 A JP H0517294A
Authority
JP
Japan
Prior art keywords
substrate
etching
single crystal
light
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17416691A
Other languages
Japanese (ja)
Other versions
JP2815249B2 (en
Inventor
Hisakazu Miyatake
久和 宮武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP17416691A priority Critical patent/JP2815249B2/en
Publication of JPH0517294A publication Critical patent/JPH0517294A/en
Application granted granted Critical
Publication of JP2815249B2 publication Critical patent/JP2815249B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To suppress the generation of unequal thicknesses in the Si single crystal substrate constituting a substrate for a monolithic liquid crystal display element by etching this substrate. CONSTITUTION:While the Si single crystal substrate 3 stuck to a quartz substrate 2 or glass substrate are subjected to etching dividedly in plural zones, the thicknesses of the respective zones are detected by optical means consisting of a light emitting section 6 and a light receiving section 7 and the etching rates of the respective zones to be executed by parallel flat plate electrodes 5 are controlled in accordance with the results of the detection. The etching rate to the thick zones are, therefore, increased and the etching rates to the thin zones are decreased, by which the Si single crystal substrate 3 is eventually etched at nearly the uniform thickness distribution.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、モノリシック液晶表示
素子に用いる基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a substrate used for a monolithic liquid crystal display device.

【0002】[0002]

【従来の技術】カラー液晶表示素子は、従来、石英また
はガラス製基板上にポリシリコン膜又はアモルファスS
i膜を堆積した基板が用いられ、その基板上に画素部と
駆動回路部とを形成することによりモノリシック型に作
製されていた。
2. Description of the Related Art Conventionally, a color liquid crystal display device has a polysilicon film or amorphous S on a quartz or glass substrate.
A substrate on which an i film is deposited is used, and a pixel portion and a driving circuit portion are formed on the substrate to produce a monolithic type.

【0003】ところが、近年においてはハイビジョン対
応用のカラー液晶表示素子の開発が進められ、そのため
に上記ポリシリコン膜やアモルファスSi膜に代えて、
Si単結晶基板を石英またはガラス製基板に貼り合わせ
た基板が採用されつつある。これは、ポリシリコン膜や
アモルファスSi膜ではトランジスタのチャネル部移動
度がそれぞれ50cm2-1sec-1、1cm2-1se
-1程度と低いが、Si単結晶では前記移動度が著しく
大きいからである。
However, in recent years, development of a color liquid crystal display device for high-definition has been advanced, and therefore, instead of the above polysilicon film or amorphous Si film,
Substrates in which a Si single crystal substrate is bonded to a quartz or glass substrate are being adopted. This is because the mobility of the channel portion of the transistor is 50 cm 2 V -1 sec -1 and 1 cm 2 V -1 se for the polysilicon film and the amorphous Si film, respectively.
This is because it is as low as about c −1 , but the mobility is extremely large in a Si single crystal.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、Si単
結晶基板をそのままで貼り合わせた基板の場合、そのS
i単結晶基板の厚さムラが大きく、例えば直径4インチ
の基板では厚さ1μmに対して約30〜40%もあり、
表示素子の作製上、大きな障害となっている。そのた
め、厚みが500〜600μmのSi単結晶基板を石英
基板等に貼り合わせたのち、機械研磨又は化学研磨によ
って例えば1μmまで研磨しているが、この方法では厚
さムラを5%以下にはできないため、ハイビジョン表示
素子の実現化に対応できずにいた。
However, in the case of a substrate obtained by directly bonding Si single crystal substrates, the S
The thickness of the i single crystal substrate is large, for example, a substrate having a diameter of 4 inches has a thickness of about 30 to 40% for a thickness of 1 μm.
This is a major obstacle in manufacturing a display element. Therefore, a Si single crystal substrate having a thickness of 500 to 600 μm is bonded to a quartz substrate or the like, and then mechanically polished or chemically polished to, for example, 1 μm. However, the thickness unevenness cannot be reduced to 5% or less by this method. Therefore, it was not possible to support the realization of high-definition display devices.

【0005】本発明はこのような従来技術の課題を解決
すべくなされたものであり、Si単結晶基板にエッチン
グを施す工夫をして厚さムラが発生するのを抑制して、
ハイビジョン用モノリシック液晶表示素子の実現性を高
め得るモノリシック液晶表示素子用基板の製造方法を提
供することを目的とする。
The present invention has been made to solve the above-mentioned problems of the prior art, and suppresses the occurrence of thickness unevenness by devising etching of a Si single crystal substrate.
An object of the present invention is to provide a method for manufacturing a substrate for a monolithic liquid crystal display device, which can enhance the feasibility of a monolithic liquid crystal display device for high definition.

【0006】[0006]

【課題を解決するための手段】本発明は、石英又はガラ
ス製基板に貼り合わせたSi単結晶基板をエッチングし
てモノリシック液晶表示素子用基板を製造する方法であ
って、該Si単結晶基板に対して複数のゾーンに分割し
てエッチングを施しつつ、各ゾーンの厚みを光学的手段
にて検出し、その検出結果に基づき各ゾーンのエッチン
グ量を制御するので、そのことにより上記目的を達成で
きる。
The present invention is a method for producing a substrate for a monolithic liquid crystal display device by etching a Si single crystal substrate bonded to a quartz or glass substrate. On the other hand, while performing the etching divided into a plurality of zones, the thickness of each zone is detected by an optical means, and the etching amount of each zone is controlled based on the detection result. Therefore, the above object can be achieved. .

【0007】[0007]

【作用】本発明にあっては、石英又はガラス製基板に貼
り合わせたSi単結晶基板に対し、複数のゾーンに分割
してエッチングを施しつつ、各ゾーンの厚みを光学的手
段にて検出し、その検出結果に基づき各ゾーンのエッチ
ング量を制御する。このため、厚いゾーンに対してエッ
チング量を増大させ、薄いゾーンに対してエッチング量
を減少させることにより、Si単結晶基板は各ゾーンに
おいてほぼ均一な厚み分布でエッチングが施されること
となる。
According to the present invention, an Si single crystal substrate bonded to a quartz or glass substrate is divided into a plurality of zones for etching, and the thickness of each zone is detected by an optical means. The etching amount of each zone is controlled based on the detection result. Therefore, by increasing the etching amount in the thick zone and decreasing the etching amount in the thin zone, the Si single crystal substrate is etched with a substantially uniform thickness distribution in each zone.

【0008】[0008]

【実施例】以下、本発明の一実施例を説明する。EXAMPLE An example of the present invention will be described below.

【0009】図1は本実施例に用いるドライエッチャー
を示す模式図である。このドライエッチャーは、被エッ
チング対象の基板1を保持するステージ4と、基板1に
平行に対向配設した反応性イオンエッチ用の平行平板電
極5と、平行平板電極5の両側に設けられた、例えばレ
ーザ光を発生する発光部6及びその受光部7からなる光
干渉計と、受光部7にて検出された信号を入力し、その
入力信号に基づいて前記平行平板電極5の出力制御を行
うCPU8と、ステージ4と平行平板電極5との間に電
圧を印加する交流電源9とを備える。前記ステージ4に
は、本実施例においては、基板1として石英基板2にS
i単結晶基板3を貼り合わせたものがセットされる。
FIG. 1 is a schematic diagram showing a dry etcher used in this embodiment. This dry etcher is provided on a stage 4 for holding the substrate 1 to be etched, a parallel plate electrode 5 for reactive ion etching which is arranged in parallel and opposite to the substrate 1, and both sides of the parallel plate electrode 5. For example, an optical interferometer including a light emitting section 6 for generating a laser beam and its light receiving section 7 and a signal detected by the light receiving section 7 are input, and output control of the parallel plate electrode 5 is performed based on the input signal. A CPU 8 and an AC power supply 9 for applying a voltage between the stage 4 and the parallel plate electrode 5 are provided. In the present embodiment, the stage 4 is provided with a quartz substrate 2 and an S
The i-single crystal substrate 3 bonded together is set.

【0010】前記平行平板電極5は反応性イオンエッチ
用に設けられ、基板1側の表面(この例では底面)には
メッシュ状に分割して多数の分割電極5aが縦横に配設
されている。各分割電極5aはそれぞれ、その下方の基
板1部分をエッチングゾーンとしてエッチングでき、各
分割電極5aに与えられる電圧が前記CPU8にて調整
されることにより、エッチング量の調整が行われる。
The parallel plate electrode 5 is provided for reactive ion etching, and a large number of divided electrodes 5a are arranged vertically and horizontally on the surface (bottom surface in this example) on the substrate 1 side in a mesh shape. . Each divided electrode 5a can be etched using the substrate 1 portion below it as an etching zone, and the amount of etching is adjusted by adjusting the voltage applied to each divided electrode 5a by the CPU 8.

【0011】前記発光部6は、その光照射方向をステー
ジ4に保持された基板1の上表面に向け、基板1の上表
面全域を照射するように設けている。受光部7は、縦横
に多数配設した受光素子を備え、各素子の検出視野を基
板1の上表面に向けている。各素子の検出視野は、前記
分割電極5aにて個別にエッチングされる基板1のエッ
チングゾーンと、1対1で対応するようになしてある。
The light emitting section 6 is provided so that its light irradiation direction is directed to the upper surface of the substrate 1 held by the stage 4, and the entire upper surface of the substrate 1 is irradiated. The light receiving section 7 includes a large number of light receiving elements arranged vertically and horizontally, and the detection field of view of each element is directed to the upper surface of the substrate 1. The detection visual field of each element has a one-to-one correspondence with the etching zone of the substrate 1 that is individually etched by the divided electrodes 5a.

【0012】各受光素子は、前記発光部6での光強度を
調節して一定値にすることにより、基板1の上側にある
Si単結晶基板3の上表面からの反射光と、その下表面
からの反射光ととの干渉光に基づいて、Si単結晶基板
3の各エッチングゾーンの厚みを検出できる。この検出
された厚み信号はCPU8に与えられる。CPU8は入
力信号に基づいて平坦度を検出し、平行平板電極5をフ
ィードバック制御する。この制御は、エッチング量が過
多となっているエッチングゾーンに対応する分割電極5
aに対しては印加電圧を低くし、過小となっているエッ
チングゾーンに対応する分割電極5aに対しては印加電
圧を高くする。
Each light receiving element adjusts the light intensity in the light emitting portion 6 to a constant value, so that the light reflected from the upper surface of the Si single crystal substrate 3 above the substrate 1 and the lower surface thereof. The thickness of each etching zone of the Si single crystal substrate 3 can be detected based on the interference light with the reflected light from the. The detected thickness signal is given to the CPU 8. The CPU 8 detects the flatness based on the input signal and feedback-controls the parallel plate electrode 5. This control is performed by the divided electrode 5 corresponding to the etching zone where the etching amount is excessive.
The applied voltage is made low for a and the applied voltage is made high for the divided electrodes 5a corresponding to the etching zone which is too small.

【0013】かかるドライエッチャーによるエッチング
は次のように行う。先ず、石英基板2にSi単結晶基板
3を貼り合わせた基板1を、エッチングを行うSi単結
晶基板3側を平行平板電極5へ向けてステージ4にセッ
トする。この石英基板2は、例えば厚さ約500μm、
直径6インチであり、一方のSi単結晶基板3はこれと
同等の厚さ、直径を有する。なお、Si単結晶基板3は
その厚さがもっと薄いものであっても構わない。
Etching with such a dry etcher is performed as follows. First, the substrate 1 in which the Si single crystal substrate 3 is bonded to the quartz substrate 2 is set on the stage 4 with the side of the Si single crystal substrate 3 to be etched facing the parallel plate electrode 5. The quartz substrate 2 has, for example, a thickness of about 500 μm,
The diameter is 6 inches, and one Si single crystal substrate 3 has the same thickness and diameter. The Si single crystal substrate 3 may be thinner.

【0014】次いで、交流電源9を通電状態にすると共
に、発光部6、受光部7及びCPU8を動作させ、エッ
チングを開始する。このとき、発光部6から出射される
レーザ光の強度は、レーザ光の一部が基板1の下側の石
英基板2の上表面に達するように定めておく。
Then, the AC power supply 9 is turned on, and the light emitting section 6, the light receiving section 7 and the CPU 8 are operated to start etching. At this time, the intensity of the laser light emitted from the light emitting unit 6 is set so that a part of the laser light reaches the upper surface of the quartz substrate 2 below the substrate 1.

【0015】これにより、Si単結晶基板3が分割電極
5aにより各エッチングゾーン毎にエッチングされる。
このエッチングのとき、基板1の各エッチングゾーン毎
のエッチング量は、受光部7の対応する各受光素子にて
検出され、この検出信号に基づいてCPU8が上述した
ように分割電極5aへ印加する電圧を制御する。例え
ば、分割電極5aの左から2番目のBにてエッチングさ
れている基板1部分を検出している受光部7の受光素子
bで検知した光強度に基づいて、分割電極5aの左から
2番目のBにフィードバックし、そのBの分割電極5a
に対応するエッチングゾーンのエッチング速度を制御す
る。なお、A〜Hで示す各分割電極5aにおいても、対
応するa〜hで示す受光素子にて検出された信号に基づ
いて同様な制御が行われる。
As a result, the Si single crystal substrate 3 is etched by the divided electrodes 5a in each etching zone.
At the time of this etching, the etching amount of each etching zone of the substrate 1 is detected by each corresponding light receiving element of the light receiving unit 7, and the voltage applied to the divided electrode 5a by the CPU 8 as described above based on this detection signal. To control. For example, based on the light intensity detected by the light receiving element b of the light receiving unit 7 that detects the portion of the substrate 1 that is etched at the second B from the left of the divided electrode 5a, the second from the left of the divided electrode 5a is detected. To the B of the divided electrode 5a of the B
To control the etching rate of the etching zone corresponding to. Similar control is performed on each of the divided electrodes 5a indicated by A to H based on the signal detected by the corresponding light receiving element indicated by ah.

【0016】従って、本実施例においては、石英基板2
に貼り合わせたSi単結晶基板3を均一な厚み分布でエ
ッチングを行うことができ、最終的に所望の厚み、例え
ば1μmにまでエッチングを施したところ、厚みムラを
5%以下に抑制することが可能となった。
Therefore, in this embodiment, the quartz substrate 2 is used.
The Si single crystal substrate 3 bonded to the substrate can be etched with a uniform thickness distribution, and when finally etched to a desired thickness, for example, 1 μm, thickness unevenness can be suppressed to 5% or less. It has become possible.

【0017】上記実施例ではSi単結晶基板を石英基板
に貼り合わせた基板を例に挙げて説明しているが、本発
明はこれに限らず、Si単結晶基板をガラス基板に貼り
合わせた基板を対しても適用できることはもちろんであ
る。
In the above embodiments, the substrate in which the Si single crystal substrate is bonded to the quartz substrate has been described as an example, but the present invention is not limited to this, and the substrate in which the Si single crystal substrate is bonded to the glass substrate is used. Of course, it can be applied to.

【0018】また、上記実施例では反応性イオンエッチ
によりSi単結晶基板をエッチングするようにしている
が、本発明はこれに限らず、他のエッチング法を用いて
も実施できる。
Further, although the Si single crystal substrate is etched by the reactive ion etching in the above-mentioned embodiment, the present invention is not limited to this, and other etching methods can be used.

【0019】[0019]

【発明の効果】以上詳述したように本発明による場合に
は、厚みムラを5%以下に抑制することができるので、
それまで用いていたポリシリコンやアモルファスシリコ
ンに代えて、単結晶Siに液晶用表示素子用画素部と駆
動回路とを一体的に作り込むことにより、将来のハイビ
ジョン用モノリシック液晶表示素子の実現性を高めるこ
とができる。
As described above in detail, in the case of the present invention, the thickness unevenness can be suppressed to 5% or less.
In place of the polysilicon and amorphous silicon that have been used up to that point, the feasibility of future monolithic liquid crystal display devices for high-definition television will be realized by incorporating the liquid crystal display element pixel unit and the drive circuit into single crystal Si. Can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図1】本実施例により石英基板に貼り合わせたSi単
結晶基板を均一な厚み分布でエッチングしている状態を
示す模式図である。
FIG. 1 is a schematic view showing a state where a Si single crystal substrate bonded to a quartz substrate is etched with a uniform thickness distribution according to the present embodiment.

【符号の説明】[Explanation of symbols]

1 基板 2 石英基板 3 Si単結晶基板 5 平行平板電極 5a 分割電極 6 発光部 7 受光部 8 CPU 9 交流電源 1 substrate 2 Quartz substrate 3 Si single crystal substrate 5 parallel plate electrodes 5a split electrode 6 light emitting part 7 Light receiving part 8 CPU 9 AC power supply

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】石英又はガラス製基板に貼り合わせたSi
単結晶基板をエッチングしてモノリシック液晶表示素子
用基板を製造する方法であって、 該Si単結晶基板に対して複数のゾーンに分割してエッ
チングを施しつつ、各ゾーンの厚みを光学的手段にて検
出し、その検出結果に基づき各ゾーンのエッチング量を
制御するモノリシック液晶表示素子用基板の製造方法。
1. Si bonded to a quartz or glass substrate
A method of manufacturing a substrate for a monolithic liquid crystal display element by etching a single crystal substrate, which comprises dividing the Si single crystal substrate into a plurality of zones and performing etching while using the thickness of each zone as an optical means. And a method for manufacturing a substrate for a monolithic liquid crystal display element, which controls the etching amount of each zone based on the detection result.
【請求項2】前記光学的手段がSi単結晶基板へ向けて
光を発する発光部と、Si単結晶基板からの反射光を捉
える受光部とからなり、該受光部がエッチングされるS
i単結晶基板上の各ゾーンに対応した数の受光素子を有
し、更に前記エッチングを施す手段が、該各ゾーンに対
応した数のドライエッチング用電極を備え、該エッチン
グ用電極が該受光素子にて捉えられた光の強度に応じて
制御される請求項1記載のモノリシック液晶表示素子用
基板の製造方法。
2. The optical means comprises a light emitting portion which emits light toward the Si single crystal substrate and a light receiving portion which catches reflected light from the Si single crystal substrate, and the light receiving portion is etched S
The light-receiving element is provided in the number corresponding to each zone on the i single crystal substrate, and the means for performing the etching is provided with the number of dry etching electrodes corresponding to each zone, and the etching electrode is provided in the light-receiving element. The method for manufacturing a substrate for a monolithic liquid crystal display element according to claim 1, wherein the method is controlled in accordance with the intensity of the light captured by.
JP17416691A 1991-07-15 1991-07-15 Method for manufacturing substrate for monolithic liquid crystal display element Expired - Fee Related JP2815249B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17416691A JP2815249B2 (en) 1991-07-15 1991-07-15 Method for manufacturing substrate for monolithic liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17416691A JP2815249B2 (en) 1991-07-15 1991-07-15 Method for manufacturing substrate for monolithic liquid crystal display element

Publications (2)

Publication Number Publication Date
JPH0517294A true JPH0517294A (en) 1993-01-26
JP2815249B2 JP2815249B2 (en) 1998-10-27

Family

ID=15973861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17416691A Expired - Fee Related JP2815249B2 (en) 1991-07-15 1991-07-15 Method for manufacturing substrate for monolithic liquid crystal display element

Country Status (1)

Country Link
JP (1) JP2815249B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
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US7226114B2 (en) 2004-05-11 2007-06-05 Honda Motor Co., Ltd. Body structure for vehicle having sliding door
JP2009170648A (en) * 2008-01-16 2009-07-30 Disco Abrasive Syst Ltd Plasma etching device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102616516B1 (en) * 2019-03-14 2023-12-26 주식회사 케이씨텍 Apparatus for Treating Substrate and the Method of Treating Substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7226114B2 (en) 2004-05-11 2007-06-05 Honda Motor Co., Ltd. Body structure for vehicle having sliding door
JP2009170648A (en) * 2008-01-16 2009-07-30 Disco Abrasive Syst Ltd Plasma etching device

Also Published As

Publication number Publication date
JP2815249B2 (en) 1998-10-27

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