JP2815249B2 - Method for manufacturing substrate for monolithic liquid crystal display element - Google Patents
Method for manufacturing substrate for monolithic liquid crystal display elementInfo
- Publication number
- JP2815249B2 JP2815249B2 JP17416691A JP17416691A JP2815249B2 JP 2815249 B2 JP2815249 B2 JP 2815249B2 JP 17416691 A JP17416691 A JP 17416691A JP 17416691 A JP17416691 A JP 17416691A JP 2815249 B2 JP2815249 B2 JP 2815249B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- etching
- zone
- liquid crystal
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Drying Of Semiconductors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、モノリシック液晶表示
素子に用いる基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate used for a monolithic liquid crystal display device.
【0002】[0002]
【従来の技術】カラー液晶表示素子は、従来、石英また
はガラス製基板上にポリシリコン膜又はアモルファスS
i膜を堆積した基板が用いられ、その基板上に画素部と
駆動回路部とを形成することによりモノリシック型に作
製されていた。2. Description of the Related Art Conventionally, a color liquid crystal display element has conventionally been formed by forming a polysilicon film or an amorphous silicon film on a quartz or glass substrate.
A substrate on which an i-film is deposited is used, and a pixel portion and a drive circuit portion are formed on the substrate to produce a monolithic type.
【0003】ところが、近年においてはハイビジョン対
応用のカラー液晶表示素子の開発が進められ、そのため
に上記ポリシリコン膜やアモルファスSi膜に代えて、
Si単結晶基板を石英またはガラス製基板に貼り合わせ
た基板が採用されつつある。これは、ポリシリコン膜や
アモルファスSi膜ではトランジスタのチャネル部移動
度がそれぞれ50cm2V-1sec-1、1cm2V-1se
c-1程度と低いが、Si単結晶では前記移動度が著しく
大きいからである。However, in recent years, the development of a color liquid crystal display element for high vision has been promoted, and for that purpose, instead of the above-mentioned polysilicon film and amorphous Si film,
A substrate in which a Si single crystal substrate is bonded to a quartz or glass substrate is being adopted. This is because a polysilicon film or an amorphous Si film channel portion mobility of the transistor, each 50cm 2 V -1 sec -1, 1cm 2 V -1 se
Although it is as low as c −1, the mobility is remarkably large in the Si single crystal.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、Si単
結晶基板をそのままで貼り合わせた基板の場合、そのS
i単結晶基板の厚さムラが大きく、例えば直径4インチ
の基板では厚さ1μmに対して約30〜40%もあり、
表示素子の作製上、大きな障害となっている。そのた
め、厚みが500〜600μmのSi単結晶基板を石英
基板等に貼り合わせたのち、機械研磨又は化学研磨によ
って例えば1μmまで研磨しているが、この方法では厚
さムラを5%以下にはできないため、ハイビジョン表示
素子の実現化に対応できずにいた。However, in the case of a substrate in which a Si single crystal substrate is bonded as it is, the S
The thickness unevenness of the i-single-crystal substrate is large, for example, about 30 to 40% of the thickness of 1 μm for a 4-inch diameter substrate
This is a major obstacle in manufacturing a display element. For this reason, a single crystal silicon substrate having a thickness of 500 to 600 μm is bonded to a quartz substrate or the like and then polished to, for example, 1 μm by mechanical polishing or chemical polishing. However, this method cannot reduce thickness unevenness to 5% or less. Therefore, it has not been possible to cope with the realization of a high-vision display device.
【0005】本発明はこのような従来技術の課題を解決
すべくなされたものであり、Si単結晶基板にエッチン
グを施す工夫をして厚さムラが発生するのを抑制して、
ハイビジョン用モノリシック液晶表示素子の実現性を高
め得るモノリシック液晶表示素子用基板の製造方法を提
供することを目的とする。The present invention has been made in order to solve such problems of the prior art, and it is possible to suppress the occurrence of thickness unevenness by devising etching of a Si single crystal substrate.
It is an object of the present invention to provide a method for manufacturing a substrate for a monolithic liquid crystal display element that can enhance the feasibility of a monolithic liquid crystal display element for high definition television.
【0006】[0006]
【課題を解決するための手段】本発明は、石英又はガラ
ス製基板に貼り合わせたSi単結晶基板をエッチングし
てモノリシック液晶表示素子用基板を製造する方法であ
って、前記Si単結晶基板へ向けて光を1つの発光部か
ら発し、該Si単結晶基板の各ゾーンからのそれぞれの
反射光を該各ゾーンに対応する各受光素子によって検出
し、これらの受光素子の出力に応じて、該各ゾーンに対
応するそれぞれのドライエッチング用電極を制御手段に
よって個別制御し、これによって該各ゾーンのエッチン
グを個別制御しており、そのことにより上記目的を達成
できる。SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a substrate for a monolithic liquid crystal display device by etching a Si single crystal substrate bonded to a quartz or glass substrate. Directs light to one light emitting part
From each zone of the Si single crystal substrate
Reflected light is detected by each light receiving element corresponding to each zone
Then, according to the output of these light receiving elements, each zone is
Each corresponding dry etching electrode as control means
Therefore, the individual control is performed, and thereby, the etching of each zone is performed.
The individual objects are controlled individually, thereby achieving the above object.
【0007】[0007]
【作用】本発明にあっては、石英又はガラス製基板に貼
り合わせたSi単結晶基板に対し、複数のゾーンに分割
してエッチングを施しつつ、各ゾーンの厚みを光学的手
段にて検出し、その検出結果に基づき各ゾーンのエッチ
ング量を制御する。このため、厚いゾーンに対してエッ
チング量を増大させ、薄いゾーンに対してエッチング量
を減少させることにより、Si単結晶基板は各ゾーンに
おいてほぼ均一な厚み分布でエッチングが施されること
となる。According to the present invention, the thickness of each zone is detected by optical means while etching is performed on the Si single crystal substrate bonded to the quartz or glass substrate while being divided into a plurality of zones. The amount of etching in each zone is controlled based on the detection result. For this reason, by increasing the etching amount for the thick zone and decreasing the etching amount for the thin zone, the Si single crystal substrate is etched with a substantially uniform thickness distribution in each zone.
【0008】[0008]
【実施例】以下、本発明の一実施例を説明する。An embodiment of the present invention will be described below.
【0009】図1は本実施例に用いるドライエッチャー
を示す模式図である。このドライエッチャーは、被エッ
チング対象の基板1を保持するステージ4と、基板1に
平行に対向配設した反応性イオンエッチ用の平行平板電
極5と、平行平板電極5の両側に設けられた、例えばレ
ーザ光を発生する発光部6及びその受光部7からなる光
干渉計と、受光部7にて検出された信号を入力し、その
入力信号に基づいて前記平行平板電極5の出力制御を行
うCPU8と、ステージ4と平行平板電極5との間に電
圧を印加する交流電源9とを備える。前記ステージ4に
は、本実施例においては、基板1として石英基板2にS
i単結晶基板3を貼り合わせたものがセットされる。FIG. 1 is a schematic diagram showing a dry etcher used in this embodiment. The dry etcher was provided on both sides of the stage 4 for holding the substrate 1 to be etched, the parallel plate electrode 5 for reactive ion etching disposed in parallel and opposed to the substrate 1, and the parallel plate electrode 5. For example, an optical interferometer including a light emitting section 6 and a light receiving section 7 for generating a laser beam, and a signal detected by the light receiving section 7 are input, and the output of the parallel plate electrode 5 is controlled based on the input signal. The apparatus includes a CPU 8 and an AC power supply 9 for applying a voltage between the stage 4 and the parallel plate electrode 5. In the present embodiment, the stage 4 has a quartz substrate 2 as the substrate 1 and an S
An i-single-crystal substrate 3 is attached.
【0010】前記平行平板電極5は反応性イオンエッチ
用に設けられ、基板1側の表面(この例では底面)には
メッシュ状に分割して多数の分割電極5aが縦横に配設
されている。各分割電極5aはそれぞれ、その下方の基
板1部分をエッチングゾーンとしてエッチングでき、各
分割電極5aに与えられる電圧が前記CPU8にて調整
されることにより、エッチング量の調整が行われる。The parallel plate electrodes 5 are provided for reactive ion etching, and a large number of divided electrodes 5a are vertically and horizontally arranged on the surface (the bottom surface in this example) on the substrate 1 side in a mesh shape. . Each of the divided electrodes 5a can be etched by using a portion of the substrate 1 thereunder as an etching zone, and the amount of etching is adjusted by adjusting the voltage applied to each of the divided electrodes 5a by the CPU 8.
【0011】前記発光部6は、その光照射方向をステー
ジ4に保持された基板1の上表面に向け、基板1の上表
面全域を照射するように設けている。受光部7は、縦横
に多数配設した受光素子を備え、各素子の検出視野を基
板1の上表面に向けている。各素子の検出視野は、前記
分割電極5aにて個別にエッチングされる基板1のエッ
チングゾーンと、1対1で対応するようになしてある。The light emitting section 6 is provided so that the light irradiation direction is directed to the upper surface of the substrate 1 held on the stage 4 so as to irradiate the entire upper surface of the substrate 1. The light receiving section 7 includes a large number of light receiving elements arranged vertically and horizontally, and directs a detection visual field of each element toward the upper surface of the substrate 1. The detection visual field of each element is made to correspond one-to-one with the etching zone of the substrate 1 which is individually etched by the divided electrode 5a.
【0012】各受光素子は、前記発光部6での光強度を
調節して一定値にすることにより、基板1の上側にある
Si単結晶基板3の上表面からの反射光と、その下表面
からの反射光ととの干渉光に基づいて、Si単結晶基板
3の各エッチングゾーンの厚みを検出できる。この検出
された厚み信号はCPU8に与えられる。CPU8は入
力信号に基づいて平坦度を検出し、平行平板電極5をフ
ィードバック制御する。この制御は、エッチング量が過
多となっているエッチングゾーンに対応する分割電極5
aに対しては印加電圧を低くし、過小となっているエッ
チングゾーンに対応する分割電極5aに対しては印加電
圧を高くする。Each light receiving element adjusts the light intensity in the light emitting section 6 to a constant value, so that the light reflected from the upper surface of the Si single crystal substrate 3 on the upper side of the substrate 1 and the lower surface thereof The thickness of each etching zone of Si single crystal substrate 3 can be detected based on the interference light with the reflected light from. The detected thickness signal is given to the CPU 8. The CPU 8 detects the flatness based on the input signal, and performs feedback control of the parallel plate electrode 5. This control is performed for the divided electrodes 5 corresponding to the etching zones where the etching amount is excessive.
The applied voltage is reduced for a, and the applied voltage is increased for the divided electrode 5a corresponding to the etching zone that is too small.
【0013】かかるドライエッチャーによるエッチング
は次のように行う。先ず、石英基板2にSi単結晶基板
3を貼り合わせた基板1を、エッチングを行うSi単結
晶基板3側を平行平板電極5へ向けてステージ4にセッ
トする。この石英基板2は、例えば厚さ約500μm、
直径6インチであり、一方のSi単結晶基板3はこれと
同等の厚さ、直径を有する。なお、Si単結晶基板3は
その厚さがもっと薄いものであっても構わない。The etching by the dry etcher is performed as follows. First, the substrate 1 in which the Si single crystal substrate 3 is bonded to the quartz substrate 2 is set on the stage 4 with the Si single crystal substrate 3 to be etched facing the parallel plate electrode 5. The quartz substrate 2 has a thickness of about 500 μm, for example.
The diameter is 6 inches, and one Si single crystal substrate 3 has the same thickness and diameter. Note that the Si single crystal substrate 3 may have a smaller thickness.
【0014】次いで、交流電源9を通電状態にすると共
に、発光部6、受光部7及びCPU8を動作させ、エッ
チングを開始する。このとき、発光部6から出射される
レーザ光の強度は、レーザ光の一部が基板1の下側の石
英基板2の上表面に達するように定めておく。Next, the AC power supply 9 is turned on, the light emitting unit 6, the light receiving unit 7, and the CPU 8 are operated to start etching. At this time, the intensity of the laser light emitted from the light emitting unit 6 is determined so that a part of the laser light reaches the upper surface of the quartz substrate 2 below the substrate 1.
【0015】これにより、Si単結晶基板3が分割電極
5aにより各エッチングゾーン毎にエッチングされる。
このエッチングのとき、基板1の各エッチングゾーン毎
のエッチング量は、受光部7の対応する各受光素子にて
検出され、この検出信号に基づいてCPU8が上述した
ように分割電極5aへ印加する電圧を制御する。例え
ば、分割電極5aの左から2番目のBにてエッチングさ
れている基板1部分を検出している受光部7の受光素子
bで検知した光強度に基づいて、分割電極5aの左から
2番目のBにフィードバックし、そのBの分割電極5a
に対応するエッチングゾーンのエッチング速度を制御す
る。なお、A〜Hで示す各分割電極5aにおいても、対
応するa〜hで示す受光素子にて検出された信号に基づ
いて同様な制御が行われる。Thus, the Si single crystal substrate 3 is etched for each etching zone by the divided electrode 5a.
At the time of this etching, the etching amount of each etching zone of the substrate 1 is detected by each corresponding light receiving element of the light receiving section 7, and based on this detection signal, the CPU 8 applies the voltage applied to the divided electrode 5a as described above. Control. For example, based on the light intensity detected by the light receiving element b of the light receiving section 7 which detects the portion of the substrate 1 etched at the second B from the left of the split electrode 5a, the second from the left of the split electrode 5a Of the divided electrode 5a of the B
Is controlled in the etching zone corresponding to. In each of the divided electrodes 5a indicated by A to H, similar control is performed based on the signals detected by the corresponding light receiving elements indicated by a to h.
【0016】従って、本実施例においては、石英基板2
に貼り合わせたSi単結晶基板3を均一な厚み分布でエ
ッチングを行うことができ、最終的に所望の厚み、例え
ば1μmにまでエッチングを施したところ、厚みムラを
5%以下に抑制することが可能となった。Therefore, in this embodiment, the quartz substrate 2
Can be etched with a uniform thickness distribution, and finally etched to a desired thickness, for example, 1 μm, to suppress thickness unevenness to 5% or less. It has become possible.
【0017】上記実施例ではSi単結晶基板を石英基板
に貼り合わせた基板を例に挙げて説明しているが、本発
明はこれに限らず、Si単結晶基板をガラス基板に貼り
合わせた基板を対しても適用できることはもちろんであ
る。In the above embodiment, a substrate in which a Si single crystal substrate is bonded to a quartz substrate is described as an example. However, the present invention is not limited to this, and a substrate in which a Si single crystal substrate is bonded to a glass substrate is described. Of course, it can also be applied to
【0018】また、上記実施例では反応性イオンエッチ
によりSi単結晶基板をエッチングするようにしている
が、本発明はこれに限らず、他のエッチング法を用いて
も実施できる。Further, in the above embodiment, the Si single crystal substrate is etched by reactive ion etching. However, the present invention is not limited to this, and other etching methods can be used.
【0019】[0019]
【発明の効果】以上詳述したように本発明による場合に
は、厚みムラを5%以下に抑制することができるので、
それまで用いていたポリシリコンやアモルファスシリコ
ンに代えて、単結晶Siに液晶用表示素子用画素部と駆
動回路とを一体的に作り込むことにより、将来のハイビ
ジョン用モノリシック液晶表示素子の実現性を高めるこ
とができる。As described in detail above, according to the present invention, thickness unevenness can be suppressed to 5% or less.
In place of the polysilicon and amorphous silicon used up to that point, the feasibility of a future HDTV monolithic liquid crystal display device will be realized by integrating the pixel portion for the liquid crystal display device and the drive circuit into single-crystal Si. Can be enhanced.
【図1】本実施例により石英基板に貼り合わせたSi単
結晶基板を均一な厚み分布でエッチングしている状態を
示す模式図である。FIG. 1 is a schematic diagram showing a state in which a Si single crystal substrate bonded to a quartz substrate is etched with a uniform thickness distribution according to the present embodiment.
1 基板 2 石英基板 3 Si単結晶基板 5 平行平板電極 5a 分割電極 6 発光部 7 受光部 8 CPU 9 交流電源 DESCRIPTION OF SYMBOLS 1 Substrate 2 Quartz substrate 3 Si single crystal substrate 5 Parallel plate electrode 5a Split electrode 6 Light emitting part 7 Light receiving part 8 CPU 9 AC power supply
Claims (1)
i単結晶基板をエッチングしてモノリシック液晶表示素
子用基板を製造する方法であって、前記Si単結晶基板へ向けて光を1つの発光部から発
し、該Si単結晶基板の各ゾーンからのそれぞれの反射
光を該各ゾーンに対応する各受光素子によって検出し、
これらの受光素子の出力に応じて、該各ゾーンに対応す
るそれぞれのドライエッチング用電極を制御手段によっ
て個別制御し、これによって該各ゾーンのエッチングを
個別制御する モノリシック液晶表示素子用基板を製造す
る方法。1. S bonded to a quartz or glass substrate
A method for manufacturing a substrate for a monolithic liquid crystal display element by etching an i-single-crystal substrate, wherein light is emitted from one light-emitting portion toward the Si-single-crystal substrate.
And each reflection from each zone of the Si single crystal substrate
Light is detected by each light receiving element corresponding to each zone,
According to the outputs of these light receiving elements,
Control each dry etching electrode.
And individually control the etching of each zone.
A method of manufacturing a substrate for a monolithic liquid crystal display element that is individually controlled .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17416691A JP2815249B2 (en) | 1991-07-15 | 1991-07-15 | Method for manufacturing substrate for monolithic liquid crystal display element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17416691A JP2815249B2 (en) | 1991-07-15 | 1991-07-15 | Method for manufacturing substrate for monolithic liquid crystal display element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0517294A JPH0517294A (en) | 1993-01-26 |
JP2815249B2 true JP2815249B2 (en) | 1998-10-27 |
Family
ID=15973861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17416691A Expired - Fee Related JP2815249B2 (en) | 1991-07-15 | 1991-07-15 | Method for manufacturing substrate for monolithic liquid crystal display element |
Country Status (1)
Country | Link |
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JP (1) | JP2815249B2 (en) |
Cited By (1)
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KR20200109757A (en) * | 2019-03-14 | 2020-09-23 | 주식회사 케이씨텍 | Apparatus for Treating Substrate and the Method of Treating Substrate |
Families Citing this family (2)
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JP4098273B2 (en) | 2004-05-11 | 2008-06-11 | 本田技研工業株式会社 | Body structure of vehicle with sliding door |
JP2009170648A (en) * | 2008-01-16 | 2009-07-30 | Disco Abrasive Syst Ltd | Plasma etching device |
-
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Cited By (2)
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KR20200109757A (en) * | 2019-03-14 | 2020-09-23 | 주식회사 케이씨텍 | Apparatus for Treating Substrate and the Method of Treating Substrate |
KR102616516B1 (en) | 2019-03-14 | 2023-12-26 | 주식회사 케이씨텍 | Apparatus for Treating Substrate and the Method of Treating Substrate |
Also Published As
Publication number | Publication date |
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JPH0517294A (en) | 1993-01-26 |
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