JPH0516795Y2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Field of Industrial Application The present invention relates to a playback device for an electronic still camera, and more particularly to a color signal circuit that converts a playback signal from a magnetic disk into a color non-interlaced signal.

(b) Conventional technology Regarding electronic still cameras, for example, the magazine ``Nikkei Electronics'' published by Nikkei McGraw-Hill, Inc.
"Diameter" described on pages 80 to 85 of "July 2, 1984 issue"
Recording 25 still images on a 47mm floppy disk - standard for magnetic disks for electronic still cameras
is shown.

This magnetic disk is shown in FIG. In FIG. 9, 10 is a magnetic disk rotating at 3600 rpm. This magnetic disk 10 has 52 concentric recording tracks. Furthermore, in Figure 9,
Only two recording tracks 11 and 12 are shown.

With electronic still cameras, this recording track has one
It is specified that the field video signal should be FM modulated and recorded. Therefore, when recording one frame of video consisting of two fields (hereinafter referred to as frame recording), as shown in Figure 9,
The first field (1H
262.5H) is recorded, and the video signal of the second field (262.5H to 525H) is recorded on the next recording track 12.

Also, color difference signals (RY, B-Y) are recorded alternately for each horizontal scanning line (hereinafter referred to as R-Y, B-Y).
When color difference signals exist alternately, it is called line sequential).

A device for converting the signal reproduced from this magnetic disk into a non-interlaced signal is disclosed in Japanese Patent Laid-Open No. 174077/1983.

In this Japanese Patent Application Laid-open No. 59-174077, first and second heads are used which simultaneously reproduce the signals of two tracks. Then, the signals from the first and second heads are converted into double-speed signals by the first and second time-base compression circuits, and a non-interlaced signal is created from the double-speed signals.

By the way, the color difference signal of an electronic still camera is R
-Y color difference signal and B-Y color difference signal are line sequential signals.

Therefore, the horizontal scanning period including the R-Y color difference signal does not include the B-Y color difference signal. Therefore, it is necessary to create and insert this unincluded BY color difference signal from the BY color difference signal during the adjacent horizontal scanning period. In the horizontal scanning period including the R-Y color difference signal, a similar operation is performed for the B-Y color difference signal (hereinafter, the operation of creating and inserting the missing color difference signal is referred to as synchronization).

(c) Problems to be solved by the invention Naturally, this synchronization is also performed during non-interlaced playback. Therefore, during non-interlaced reproduction, the speed of the color color signal (color difference signal) must be doubled, and a new color difference signal must be created for synchronization, making the circuit configuration complicated.

(d) Means for solving the problem The present invention writes a color difference signal over one horizontal scanning period, and repeats the written color difference signal for one horizontal scanning period at about twice the writing speed. This is a color signal circuit including a memory circuit for reading.

(e) Effect The memory circuit repeatedly reads out the written color difference signal for one horizontal scanning period at least twice at double speed. Therefore, one double-speed color difference signal read out repeatedly can be used for synchronizing other horizontal scanning periods.

(F) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 to 8.

FIG. 2 is a diagram schematically showing a non-interlacing device for an electronic still camera. In Figure 2, 1
0 is a magnetic disk. This magnetic disk 10
In this example, a frame video signal is recorded on two tracks for each field. Reference numerals 13 and 14 designate first and second heads for simultaneously reproducing the signals recorded on these two tracks. Incidentally, the first and second heads may be integrally formed by a dual magnetic head. 16 and 18 are high pass filters, 2
0 and 22 are low-pass filters, 24 and 26 are FM demodulation circuits for luminance signals, and 28 and 30 are FM demodulation circuits for color difference signals.

32 and 34 are time-base compression circuits for luminance signals. A selector 36 selectively outputs the double-speed signals from the time axis compression circuits 32 and 34 every 1/2 horizontal scanning period (non-interlaced horizontal period).

40 is a time-base compression circuit for color difference signals, which is the gist of the present invention. This time axis compression circuit 40 is
The color difference signals from the FM demodulation circuits 28 and 30 are input, and double-speed R-Y, BY color-difference signals are always output.

42 is an RGB signal generation circuit. The RGB signal generation circuit 42 generates a double-speed luminance signal and a double-speed R-
Double-speed RGB signals and synchronization signals are created from the Y and B-Y color difference signals.

A time-base compression circuit 40 for color difference signals, which is the gist of the present invention, will be explained with reference to FIG.

40a and 40b are line-sequential color difference signal input terminals. 44 and 46 are analog-to-digital converters (AD) that convert line-sequential color difference signals into digital data.
converter). 48 and 50 are switches, 52 is
This is a 0.5H (1H is one horizontal scanning period) delay circuit.
54 and 56 are double-speed circuits that repeatedly output the input color difference signal twice at twice the speed.
58 and 60 are switches, and 62 and 64 are switching circuits. 66 and 68 are digital-to-analog converters (DA converters), which output R-Y color difference signals and B-Y color difference signals, respectively.

70 is a discrimination circuit. This discrimination circuit 70 has color difference signals Ca input to input terminals 40a and 40b,
Determine the state of Cb. Comparators 72 and 74 compare the level of the color difference signal within the vertical retrace period after nH with the level of the color difference signal after (n+1)H based on the vertical synchronization signal. In other words, R-Y
The color difference signal is FM modulated at 1.2MHz and recorded on the magnetic disk, and the BY color difference signal is FM modulated at 1.3MHz. When this color difference signal is demodulated by the FM demodulator 28 in Fig. 2, as shown in Fig. 4a, R-Y
The clamp levels of the color difference signal and the BY color difference signal are different. Therefore, the comparators 72 and 74 compare the clamp levels during the retrace period, and the comparators 72 and 74
By recognizing the two outputs, the states of the color difference signals Ca and Cb can be determined.

76 is an exclusive OR circuit that compares the outputs from the comparators 72 and 74.

78 is a selection circuit controlled by the output of the exclusive OR circuit 76; This selection circuit 78
is the HP' signal (Fig. 4 e) when a high level signal is input.
(see) is selected and output. Also, this selection circuit 78
is the HP signal (Fig. 4 d) when the low level signal is input.
(see) is selected and output. The HP and HP' signals are generated from the horizontal synchronization signal of the reproduced video signal, or by a reference oscillation circuit that is reset by the vertical synchronization signal of the reproduced video signal.

Note that the output of the comparison circuit 72 causes the switching circuit 6 to
2,64 works. This switching circuit 62 outputs the output of the switch 58 to the DA converter 66 when a high level signal is input from the comparator circuit 72, and outputs the output of the switch 60 to the DA converter 66 when a low level signal is input. . Furthermore, when a high level signal is input from the comparator circuit 72, the switching circuit 64 outputs the output of the switch 60 to the DA converter 68, and when a low level signal is input, the switching circuit 64 outputs the output of the switch 60 to the DA converter 68.
8 is output to the DA converter 68.

FIG. 3 shows an example of the comparator 72,
72a is a latch circuit that latches digital data using a pulse signal (VnH) nH after the vertical synchronization signal (see FIG. 4b). 72b connects the output of the latch circuit 72a and the input digital data;
This is a comparator for comparison, and this comparator outputs a high level signal when the output of the latch circuit 72a is small. 72c is a pulse signal (V(n+1)H) after (n+1)H from the vertical synchronization signal
(See Figure 4c) is a flip-flop that latches the comparator output. The comparator 74 also operates in a similar manner (see f and g in FIG. 4).

The operation of the time axis compression circuit 40 by the discrimination circuit 70 will be explained with reference to FIGS. 5 and 6.

When the signal shown in FIG. 5a is input to the input terminal 40a and the signal shown in FIG. 5b is input to the input terminal 40b, the comparator 72 in FIG. 74 outputs a low level signal. Therefore, the exclusive OR circuit 76 outputs a high level signal. The switches 48 and 50 are controlled by this high level signal, and the signal Cb at the input terminal 40b is input to the speed doubler circuit 56, which outputs the signal shown in FIG. 5e. Further, the signal Ca at the input terminal 40a is input to the 0.5H delay circuit 52 and is
Outputs the signal. This output signal is transmitted to the double speed circuit 54.
The signal shown in FIG. 5d is output.

Further, the selection circuit 78 selects the HP' signal shown in FIG.・G signal is output. Further, the switches 62 and 64 are controlled by the signal from the comparator 72, and the output of the switch 58 is outputted to the RY output terminal 40c via the switch 62 and the DA converter 66. Also, the output of the switch 60 is sent to the switch 64 and the DA converter 68.
The signal is outputted to the BY output terminal 40d via.
Incidentally, FIG. 5h shows a luminance signal corresponding to this double speed color difference signal.

Further, when the signal shown in FIG. 6a is input to the input terminal 40a and the signal shown in FIG. 6b is input to the input terminal 40b, high level signals are output from the comparators 72 and 74. The double speed circuit 54 outputs the signal shown in FIG. 6 d, and the double speed circuit 56 outputs the signal shown in FIG. 6 e. Furthermore, the selection circuit 78 outputs the HP signal shown in FIG. 4d in response to the low level signal output from the exclusive OR circuit 76, and this signal controls the switches 58 and 60, causing the switch 58 to output the signal shown in FIG. 6f. The output switch 60 outputs the signal shown in FIG. 6g. R-Y output terminal 40
c outputs the signal shown in Fig. 6 f, and the B-Y output terminal 4
0d outputs the signal shown in FIG. 6g.

Figure 7 shows a double speed circuit, 90,9
1 is a memory that stores color difference signals for 1H period.
Reference numeral 92 denotes an input terminal to which a signal synchronized with the horizontal synchronization component of the input color difference signal is input. 93 is
This is a switch that is switched in response to a signal from an input terminal 92, and the states of the memories 90 and 91 change in conjunction with this switch 93. In other words, switch 9
3, when one of the memories is connected to the input terminal 54a, that memory enters the write mode. Note that the switch 94 also operates in conjunction with the switch 93 and is connected to the memory in read mode.
A write address counter 95 determines the write address, and is reset by the horizontal synchronization signal and counted up by the 1/2 clock signal. A read address counter 96 determines a read address, and is counted up by a clock signal. This read address counter 96 is controlled by a 1/2 horizontal synchronization signal (non-interlaced horizontal synchronization signal).
It will be reset.

That is, when a line-sequential color difference signal as shown in FIG. 8a is input from the input terminal 54a, the memory 9
0 and 91 operate as shown in FIGS. 8b and 8c. Then, the switch 94 outputs the signal shown in FIG. 8d.

The operation of the above circuit will be explained.

The color difference signal component of the FM modulated wave is extracted from the signal reproduced from the magnetic disk 10 of FIG. 2 via the first and second heads 13 and 14 by low-pass filters 20 and 22. This signal is FM demodulated by the FM demodulation circuits 28 and 30 into the signals shown in FIG. 5a and b.

The FM demodulated line-sequential color difference signals are converted into digital data by AD converters 44 and 46 shown in FIG. 1, respectively. The discrimination circuit 70 outputs a signal to operate the exclusive OR circuit 76. Then,
The switches 48 and 50 are controlled, and the output of the AD converter 44 is sent to the double speed circuit 5 via the 0.5H delay circuit 52.
4 is input. The input signal to the speed doubler circuit 54 is as shown in FIG. 5c. Further, the output of the AD converter 46 is input to a speed doubler circuit 56. The input signal to this speed doubler circuit 56 is as shown in FIG. 5b.

Therefore, the outputs from the two speed-doubling circuits 54 and 56 are as shown in FIG. 5d.

This signal (FIG. 5d, e) is then output to switches 58 and 60. switch 58,60
is controlled by the HP signal selected by the selection circuit 78 (FIG. 4e). With this control, the switch 58 outputs the digital data of the R-Y color difference signal (see FIG. 5 f), and the switch 60 outputs the digital data of the B-Y color difference signal (see FIG. 5 g). . Therefore, the DA converter 66,6
8 outputs an RY color difference signal and a B-Y color difference signal, respectively.

This double-speed color difference signal (FIG. 5f, g) is inputted to the RGB signal generation circuit 42 together with a separately generated double-speed luminance signal (see FIG. 5h), and the double-speed (non-interlaced) RGB signal is input to the RGB signal generation circuit 42. and outputs a synchronization signal.

(g) Effects of the invention As described above, in the invention, the same color difference signal is read out twice in the time-base compression circuit. Therefore, one portion of this double-speed color difference signal is used as a color difference signal corresponding to the luminance signal reproduced from the same head, and the remaining one portion of this double-speed color difference signal is used to reproduce the luminance signal reproduced from another head. It can be used as a color difference signal corresponding to the signal.

In other words, it is useful to be able to efficiently double and synchronize line-sequential color difference signals at the same time using the time-base compression circuit.

[Brief explanation of the drawing]

1 to 8 relate to an embodiment of the present invention,
Figure 1 is a diagram of the time base compression circuit, Figure 2 is a diagram of the non-interlaced playback device, Figure 3 is a diagram of the comparison circuit,
Figure 4 is a diagram for explaining the operation of the comparison circuit, Figures 5 and 6 are diagrams for explaining the operation, and Figure 7 is a diagram for explaining the operation.
This figure is a diagram of a double speed circuit, and FIG. 8 is a diagram for explaining the operation of the double speed circuit. FIG. 9 is a diagram of a magnetic disk. 10... Magnetic disk, 13, 14... Head (first and second head), 40... Time axis compression circuit, 9
0,91...Memory (memory circuit).

Claims (1)

[Claims for Utility Model Registration] A magnetic disk non-interlaced playback device in which frame video signals including line-sequential R-Y color difference signals and B-Y color difference signals are recorded in two concentric tracks, one field each. A color signal circuit comprising: first and second heads for simultaneously reproducing the color difference signals respectively recorded on the two tracks; and a time axis compression circuit for doubling the speed of the color difference signals. , the time axis compression circuit includes a delay circuit that delays one of the line-sequential color difference signals reproduced by the first and second heads by 0.5H, and a delay circuit that delays the color difference signal from the delay circuit by twice as much. a first double-speed circuit that repeatedly outputs the other color difference signal of the respective line-sequential color difference signals twice at twice the speed; 1 Select and input the output from the second double speed circuit, output the same R-Y color difference signal at double speed from one output terminal twice each time, and output the same B-Y color difference signal at double speed from the other output terminal. 1. A color signal circuit comprising: a switch that repeatedly outputs twice each time.