JPH05167957A - Driving circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To enable the zoom display magnifying pictures 4/3 times in the vertical direction with simple configuration. CONSTITUTION:An output terminal of a Y driver 14A is connected with gate lines Y1, Y3,... and an output terminal of a Y driver 14B is connected to gate lines Y2, Y4,... An output terminal of the Y driver 14C is connected with gate lines Y1, Y5,... at every four lines and an output terminal of a Y driver 14D is connected with gate lines Y2, Y6,... at every four lines. Thus, for example, the first three of the eight gate lines, the next two, then the last three can be turned on simultaneously, and the 8-line picture elements can be driven in three horizontal periods. In short, the zoom display magnifying pictures 4/3 times in the vertical direction is enabled for 2-line simultaneous write driving.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit of a liquid crystal display device, and more particularly to a drive circuit of a liquid crystal display device suitable for a device having a zoom display function for enlarging in a vertical direction.

[0002]

2. Description of the Related Art In recent years, display devices using liquid crystals have become widespread. For example, a pocket liquid crystal television receiver, a laptop computer display device, a liquid crystal projector, and the like have been commercialized. In particular, liquid crystal projectors are expected to be used for high-definition televisions because they can easily have a large screen.

FIG. 7 is an explanatory view showing a liquid crystal projector using such a liquid crystal panel.

A high frequency (RF) signal induced in the antenna 1 is given to the tuner 2 to demodulate a signal of a predetermined channel. The demodulated video signal is subjected to video processing in the video signal processing circuit 3, amplified, and then supplied to the liquid crystal module 4. The liquid crystal module 4 has a large number of vertically and horizontally divided pixels, and a liquid crystal (not shown) of the liquid crystal module 4 is controlled between a transmission state and a light shielding state by an applied voltage supplied to an electrode corresponding to each pixel. .. By supplying the video signal from the video signal processing circuit 3 as the applied voltage,
The transparency of each pixel is based on the video signal, and the liquid crystal module 4 can display a video.

On the other hand, the light emitted from the light source 5 is condensed by the reflector 6 and is incident on the liquid crystal module 4. As the light source 5, a discharge lamp such as a metal halide having high efficiency, high brightness and high color rendering properties is adopted. The light flux from the reflector 6 passes according to the transparency (transmittance) of each pixel of the liquid crystal module 4, and is emitted as image light. The transmitted light is enlarged and projected on the screen 8 by the projection lens 7. By the way, in the liquid crystal projector, there are a single plate type using one liquid crystal module and a three plate type using three liquid crystal modules. The single plate type has a simple structure and can be reduced in cost. However, at present, the resolution of the liquid crystal module is not sufficient, and if a single-plate type color filter is adopted for colorization, the resolution will be deteriorated. For this reason, the 3-plate type is now the mainstream. In a 3-panel liquid crystal projector, a thin film transistor (hereinafter referred to as a TFT) is provided for each pixel.
An active matrix type monochrome liquid crystal module having such switching elements is adopted.

FIG. 8 is a block diagram showing a liquid crystal display device using this type of liquid crystal module.

The video signal input through the input terminal 11 is applied to the polarity inverting circuit 12. The polarity reversing circuit 12 has a predetermined period, for example, a field period, in order to prevent deterioration of the liquid crystal.
The video signal is inverted at the frame period or the horizontal scanning period and output to the liquid crystal module 4. The liquid crystal module 4 is composed of an X driver 13, a Y driver 14 and a display unit 16.

The X driver 13 inputs the video signal from the polarity reversing circuit 12, performs sampling and holding, and the data line of the TFT arranged in each pixel of the display section 16 of the liquid crystal module 4.
Output signal to 17. Further, the Y driver 14 supplies a gate signal to each of the gate lines Y1, Y2, ... Of the liquid crystal module 4. The display unit 16 has pixels arranged in a matrix,
Each pixel is driven based on the signal supplied to each data line 17 and the gate lines Y1, Y2, ...

FIG. 9 is an explanatory diagram showing a specific configuration of the X driver 13 and the display section 16 of the liquid crystal module 4.

The display section 16 is composed of pixels arranged in a matrix. TFT18 is provided in each pixel, and each T
The gate of FT18 is connected to each gate line Y1, Y2, ...
The drain is connected to each data line 17, and the source is the transparent electrode 21.
Connected to. A liquid crystal 20 such as twisted nematic is sealed between the transparent electrode 18 and the common electrode 22. In addition,
An additional capacitor 19 for stably maintaining the pixel potential is connected between the pixel electrode 21 and the common electrode 22. The TFT 18 is turned on by a high-level (hereinafter referred to as "H") gate signal (hereinafter also referred to as an "on pulse") given to each gate line Y1, Y2, ... By the Y driver 14, and the video signal from the data line 17 is transparent electrode. Give to 21. In this way, each liquid crystal 20 between the transparent electrode 21 and the common electrode 22 is driven.

The X drivers 13 are connected in cascade in a number corresponding to the number of horizontal pixels of the display section 16. For example, if the number of pixels in the horizontal direction of the display unit is 750 and the X driver 13 is for driving 150 pixels, five sets of X drivers 13 are used.

When the start pulse STH indicating the start of the horizontal display period is supplied, the shift register 23 sequentially turns on from the first bit at a timing synchronized with the clock CLK and outputs an on pulse. When the on-pulse shifts to the last bit, the shift register 23 generates a carry-out and the start pulse S is sent to the X driver 13 in the next stage.
Supply as TH. The clock CLK is displayed on the display unit 16
The frequency is set based on the number of pixels in the horizontal direction. For example, when the number of pixels of the display unit 16 is 750 and one horizontal effective scanning period is 50 μsec, the frequency of the clock CLK is 1
Set to 5 MHz.

The level converter 24 amplifies the ON pulse of the shift register 23 and outputs it to the sample hold circuit 25. The sample hold circuit 25 samples and holds the video signal Sin supplied from the polarity inverting circuit 12 at the timing of the on-pulse from the level converter 24.
As a result, the sample hold circuit 25 holds the video signal Sin corresponding to the pixels of one line of the display section 16 during one horizontal effective scanning period, and functions as a line memory.

The output of the sample hold circuit 25 is supplied to the buffer driver 26. The buffer driver 26 amplifies the output of the sample hold circuit 25 at the timing of the output instruction signal OE and outputs it to each data line 17 of the display section 16. In addition,
The output instruction signal OE is turned on during the blanking period of the video signal Sin. On the other hand, the Y driver 14 sequentially supplies a gate signal to each of the gate lines Y1, Y2, .... This gives X
The video signal supplied from the driver 13 via the data line 17 is the T signal connected to the gate line to which the ON pulse is supplied.
Only supplied to FT18.

FIG. 10 is a block diagram showing the Y driver 14 in detail. Further, FIG. 11 is a timing chart for explaining the scanning method. Figure 11 (a) shows the input terminal
11 shows a video signal to be input, and FIG. 11B shows a start pulse ST input to the shift register 27 of the Y driver 14.
11C shows a clock YCLK input to the shift register 27, FIGS. 11D to 11G show gate signals supplied to the gate lines Y1 to Y4, and FIG.
1 (h) indicates an output instruction signal OE given to the X driver 13.

The Y driver 14 employs a two-line simultaneous write scan for writing signals to all pixels in one field period. That is, when the vertical blanking period of the video signal shown in FIG. 11A ends and the start pulse STV (FIG. 11B) indicating the display start timing in the vertical direction is input to the shift register 27, T1 and T2 are "H"
To The shift register 27 shifts the terminals to be set to "H" by the clock YCLK generated in one horizontal display period so that the terminals T3, T4, terminals T5, T6, terminal T7,
Turn on T8, ... in that order. The terminals T1, T2, ... Are connected to the gate lines Y1, Y2, ... Via the level converter 28 and the buffer driver 29, respectively.

The level of the pulse from the shift register 27 is 0 to 5V, and the level converter 28 outputs this pulse to T
About 0 to drive the gate lines Y1, Y2, ... Of the FT18
It is converted to a signal level of 30V and given to the buffer driver 29. The buffer driver 29 supplies on-pulses to the gate lines Y1, Y2, ... And drives the pixels of each line of the display section 16.

The gate lines Y1, Y2, ...
At the same time as E (Fig. 11 (h)), it becomes "H" (Fig. 11).
(D), (e)). When the gate signal is supplied to the gate lines Y1 and Y2 in the first one horizontal effective scanning period of the predetermined field period, the TFTs 18 in the first and second columns of the display section 16 are turned on, and the video signal from the X driver 13 is transmitted. The liquid crystal 20 of the first and second lines is driven by being applied to each data line 17. In this case, all gate lines except the gate lines Y1 and Y2 are off.

In the next one horizontal effective scanning period, FIG.
As shown in (f) and (g), an ON pulse is supplied to the gate lines Y3 and Y4 to turn on the TFTs 18 in the third and fourth columns. Thereafter, similarly, the Y driver 14 simultaneously supplies ON pulses to two sets of gate lines in synchronization with the timing of output from the X driver 13, sequentially shifts ON pulses in one horizontal period, and simultaneously drives the TFTs 18 of two lines. Video signals are written in all pixels in one field period.

By the way, as described above, when two gate lines are simultaneously turned on in one horizontal scanning period and signals are simultaneously written into pixels on two lines, the resolution of the display screen is reduced.
It is half the number of 16 vertical pixels. Therefore, a method of shifting the set of gate lines that are turned on simultaneously in the odd field and the even field by one gate line may be adopted.

FIG. 12 is an explanatory diagram for explaining this scanning method. FIG. 12A shows an odd field and FIG. 12B shows an even field.

In the odd field, FIG.
, The gate lines Y1 and Y1 in the first horizontal scanning period
2 (hatched portion) is turned on at the same time, and gate lines Y3 and Y4 are turned on at the same time in the next horizontal scanning period. Thereafter, similarly, the gate lines Y5 and Y6 (hatched portions) and the gate lines Y7, Y8, ... Are simultaneously turned on. On the other hand, in the even field, as shown in FIG. 12B, the gate lines Y2 and Y3 (hatched portions) are simultaneously turned on in the first horizontal scanning period, and the gate lines Y4 and Y5 are simultaneously turned on in the next horizontal scanning period. To do. Thereafter, similarly, gate lines Y6, Y7 (hatched portions), gate lines Y8, Y
Turn on at the same time with a group of 9 ,. In this way, the gate lines that are turned on simultaneously in the odd field and the even field are shifted. As a result, display close to interlaced scanning is possible, and vertical resolution can be improved.

FIG. 13 is an explanatory diagram showing a drive circuit of a conventional liquid crystal display device using two Y drivers. 14 is a timing chart for explaining the operation, FIG. 14 (a) shows a video signal, FIG. 14 (b) shows an output instruction signal OE, and FIG. 14 (c) shows an odd field. Start pulse STV1, STV2, clock YC
LK1 and YCLK2 and gate signals of the gate lines Y1 to Y4 are shown. FIG. 14D shows even field start pulses STV1 and STV2 and a clock YCLK.
1, YCLK2 and the gate signals of the gate lines Y1 to Y4 are shown.

The configuration of the Y drivers 14A and 14B is the Y driver.
The output terminal of the Y driver 14A is connected to the odd-numbered gate lines Y1, Y3, Y5, ...
The output terminal of B has even-numbered gate lines Y2, Y4, Y6, ...
Connect to. Start pulse STV for Y driver 14A
1 and a clock YCLK1 are given, and a start pulse STV2 and a clock YCLK2 are given to the Y driver 14B.

In the odd field, start pulses STV1 and STV2 are simultaneously input to the shift registers in the Y drivers 14A and 14B at the start of display after vertical blanking (FIG. 14 (c)). This allows the Y driver
As shown in FIG. 14C, 14A and 14B supply the gate signal of "H" to the gate lines Y1 and Y2 respectively connected to the output ends at the end. Horizontal cycle clock YCLK1,
2 supplies it to the shift register in the Y drivers 14A and 14B to shift the output terminal to be turned on. In this way, in the next horizontal period, the gate signals of "H" are supplied to the gate lines Y3 and Y4 connected to the next output terminals of the Y drivers 14A and 14B. After that, the same operation is repeated to perform the same scanning as in FIG.

On the other hand, in the even field, the start pulse STV2 is generated with a delay of one horizontal period from the generation timing of the start pulse STV1 (FIG. 14).
(D)). Therefore, at the start timing of the vertical scanning period, as shown in FIG. 14D, the ON pulse is supplied only to the gate line Y1 connected to the output terminal at the end of the Y driver 14A. The Y driver 14A has a clock Y at a horizontal cycle.
When CLK1 is input, the on-pulse is sequentially shifted,
On-pulses are sequentially supplied to the gate lines Y3, Y5, ....
As shown in FIG. 14D, the Y driver 14B is supplied with the pulse STV2 in the second horizontal period from the start of the vertical scanning period and supplies the "H" gate signal to the gate line Y2. Next, the output terminal for outputting the gate signal of "H" is sequentially shifted by the clock YCLK2 of the horizontal cycle, and the on-pulse is output in the order of the gate lines Y4, Y6, .... After all, in the even field, the gate lines Y2, Y3,
The gate lines Y4, Y5, ... Are turned on at the same time. In this way, scanning by the scanning method of FIG. 12 becomes possible.

By the way, in recent years, a high-definition television system has been developed, and its practical application is approaching. In Japan, a high definition system led by NHK (Japan Broadcasting Corporation) will be adopted as a high-definition television system. High-definition broadcasting has higher definition and higher image quality than the current NTSC television system, and displays on a horizontally wide display screen. FIG. 15 is an explanatory diagram showing the aspect ratio of the display screen, and FIG. 15A shows a high-definition video.
(B) shows an NTSC image. As shown in FIG. 15, the aspect ratio of NTSC video is 4: 3, and the aspect ratio of high-definition video is 16: 9, which is wider than that of NTSC video.

Currently, NHK is performing a trial broadcast of high-definition broadcasts, and the main broadcast is scheduled to start in the future. In the early stage of the diffusion of high-definition systems, NTSC equipment and high-definition equipment coexist. Therefore, it is necessary to consider compatibility between high-definition broadcasting and NTSC broadcasting. For example, a down-converter that converts the high-definition system into the NTSC system can be adopted so that the device for NTSC can receive the high-definition signal. Conceivable. In addition, among NTSC images, horizontally long images are increasing in image software such as video discs or laser discs. Therefore, in the future, it is expected that horizontal images such as high-definition images will be displayed on the screen of the NTSC standard.

FIG. 16 is an explanatory diagram for explaining the display when a wide aspect ratio image is displayed on the NTSC standard display screen. FIG. 16 (a) shows the letterbox display and FIG. 16 (b). Indicates a zoom display.

Since the aspect ratio of the image and the aspect ratio of the display screen are different, it is not possible to display the entire high-definition image on the entire display screen without distortion. FIG.
16A shows a letterbox display. In this letterbox display, as shown in FIG. 16A, a mask portion 32 (broken line portion) is formed above and below a display screen 31 having an aspect ratio of 4: 3. ) Is set and the aspect ratio is 16:
The video signals of 9 are displayed in the central portion 33 of the screen. The letterbox display has the advantage of being able to display all video information, but the display area is only the central portion 33, and some viewers may feel uncomfortable with the upper and lower mask portions 32 being unnatural. In addition, since the image is not displayed on the entire screen, the image becomes small and difficult to see on a relatively small display screen such as a liquid crystal panel.

Therefore, the zoom display shown in FIG. 16 (b) may be adopted. In FIG. 16B, FIG.
The central portion 33 of the central portion 33 has an enlarged aspect ratio of 4: 3 so as to be displayed in the entire area of the display screen 31 having an aspect ratio of 4: 3. In this zoom display, an image can be displayed on the entire screen, and a powerful and natural image screen can be obtained. However, the left and right parts (broken line parts) of the image are not displayed, and part of the image information is lost.

As described above, the letter box display and the zoom display have advantages and disadvantages, and both display methods are selectively used according to the video content and the taste of the viewer.

FIG. 17 is a block diagram showing a drive circuit of a conventional liquid crystal display device capable of zoom display.

In a display device using a CRT (cathode ray tube), it is possible to easily expand the horizontal and vertical amplitudes by controlling the deflection system, for example. On the other hand, in a liquid crystal display device, digital processing such as signal interpolation is performed in order to perform a fractional (4/3) zoom in the vertical direction.

The video signal input through the input terminal 11 is given to the zoom circuit 35. The zoom circuit 35 temporally expands the input video signal and supplies it to the polarity inversion circuit 12, and also performs signal interpolation in the vertical direction. For example, the zoom circuit 35 stores video signals for several lines,
A predetermined coefficient is given to each horizontal line and added, thereby creating a new horizontal line and performing interpolation. As a result, the video signal is expanded 4/3 times in the vertical direction.

The polarity reversing circuit 12 inverts the polarity of the video signal at a field cycle, a frame cycle, a horizontal scanning cycle, etc., and outputs it to the X driver 13 of the liquid crystal module 36. The X driver 13 samples and holds the input signal, and outputs the data line to the drain of the TFT that constitutes each pixel of the display unit 16.
Supply signal via 17. In this case, the phase of the start pulse STH supplied to the X driver 13 is shifted according to the horizontal zoom amount. Y driver 14A, 14
B is a gate of the TFT of the display section 16 to the gate lines Y1, Y2,
Supply the gate signal via. The video signal is vertically multiplied by 4/3 by interpolation, and the image on the display screen is displayed by being enlarged by 4/3 times in the vertical direction. In this way, the video is zoomed in the horizontal and vertical directions to display a wide image with an aspect ratio of 16: 9 on a screen with an aspect ratio of 4: 3.

Thus, in the vertical direction, a fractional multiple (4/3)
It is extremely difficult to perform zoom display by analog signal processing. Therefore, the zoom circuit 35 and the like are provided to perform complicated digital signal processing such as signal interpolation. However, the zoom circuit 35 has a relatively complicated circuit configuration, which increases the circuit scale and the cost. In particular, since a three-plate type liquid crystal projector uses three liquid crystal modules, three sets of digital signal processing circuits having complicated circuit configurations are required, and the circuit scale is remarkably increased.

[0038]

As described above, in the drive circuit of the above-mentioned conventional liquid crystal display device, it is necessary to perform digital signal processing in order to enable zoom display, and the circuit scale is extremely increased. There was a problem that it would end up.

It is an object of the present invention to provide a drive circuit for a liquid crystal display device capable of performing zoom display with a relatively simple circuit structure.

[0040]

In a drive circuit of a liquid crystal display device according to the present invention, a pixel is formed at each intersection of a plurality of data lines and a plurality of gate lines arranged in a grid and is supplied to the gate line. One of a plurality of gate lines, a liquid crystal display unit that drives the pixels by an on-pulse and a pixel signal supplied to the data lines, a data line drive circuit that supplies pixel signals to the plurality of data lines in a horizontal cycle, In the 3 (n-1) + 1th horizontal scanning period (n is a natural number) of the field, the 8 (n-1) +1, 8 (n-1) +2 and 8th
The (n-1) + 3rd gate line is simultaneously supplied with the ON pulse, and the 3 (n-1) + 2nd horizontal scanning period
The (n-1) + 4th and 8th (n-1) + 5th gate lines are simultaneously supplied with on-pulses, and the 8 (n-1) + 6th and the (n-1) + 6th gate lines are supplied during the 3 (n-1) + 3rd horizontal scanning period. 8 (n-1)
An on-pulse is simultaneously supplied to the + 7th and 8th (n-1) + 8th gate lines, and 3 (n-) of the other field is supplied.
1) An ON pulse is simultaneously supplied to the 8th (n-1) th and 8th (n-1) + 1th gate lines in the + 1st horizontal scanning period, and in the 3 (n-1) + 2nd horizontal scanning period. Is the 8th
(N-1) +2, 8th (n-1) +3 and 8th (n-)
1) Supply ON pulse to + 4th gate line at the same time,
8 (n-) during the 3 (n-1) + th horizontal scanning period
1) +5, 8th (n-1) +6 and 8th (n-1) +7
And a gate line driving circuit for simultaneously supplying an ON pulse to the second gate line.

[0041]

In the present invention, the liquid crystal display section is configured such that the gate line driving circuit supplies an ON pulse to each gate line, the data line driving circuit supplies a pixel signal to each data line, and the liquid crystal display unit is formed at the intersection of the data line and the gate line. Drive the selected pixel. The gate line driving circuit simultaneously turns on the first three of the predetermined eight gate lines in the first horizontal scanning period of the predetermined three horizontal periods of one field, and the next two in the next horizontal scanning period. Gate lines are turned on at the same time, and the last three gate lines are turned on at the same time in the next horizontal scanning period. Therefore, eight gate lines are driven in three horizontal scanning periods, and the image displayed on the liquid crystal display unit is magnified 4/3 times in the vertical direction with respect to the two-line simultaneous writing drive. The gate line drive circuit simultaneously turns on a set of gate lines different from one field in the other field, thereby improving the vertical resolution.

[0042]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a drive circuit of a liquid crystal display device according to the present invention. In FIG. 1, the same components as those in FIG. 17 are designated by the same reference numerals.

First, the operating principle in the zoom display mode will be described.

In the letterbox display, as described above, the two gate lines are simultaneously turned on in one horizontal scanning period, and the two-line simultaneous write drive for simultaneously writing signals to the pixels of two lines is performed. In this case, 3
The number of lines driven in the horizontal period is six. In the zoom display mode of this embodiment, three gate lines are simultaneously turned on in a predetermined horizontal period, and two gate lines are simultaneously turned on in the next horizontal period. Further, in the next horizontal period, three gate lines are simultaneously turned on (hereinafter, 3-2
-3 drive system). That is, in this method, eight lines of pixels are driven in three horizontal scanning periods. Therefore, in the letterbox display mode and the zoom display mode, the ratio of the number of drive gate lines in the same period is 6: 8 =
The ratio is 3: 4, which is equal to the enlargement ratio of zoom display to letterbox display. That is, by adopting the 3-2-3 driving method, the expansion ratio in the vertical direction of the display screen is increased to 4/3 times and zoom display is possible without performing digital signal processing.

In FIG. 1, the video signal input through the input terminal 11 is applied to the polarity inverting circuit 12. Polarity inversion circuit
Reference numeral 12 inverts a video signal at a predetermined cycle, for example, a field cycle, a frame cycle or a horizontal scanning cycle, and outputs the video signal to the liquid crystal module 41. Liquid crystal module 41 is X driver 1
3, Y drivers 14A to 14D and a display unit 16 are used. The display unit 16 has pixels arranged in a matrix, and a TFT (not shown) is formed in each pixel,
The liquid crystal of each pixel is driven by the FT to display a screen.
The display unit 16 has a number of data lines according to the number of pixels in the horizontal direction and gate lines Y1, Y2, ... According to the number of pixels in the vertical direction, and the drains of the TFTs in the column direction are connected to the data lines. The gates of the TFTs in the row direction are gate lines Y1 and Y2.
,,. The display unit 16 drives the TFTs by the video signals supplied to the respective data lines and the gate signals supplied to the respective gate lines Y1, Y2, ... to control the state of the liquid crystal.

The X driver 13 has an output terminal corresponding to the data line, receives the video signal from the polarity reversing circuit 12, performs sampling and holding, and outputs from the output terminals to the display unit 16 at the timing of the output instruction signal OE. The video signal is supplied to the data line.

In this embodiment, four Y drivers 14 are used.
The gate lines Y1, Y2, A, 14B, 14C and 14D are
Is supplying the gate signal to. Y driver 14A to 14
D outputs a gate signal of "H" from an output terminal according to start pulses STV1 to STV4 indicating display start timings in the vertical direction, respectively, and shifts an output terminal for outputting a gate signal of "H" according to clocks YCLK1 to YCLK4, respectively. .. The output terminals of the Y driver 14A are connected to the gate lines Y1, Y3, Y5, ... Of the display section 16, and the output terminals of the Y driver 14B are connected to the gate lines Y2, Y of the display section 16.
Connect to 4, Y6, .... Furthermore, in this embodiment,
Each output terminal of Y driver 14C has four gate lines Y1
, Y5, Y9, Y13, ..., and each output terminal of the Y driver 14D has four gate lines Y2, Y6, Y10, Y.
Connect to 14, Y18, .... It should be noted that only the Y drivers 14A and 14B are in operation during normal two-line simultaneous write driving, and all of the Y drivers 14A to 14D are in operation during zoom display.

FIG. 2 is a block diagram showing a specific configuration of the Y drivers 14A to 14D shown in FIG. 2A to 2D show Y drivers 14A to 14D, respectively.

The Y driver 14A comprises a shift register 42A, a level converter 43A and a buffer driver 44A. In the zoom display mode, the shift register 42A has a start pulse S indicating the start of the vertical display period.
When TV1 is input, first, for example, the terminal SFTA2 is turned on (“H”) in synchronization with the clock pulse YCLK1.
To Next, a clock pulse YC generated in one horizontal cycle
When LK1 is input, the next terminal SFTA3 is turned on. Further, the terminal SFTA4 is turned on by the next clock pulse YCLK1. Next clock pulse YCLK
When 1 is input, the shift register 42A causes the terminal SFTA
Turn on 6. After that, similarly, the shift register 42A repeats the shift of the terminal to be turned on in three horizontal cycles. That is, the shift register 42A repeats a shift of 3 horizontal cycles consisting of two 1-bit shifts and one 2-bit shift, and outputs an "H" signal to the level converter 43A.

The level converter 43A is a shift register 42.
The pulse from A is converted into a signal level of about 0 to 30 V necessary for driving the gate lines Y1, Y2, ... Of the display section 16 and given to the buffer driver 44A. The buffer driver 44A supplies a "H" on-pulse to the gate lines Y1, Y2, ... To drive the pixels on each line of the display section 16. Shift register
42A terminals SFTA1, SFTA2, ... Are gate lines Y
, Y3, ..., For example, on-pulses are supplied in order of the gate lines Y3, Y5, Y7, Y11, Y13, Y15, ... In one horizontal cycle. The start pulse STV1
Depending on the setting of, for example, the gate line Y3
, Y7, Y9, Y11, Y15, Y17, ...

The configuration of the Y drivers 14B to 14D is similar to that of the Y driver 14A, and each has a shift register 42B, a shift register 42C or a shift register 42D, and a level converter 43B, a level converter 43C or a level converter 43D. In addition, it has a buffer driver 44B, a buffer driver 44C or a buffer driver 44D. The configurations of the level converters 43B to 43D and the buffer drivers 44B to 44D are similar to those of the level converter 43A and the buffer driver 44A, respectively.

The shift register 42B of the Y driver 14B is
When the start pulse STV2 is input in the zoom display mode, for example, the terminal SFTB1 at the end is turned on in synchronization with the clock pulse YCLK2. Then
Each time the clock pulse YCLK2 is input, the terminals to be turned on are SFTB2, SFTB4, SFTB5, SFT.
B6, SFTB8, SFTB9, SFTB10, SFT
B12, ... are shifted in this order. That is, similarly to the shift register 42A, the shift register 42B also employs a shift of three horizontal periods consisting of two 1-bit shifts and one 2-bit shift to shift the terminal to be turned on. Terminals SFTB1 and SFTB of shift register 42B
2, ... Corresponds to the gate lines Y2, Y4 ,.
The Y driver 14B, for example, uses the gate line Y2 in one horizontal cycle.
, Y4, Y8, Y10, Y12, Y16, ... Depending on the setting of the start pulse STV2, for example, the gate lines Y4, Y6, Y8, Y12, Y
It is also possible to output on-pulses in the order of 14, Y16, ....

The shift register 42C of the Y driver 14C is
In the zoom display mode, when the start pulse STV3 is input, for example, the terminal SFTC1 is turned on in synchronization with the clock pulse YCLK3. Next, clock Y
Every time 3 pulses of CLK3 are input, the terminal SFTC3,
The terminals to be set to "H" are shifted in the order of SFTC5, SFTC7, .... That is, the shift register 42C shifts the terminal to be turned on by 2 bits in 3 horizontal cycles. The terminals SFTC1, SFTC2, ... Of the shift register 42C correspond to the gate lines Y1, Y5, Y9 ,.
The driver 14C uses, for example, a gate line Y1,
ON pulses are output in the order of Y9, Y17, .... By setting the start pulse STV3, the gate line that first supplies the ON pulse and its timing can be appropriately adjusted.

The shift register 42D of the Y driver 14D is
In the zoom display mode, when the start pulse STV4 is input, the terminal SFTD2 is turned on in synchronization with the clock pulse YCLK4. Next, clock YCLK3
Each time 3 pulses are input, the terminals SFTD4, SFTD
The terminals to be set to "H" are shifted in the order of 6, SFTD8, .... That is, the shift register 42D shifts the terminal to be turned on in 3 horizontal cycles by 2 bits. The terminals SFTD1, SFTD2, ... Of the shift register 42D correspond to the gate lines Y2, Y6, Y10 ,.
14D outputs on-pulses in the order of the gate lines Y6, Y14, Y22, ... In three horizontal cycles. The start pulse ST
By setting V4, the gate line that first supplies the ON pulse and its timing can be appropriately adjusted.

Next, the operation of the embodiment thus constructed will be described with reference to FIGS. FIG. 3 is a timing chart showing gate signals output from the Y drivers 14A to 14D in the first and second fields. FIG. 3 (a) shows a video signal, and FIGS. 3 (b) to 3 (e) are first charts, respectively. The gate signals from the Y drivers 14A to 14D in the field are shown, and FIGS.
The gate signals from the Y drivers 14A to 14D in the field are shown. FIG. 4 is a timing chart showing gate signals supplied to each gate line.
4A and 4B respectively show the video signal and the output instruction signal OE, and FIGS. 4C to 4P respectively show the gate lines Y1 to Y1.
4 shows the gate signal supplied to 4. 5A and 5B are explanatory diagrams for explaining the scanning method. FIG. 5A shows the case of odd fields and FIG. 5B shows the case of even fields. It should be noted that in FIG. 5, the gate lines that are driven at the same time are clearly shown by hatching.

In the normal 2-line simultaneous write mode, Y
Only the drivers 14A and 14B are operated. The video signal input through the input terminal 11 is given to the polarity inverting circuit 12. The polarity reversing circuit 12 inverts the polarity of the video signal at a predetermined cycle and supplies it to the X driver 13. The X driver 13 supplies the video signal to each data line 17 of the display unit 16 at the timing of the output instruction signal OE generated in the horizontal cycle.

On the other hand, in this mode, the Y driver 14C,
14D is stopped. Y driver 14A, 14B
Are the start pulses STV1, S
The TV2 simultaneously turns on the terminals SFTA1 and SFTA2 at the end. As a result, an ON pulse is supplied to the gate lines Y1 and Y2 to turn on each pixel of the first and second lines of the display section 16, and the liquid crystal is driven based on the image from the X driver 13. In the next horizontal cycle, gates Y3 and Y
An on-pulse is supplied to 4, and the liquid crystal of each pixel in the third and fourth lines of the display unit 16 is driven based on the image. In this way, the two-line simultaneous write drive is performed as in the conventional case.

Here, it is assumed that the zoom display mode is designated. In this mode, all the Y drivers 14A to 14D are in the operating state. In the first field, FIG.
As shown in (b), the Y driver 14A has a gate line Y3,
ON pulses are output in one horizontal cycle in the order of Y5, Y7, Y11, Y13, Y15, .... Further, as shown in FIG. 3C, the Y driver 14B has gate lines Y2, Y4, Y8 and Y1.
ON pulses are output in the order of 0, Y12, Y16, ... In one horizontal cycle. In addition, as shown in FIG.
C outputs on-pulses in the order of the gate lines Y1, Y9, ... In three horizontal cycles. Further, as shown in FIG. 3 (e), the Y driver 14D delays the output of the first ON pulse of the Y drivers 14A to 14C by two horizontal periods, and the gate line Y6
, Y14, ... In this order, ON pulses are output in three horizontal cycles.

Therefore, as shown in FIGS. 3 and 4, the first
In the first horizontal period of the field, Y drivers 14A, 14
ON pulses are simultaneously supplied to the gate lines Y1, Y2, and Y3 by B and 14C, the pixels of the first to third lines of the display unit 16 are turned on, and the liquid crystal is driven based on the video signal from the X driver 13. To be done. In the next horizontal period, on-pulses are supplied to the gate lines Y4 and Y5 by the Y drivers 14A and 14B to drive the pixels of the fourth and fifth lines of the display section 16. In the next horizontal period, Y drivers 14A, 14B,
The ON pulse is simultaneously supplied to the gate lines Y6, Y7 and Y8 by 14D, and the video signal is written in the pixels of the sixth to eighth lines of the display section 16. After that, in the same manner as in FIG.
As shown in (a), the display unit 16 has three lines, two lines,
The pixels of three lines are written in the horizontal cycle, and all the pixels are written in one field period. That is, the video signal is written in the pixels of 8 lines in the three horizontal periods, and the video signal is expanded by 4/3 times in the vertical direction and displayed.

In the second field, the Y driver 14
As shown in FIG. 3 (f), A is gates Y3, Y7, Y
ON pulses are output in the horizontal cycle in the order of 9, Y11, Y15, Y17, .... Further, the Y driver 14B, as shown in FIG. 3 (g), includes gate lines Y4, Y6, Y8, Y12, Y14, Y.
Outputs on-pulses in the horizontal cycle in the order 16 ... Also,
As shown in FIG. 3 (h), the Y driver 14C delays the output of the first on-pulse of the Y drivers 14A and 14B by one horizontal period and outputs on-pulses in the order of the gate lines Y5, Y13, ... In three horizontal cycles. Output. Also, the Y driver 14D
As shown in FIG. 3 (i), the gate lines Y2, Y10, ...

That is, in the second field, first, the gate lines Y2 are driven by the Y drivers 14A, 14B and 14D.
, Y3, Y4 are supplied with on-pulses, as shown in FIG.
As indicated by the slanted lines, the display unit 16 simultaneously writes to the pixels of the second to fourth lines. In the next horizontal period, the gate lines Y5, Y6, and Y6 are driven by the Y drivers 14A, 14B, and 14C.
An on-pulse is supplied to Y7 to simultaneously write in each pixel on the fifth to seventh lines. In the next horizontal period, on-pulses are supplied to the gate lines Y8 and Y9 by the Y drivers 14A and 14B, and writing is simultaneously performed on each pixel of the eighth and ninth lines. In the next horizontal period, Y drivers 14A, 14
An on-pulse is supplied to the gate lines Y10, Y11, Y12 by B and 14D, and writing is simultaneously performed on each pixel of the tenth to twelfth lines. After that, the same operation is repeated, and the image is vertically expanded by 4/3 and displayed.

By shifting the set of gate lines for simultaneously supplying on-pulses in the odd field and the even field, the vertical resolution close to the interlaced scanning display of the CRT is obtained. Further, by shifting the set of gate lines for simultaneously supplying the ON pulse to the two gate lines by 4 lines in the odd field and the even field, these two gate lines are placed in the middle of the two 3-line simultaneous driving portions in the previous field. It is located in the area to reduce interference.

As described above, in this embodiment, the Y drivers 14C and 14D are provided outside the Y drivers 14A and 14B,
These Y drivers 14C and 14D supply on-pulses to every four gate lines, and it is possible to simultaneously supply on-pulses to three, two, and three gate lines in a predetermined three horizontal periods. I have to. That is, eight lines of pixels can be driven in three horizontal periods, and a zoom display in which the image is vertically multiplied by 4/3 is enabled. In addition, since the pairs of gate lines that supply on-pulses are shifted in the odd field and the even field, it is possible to improve the vertical resolution.
Interference can be reduced.

In the above embodiment, the case where a high-definition image having an aspect ratio of 16: 9 is zoom-displayed on an NTSC standard display screen having an aspect ratio of 4: 3 has been described. , The aspect ratio is 4: 3 and the aspect ratio is 4: 3.
It is obvious that the method can be applied to the case where the TSC image is zoomed. In this embodiment, a monochrome liquid crystal module is adopted, but the present invention is also applicable to a color display liquid crystal module having a lattice pixel array in which color filters are arranged in stripes.

[0065]

As described above, according to the present invention, it is possible to perform zoom display with a relatively simple circuit structure without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a drive circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of Y drivers 14A to 14D in FIG.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is an explanatory diagram for explaining a scanning method according to the embodiment.

FIG. 6 is an explanatory diagram showing a modified example of the embodiment.

FIG. 7 is an explanatory diagram showing a liquid crystal projector using a liquid crystal panel.

FIG. 8 is a block diagram showing a liquid crystal display device using a liquid crystal module.

9 is an explanatory diagram showing a specific configuration of an X driver 13 and a display section 16 in FIG.

10 is a block diagram specifically showing a Y driver 14 in FIG.

FIG. 11 is a timing chart for explaining a conventional scanning method.

FIG. 12 is an explanatory diagram for explaining another scanning method of the conventional example.

FIG. 13 is an explanatory diagram showing a drive circuit of a conventional liquid crystal display device.

FIG. 14 is a timing chart for explaining the operation of the conventional example of FIG.

FIG. 15 is an explanatory diagram showing an aspect ratio of a display screen in NTSC and high definition.

FIG. 16 is an explanatory diagram for explaining letterbox display and zoom display.

FIG. 17 is a block diagram showing a drive circuit of a conventional liquid crystal display device.

[Explanation of symbols]

13 ... X driver, 14A to 14D ... Y driver, 16 ... Display section, 17 ... Data line, Y1, Y2, ... Gate line.

Claims (3)

[Claims] 1. A pixel is formed at each intersection of a plurality of data lines and a plurality of gate lines arranged in a grid, and the pixel is driven by an on-pulse supplied to the gate line and a pixel signal supplied to the data line. A liquid crystal display unit, a data line driving circuit that supplies pixel signals to the plurality of data lines in a horizontal cycle, and 3 (n−) of one field of the plurality of gate lines.
1) The 8th time in the + 1st (n is a natural number) horizontal scanning period.
(N-1) +1, eighth (n-1) +2 and eighth (n-)
1) Supply an ON pulse to the + 3rd gate line at the same time,
8 (n-) during the 3 (n-1) + 2nd horizontal scanning period.
1) +4 and 8 (n-1) + 5th gate lines are simultaneously supplied with on-pulses, and in the 3 (n-1) + 3rd horizontal scanning period, the 8 (n-1) +6, 8 (n) -1) +7 and 8 (n-1) + 8th gate lines are simultaneously supplied with on-pulses, while the other field is 3 (n-1) +
In the first horizontal scanning period, the eighth (n-1) and eighth (n-1)
The ON pulse is simultaneously supplied to the −1) + 1th gate line, and the 8 (n−1) + 8th (n−1) + th horizontal scanning period is performed.
-1) +2, 8th (n-1) +3 and 8th (n-1) +
An ON pulse is supplied to the fourth gate line at the same time, and 3 (n
-1) + 8th (n-1) + in the third horizontal scanning period
5. A drive circuit of a liquid crystal display device, comprising: a gate line drive circuit for simultaneously supplying ON pulses to the 5th, 8th (n-1) + 6th and 8th (n-1) + 7th gate lines. 2. A pixel is formed at each intersection of a plurality of data lines and a plurality of gate lines arranged in a grid, and the pixel is driven by an on-pulse supplied to the gate line and a pixel signal supplied to the data line. A liquid crystal display unit, a data line driving circuit that supplies pixel signals to the plurality of data lines in a horizontal cycle, and 3 (n−) of one field of the plurality of gate lines.
1) The 8th time in the + 1st (n is a natural number) horizontal scanning period.
The (n-1) +1 and 8 (n-1) + 2nd gate lines are simultaneously supplied with on-pulses, and the 8 (n-1) + 3th and 3rd (n-1) + th horizontal scanning periods are performed. 8 (n-1)
The ON pulse is simultaneously supplied to the + 4th and 8th (n-1) + 5th gate lines, and the 8th (n-1) + 6th and 8th (n-1) th lines are supplied during the 3 (n-1) + 3rd horizontal scanning period. ) +7 and 8 (n-1) + 8th gate lines are simultaneously supplied with on-pulses, and 8 (n-1) -1, 8 (n-1) -1, in the 3 (n-1) + 1th horizontal scanning period of the other field. 8th (n-
1) and 8 (n-1) + 1th gate lines are simultaneously supplied with on-pulses, and in the 3 (n-1) + 2nd horizontal scanning period, 8 (n-1) +2, 8 (n-) 1) +3 and the 8th (n-1) + 4th gate lines are simultaneously supplied with on-pulses, and the 3 (n-1) + 3rd horizontal scanning period
A driving circuit for a liquid crystal display device, comprising: a (n-1) + 5th and an (n-1) + 6th gate lines which simultaneously supply ON-pulses. 3. A pixel is formed at each intersection of a plurality of data lines and a plurality of gate lines arranged in a grid, and the pixel is driven by an on-pulse supplied to the gate line and a pixel signal supplied to the data line. A liquid crystal display unit, a data line driving circuit that supplies pixel signals to the plurality of data lines in a horizontal cycle, and 3 (n−) of one field of the plurality of gate lines.
1) The 8th time in the + 1st (n is a natural number) horizontal scanning period.
(N-1) +1, eighth (n-1) +2 and eighth (n-)
1) Supply an ON pulse to the + 3rd gate line at the same time,
8 (n-) during the 3 (n-1) + 2nd horizontal scanning period.
1) +4, 8th (n-1) +5 and 8th (n-1) +6
An on-pulse is supplied to the second gate line at the same time, and 3 (n-
1) The ON pulse is simultaneously supplied to the 8th (n-1) + 7th and 8th (n-1) + 8th gate lines in the (3) th horizontal scanning period, and the other field is 3 (n-1) +.
In the first horizontal scanning period, the 8th (n-1), 8th (n-)
1) +1 and 8 (n-1) + 2nd gate lines are simultaneously supplied with on-pulses, and 8 (n-1) +3 and 8 (n) are supplied in the 3 (n-1) + 2nd horizontal scanning period. -1) +4
An on-pulse is supplied to the second gate line at the same time, and 3 (n-
1) + 8th (n-1) +5 in the horizontal scanning period,
A drive circuit for a liquid crystal display device, comprising: a gate line drive circuit that simultaneously supplies ON pulses to the 8th (n-1) + 6th and 8th (n-1) + 7th gate lines.