JPH0516767B2 - - Google Patents
Info
- Publication number
- JPH0516767B2 JPH0516767B2 JP7783285A JP7783285A JPH0516767B2 JP H0516767 B2 JPH0516767 B2 JP H0516767B2 JP 7783285 A JP7783285 A JP 7783285A JP 7783285 A JP7783285 A JP 7783285A JP H0516767 B2 JPH0516767 B2 JP H0516767B2
- Authority
- JP
- Japan
- Prior art keywords
- collector
- base
- transistor
- npn
- connect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、増幅回路、特に入力信号電圧を電流
に交換して増幅する増幅回路に関す。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier circuit, and particularly to an amplifier circuit that converts an input signal voltage into a current and amplifies it.
第2図は、従来の増幅回路の一実施例の回路図
である。
FIG. 2 is a circuit diagram of an embodiment of a conventional amplifier circuit.
この回路は、差動型式に接続されたNPNトラ
ンジスタ9及び10(以降トランジスタをTrと
する)のベースを各々入力端子3及び4とし、
NPNTr9及び10の各エミツタに定電流源24
接続し、NPNTr9及び10の各々ダイオード接
続されたNPNTr7及び8のベース・コレクタを
接続し、エミツタは各々抵抗16及び17を介し
て高電位端1に接続し、PNPTr7のベース・コ
レクタの接続点にNPNTr11のベースを接続
し、PNPTr11のエミツタをNPNTr15のコ
レクタに接続し、その接続点から抵抗19を介し
て高電位端1に接続し、NPNPr11のコレクタ
をNPNTr15のベースと定電流源25に接続
(以上上側出力段と称する)し、PNPTr8のベー
ス・コレクタの接続点にPNPTr12のベースを
接続し、PNPTr12のエミツタから抵抗18を
介して高電位端1に接続し、PNPTr12のコレ
クタにダイオード接続されたNPNTr13のベー
ス・コレクタを接続し、NPNTr13のベース・
コレクタの接続点にNPNTr14のベースを接続
し、NPNTr13及び14のエミツタから各々抵
抗20及び21を介して、低電位端2に接続(以
上、下側出力段と称する)し、NPNTr15のエ
ミツタとNPNTr14のコレクタを接続し、その
接続点を出力端5とし、NPNTr9及び10のベ
ースに各々抵抗22及び23を介してバイアス電
圧を印加するバイアス電源26で構成される増幅
回路であり、さらに、出力端5は負荷6に接続さ
れる。 This circuit uses the bases of differentially connected NPN transistors 9 and 10 (hereinafter transistors are referred to as Tr) as input terminals 3 and 4, respectively.
Constant current source 24 for each emitter of NPNTr9 and 10
The bases and collectors of NNPTrs 7 and 8, which are diode-connected in NNPTrs 9 and 10, respectively, are connected, and the emitters are connected to the high potential end 1 through resistors 16 and 17, respectively, and to the connection point of the base and collector of PNPTr 7. Connect the base of NPNTr11, connect the emitter of PNPTr11 to the collector of NPNTr15, connect the connection point to high potential end 1 via resistor 19, and connect the collector of NPNTr11 to the base of NPNTr15 and constant current source 25 ( The base of PNPTr12 is connected to the base-collector connection point of PNPTr8, the emitter of PNPTr12 is connected to the high potential end 1 via resistor 18, and the collector of PNPTr12 is connected to the collector of PNPTr12. Connect the base and collector of NPNTr13, and connect the base and collector of NPNTr13.
The base of NPNTr 14 is connected to the connection point of the collector, and the emitters of NPNTr 13 and 14 are connected to the low potential end 2 via resistors 20 and 21, respectively (hereinafter referred to as the lower output stage), and the emitters of NPNTr 15 and NPNTr 14 are connected to the low potential end 2 (hereinafter referred to as the lower output stage). It is an amplifier circuit consisting of a bias power supply 26 that connects the collectors of the NPNTrs 9 and 10, sets the connection point as the output terminal 5, and applies a bias voltage to the bases of the NNPTrs 9 and 10 through resistors 22 and 23, respectively. 5 is connected to a load 6.
かかる従来の電流増幅回路は、ダイオード接続
されたNPNTr13とNPNTr14のカレントミ
ラー回路から構成される下側出力段はNPNTr1
4のコレクタ・ベース間容量が帰還容量となり高
域周波数での利得低下を来す。そのため、ダイオ
ード接続されたPNPTr7とダーリントン接続さ
れたPNPTr11とNPNTr15のカレントミラ
ー回路から構成される上側出力段の周波数特性
(特性)にピーキングをかけ、増幅回路全体の
特性を高域補償している。このため上側出力段
と下側出力段に利得の差が生じ、出力電流が均一
にならず、出力信号の歪の原因となる。またこの
増幅回路の構成では、定電流源24の電流値を固
定すると上側及び下側出力段の電流を均一にする
ために、最適な値に定電流源25の電流値を固定
しなけれずならない。つまり上側出力段を構成す
るカレントミラー回路の出力NPNTr15のエミ
ツタ電流が定電流源25の電流値に依存している
ため、定電流源24の電流値を変えて負荷に必要
な電流を供給すると上側出力段の電流変換比と下
側出力段の電流交換比に差を生じ、上側と下側の
出力電流が不均一になる為交流信号の振幅に上下
の差を生じ出力信号の歪の原因となる。そのた
め、希望の出力電流を得るためには、2ケ所の定
電流源を変える必要があつた。
In such a conventional current amplification circuit, the lower output stage is composed of a current mirror circuit of diode-connected NPNTr13 and NPNTr14.
The collector-base capacitance of No. 4 becomes a feedback capacitance and causes a gain drop at high frequencies. Therefore, peaking is applied to the frequency characteristics (characteristics) of the upper output stage, which consists of a current mirror circuit of diode-connected PNPTr7 and Darlington-connected PNPTr11 and NPNTr15, to compensate for the high frequency characteristics of the entire amplifier circuit. Therefore, a difference in gain occurs between the upper output stage and the lower output stage, resulting in uneven output current and distortion of the output signal. Furthermore, in the configuration of this amplifier circuit, when the current value of the constant current source 24 is fixed, the current value of the constant current source 25 must be fixed to an optimal value in order to equalize the currents in the upper and lower output stages. . In other words, since the emitter current of the output NPNTr 15 of the current mirror circuit that constitutes the upper output stage depends on the current value of the constant current source 25, if the current value of the constant current source 24 is changed to supply the necessary current to the load, the upper A difference occurs between the current conversion ratio of the output stage and the current exchange ratio of the lower output stage, and the output currents on the upper and lower sides become uneven, resulting in a difference in the amplitude of the AC signal between the upper and lower sides, which causes distortion of the output signal. Become. Therefore, in order to obtain the desired output current, it was necessary to change two constant current sources.
本発明の目的は、上記した従来技術における欠
点を無くし、上側及び、下側出力電流を均一に
し、かつ、Trのコレクタ・ベース間容量を低減
し、高域周波数での利得低下をおさえ、出力信号
の歪を軽減した回路を提供するものであり、又オ
フセツト電圧の軽減及び抵抗の相対比を良くし集
積回路に適した増幅回路を得ることにある。 The purpose of the present invention is to eliminate the drawbacks of the above-mentioned conventional technology, make the upper and lower output currents uniform, reduce the capacitance between the collector and base of the Tr, suppress the decrease in gain at high frequencies, and output It is an object of the present invention to provide a circuit with reduced signal distortion, and to obtain an amplifier circuit suitable for integrated circuits by reducing offset voltage and improving the relative ratio of resistances.
本発明の増幅回路は、第1のPNPTrのベース
を反転入力端とし、第2のPNPTrのベースを非
反転入力端とし、第1のPNPTrのエミツタを第
1の抵抗を介して高電位端に接続し、第1の
PNPTrのコレクタに第3のNPNTrのコレク
タ・ベースと第4のNPNTrのベースとを接続
し、第4のNPNTrのコレクタに第5のNPNTr
のエミツタを接続し、第5のコレクタを高電位端
に接続し、第3及び第4のNPNTrのエミツタに
各々第2及び第3の抵抗を接続し、第2の
PNPTrのエミツタを第4の抵抗を介して高電位
端に接続し、第2のPNPTrのコレクタに第6の
NPNTrのコレクタ・ベースと第7のNPNTrの
ベースを接続し、第7のNPNTrのコレクタに第
8のNPNTrのエミツタを接続し、第8の
NPNTrのコレクタに第2、第3の抵抗の接続点
を出力端として構成している。
In the amplifier circuit of the present invention, the base of the first PNPTr is an inverting input terminal, the base of the second PNPTr is a non-inverting input terminal, and the emitter of the first PNPTr is connected to a high potential terminal via a first resistor. Connect and connect the first
The collector base of the third NPNTr and the base of the fourth NPNTr are connected to the collector of the PNPTr, and the collector base of the fourth NPNTr is connected to the collector base of the fifth NPNTr.
, the fifth collector is connected to the high potential end, the second and third resistors are connected to the emitters of the third and fourth NPNTr, respectively, and the fifth collector is connected to the high potential terminal.
The emitter of the PNPTr is connected to the high potential end through the fourth resistor, and the sixth resistor is connected to the collector of the second PNPTr.
Connect the collector base of the NPNTr to the base of the seventh NPNTr, connect the collector of the seventh NPNTr to the emitter of the eighth NPNTr, and connect the emitter of the eighth NPNTr to the collector base of the seventh NPNTr.
The connection point of the second and third resistors is configured as an output terminal at the collector of the NPNTr.
次に、本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
第1図は本発明の一実施例の回路図である。こ
の実施例は、反転入力端子と非反転入力端子を有
する増幅器39及び40を用い増幅器39の反転
入力端子と増幅器40の非反転入力端子を接続
し、増幅器39の非反転入力端子と増幅器40の
反転入力端子を接続し、増幅器39及び40の出
力に各々PNPTr11のベースとPNPTr12のベ
ースを接続し、PNPTr11のエミツタを抵抗1
9を介して高電位端1に接続し、PNPTr11の
コレクタにダイオード接続したNPNTr28のコ
レクタおよびベースを接続し、NPNTr28のコ
レクタおよびベースにNPNTr29のベースを接
続し、NPNTr29のコレクタにNPNTr27の
エミツタを接続し、NPNTr27のコレクタを高
電位端1に接続しNPNTr28及び29のエミツ
タに各抵抗33及び34を接続し、PNPTr12
のエミツタを抵抗18を介して高電位端1に接続
し、PNPTr12のコレクタにNPNTr13のコ
レクタおよびベースを接続し、NPNTr13のコ
レクタおよびベースNPNTr14のベースを接続
し、NPNTr14のコレクタにNPNTr30のエ
ミツタを接続し、NPNTr30のコレクタに抵抗
33と34を接続し、NPNTr13及び14のエ
ミツタに各々抵抗20及び21を介して低電位端
2に接続し、NPNTr27のベースをダイオード
35のカソード側と抵抗36の交点に接続し、ダ
イオード35のアノード側を高電位端1に接続
し、抵抗36の他端をNPNTr30のベースとダ
イオード37のアノード側に接続し、ダイオード
37のカソード側をダイオード38のアネード側
に接続し、ダイオード38のカソード側を低電位
端2に接続し、NPNTr30のコレクタと抵抗3
3と34の接続点を出力端5として構成する増幅
回路であり、さらに出力端5は負荷6に接続して
いる。 FIG. 1 is a circuit diagram of an embodiment of the present invention. In this embodiment, amplifiers 39 and 40 having an inverting input terminal and a non-inverting input terminal are used, and the inverting input terminal of the amplifier 39 and the non-inverting input terminal of the amplifier 40 are connected. Connect the inverting input terminal, connect the bases of PNPTr11 and PNPTr12 to the outputs of amplifiers 39 and 40, respectively, and connect the emitter of PNPTr11 to the resistor 1.
9 to the high potential end 1, connect the collector and base of NPNTr28 connected to the diode to the collector of PNPTr11, connect the base of NPNTr29 to the collector and base of NPNTr28, and connect the emitter of NPNTr27 to the collector of NPNTr29. Then, connect the collector of NNPTr27 to the high potential end 1, connect the resistors 33 and 34 to the emitters of NNPTr28 and 29, and connect the collector of PNPTr27 to the high potential terminal 1.
Connect the emitter of NPNTr13 to the high potential end 1 through the resistor 18, connect the collector and base of NPNTr13 to the collector of PNPTr12, connect the collector and base of NPNTr13 to the base of NPNTr14, and connect the emitter of NPNTr30 to the collector of NPNTr14. Resistors 33 and 34 are connected to the collector of NPNTr 30, the emitters of NPNTr 13 and 14 are connected to the low potential end 2 via resistors 20 and 21, respectively, and the base of NPNTr 27 is connected to the intersection of the cathode side of diode 35 and resistor 36. , connect the anode side of the diode 35 to the high potential end 1, connect the other end of the resistor 36 to the base of the NPNTr 30 and the anode side of the diode 37, and connect the cathode side of the diode 37 to the anode side of the diode 38. The cathode side of the diode 38 is connected to the low potential terminal 2, and the collector of the NPNTr 30 and the resistor 3 are connected.
This is an amplifier circuit in which the connection point between 3 and 34 is configured as an output terminal 5, and the output terminal 5 is further connected to a load 6.
本発明の回路では、従来問題になつていた下側
出力段のカレントミラー回路のNPNTr14のコ
レクタ・ベース問容量が帰還容量となり高域周波
数での利得低下をNPNTr30をNPNTr14の
コレクタに挿入することで、帰還容量を減少し周
波数特性の良い増幅回路を得る。 In the circuit of the present invention, the collector-base capacitance of NPNTr 14 of the current mirror circuit in the lower output stage becomes a feedback capacitance, which has been a problem in the past, by inserting NPNTr 30 into the collector of NPNTr 14. , an amplifier circuit with good frequency characteristics is obtained by reducing the feedback capacitance.
又、上側出力段回路と下側出力段回路を同一回
路構成することにより、出力電流の流出電流と流
入電流を同一として、出力信号の歪を無くす効果
が得られる。 Further, by configuring the upper output stage circuit and the lower output stage circuit in the same circuit, it is possible to make the outflow current and the inflow current of the output current the same, thereby eliminating distortion of the output signal.
このように本発明によれば、周波数特性が良好
で出力歪の少ない増幅回路を得ることができる。
As described above, according to the present invention, an amplifier circuit with good frequency characteristics and low output distortion can be obtained.
第1図は本発明の一実施例を示す回路図であ
る。第2図は従来の増幅回路の一例を示す回路図
である。
1……高電位端、2……低電位端、3,4……
入力端、5……出力端、6……負荷、7,8,1
1,12……NPNトランジスタ、9,10,1
3,14,15,27,28,29……NPNト
ランジスタ、16,17,18,19,20,2
1,33,34,36……抵抗、22,23……
バイアス抵抗、24,25……定電流源、35,
37,38……ダイオード、39,40……増幅
器。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a conventional amplifier circuit. 1...High potential end, 2...Low potential end, 3, 4...
Input end, 5... Output end, 6... Load, 7, 8, 1
1, 12...NPN transistor, 9, 10, 1
3, 14, 15, 27, 28, 29...NPN transistor, 16, 17, 18, 19, 20, 2
1, 33, 34, 36...Resistance, 22, 23...
Bias resistor, 24, 25...constant current source, 35,
37, 38...diode, 39, 40... amplifier.
Claims (1)
力端とし、第2のPNPトランジスタのベースを
非反転入力端とし、前記第1のPNPトランジス
タのエミツタを第1の抵抗を介して高電位端に接
続し、前記第1のPNPトランジスタのコレクタ
に第3のNPNトランジスタのコレクタ・ベース
と第4のNPNトランジスタのベースを接続し、
前記第4のNPNトランジスタのコレクタに第5
のNPNトランジスタのエミツタを接続し、該第
5のNPNトランジスタのコレクタを高電位端に
接続し、前記第3及び第4のNPNトランジスタ
のエミツタに各々第2及び第3の抵抗を接続し、
前記第2のPNPトランジスタのエミツタに第4
の抵抗を介して高電位端に接続し、前記第2の
PNPトランジスタのコレクタに第6のNPNトラ
ンジスタのコレクタ・ベースと第7のNPNトラ
ンジスタのベースを接続し、該第7のNPNトラ
ンジスタのコレクタに第8のNPNトランジスタ
のエミツタを接続し、該第8のNPNトランジス
タのコレクタに前記第2、第3の抵抗の他端を接
続し、前記第6、第7のNPNトランジスタのエ
ミツタに各々第5、第6の抵抗を介して低電位に
接続し、前記第5、第8のNPNトランジスタの
ベースに各々第1、第2のバイアス電源を接続
し、前記第8のNPNトランジスタと第2、第3
の抵抗の接続点を出力端として構成することを特
徴とする増幅回路。1 The base of the first PNP transistor is used as an inverting input terminal, the base of the second PNP transistor is used as a non-inverting input terminal, and the emitter of the first PNP transistor is connected to a high potential terminal via a first resistor. , connecting the collector-base of a third NPN transistor and the base of a fourth NPN transistor to the collector of the first PNP transistor;
A fifth NPN transistor is connected to the collector of the fourth NPN transistor.
connecting the emitters of the fifth NPN transistor, connecting the collectors of the fifth NPN transistors to the high potential end, and connecting second and third resistors to the emitters of the third and fourth NPN transistors, respectively;
A fourth transistor is connected to the emitter of the second PNP transistor.
is connected to the high potential end through a resistor of the second
The collector-base of the sixth NPN transistor and the base of the seventh NPN transistor are connected to the collector of the PNP transistor, the emitter of the eighth NPN transistor is connected to the collector of the seventh NPN transistor, and the emitter of the eighth NPN transistor is connected to the collector of the seventh NPN transistor. The other ends of the second and third resistors are connected to the collectors of the NPN transistors, and the emitters of the sixth and seventh NPN transistors are connected to a low potential via fifth and sixth resistors, respectively. First and second bias power supplies are connected to the bases of the fifth and eighth NPN transistors, respectively.
An amplifier circuit characterized in that the connecting point of the resistors is configured as an output terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7783285A JPS61237505A (en) | 1985-04-12 | 1985-04-12 | Amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7783285A JPS61237505A (en) | 1985-04-12 | 1985-04-12 | Amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61237505A JPS61237505A (en) | 1986-10-22 |
JPH0516767B2 true JPH0516767B2 (en) | 1993-03-05 |
Family
ID=13645015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7783285A Granted JPS61237505A (en) | 1985-04-12 | 1985-04-12 | Amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61237505A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007318571A (en) * | 2006-05-26 | 2007-12-06 | Fujitsu Ltd | Operational amplifier circuit |
-
1985
- 1985-04-12 JP JP7783285A patent/JPS61237505A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS61237505A (en) | 1986-10-22 |
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