JPH05166845A - Field effect transistor - Google Patents

Abstract

PURPOSE:To get a high-speed, high-frequency, and low-noise FET which has enabled the improvement of the uniformity and the reproducibility of transistor properties, the increase of drain breakdown strength, and the reduction of source resistance, by making a multilayer semiconductor layer include a p-type semiconductor layer, and forming a p-type semiconductor layer selectively right below a gate electrode, and others. CONSTITUTION:This transistor includes a multilayer semiconductor layer 18 consisting of a compound semiconductor, a gate electrode 10, a source electrode 11, and a drain electrode 12, and has an n-type conductive channel, wherein electrons are made carriers, in one part inside the multilayer semiconductor layer 18. In such an FET, the multilayer semiconductor layer 18 includes a p-type semiconductor layer 7, and one part of the multilayer semiconductor layer 18 from the surface of the multilayer semiconductor layer 18 to at least the p-type semiconductor layer 7 is removed excluding the region 16 below the gate electrode 10, and the p-type semiconductor layer 7 is made selectively right below the gate electrode 10. And, the end in the direction of the channel of the gate electrode 10 is on the same line as the end of the p-type semiconductor layer 7 or outside of the end of the p-type semiconductor layer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor including a multi-layer semiconductor layer made of a compound semiconductor, and more particularly to improving uniformity and reproducibility of transistor characteristics,
The present invention relates to a high-speed, high-frequency, low-noise field effect transistor capable of increasing drain withstand voltage and reducing source resistance.

[0002]

2. Description of the Related Art FIG. 5 shows a sectional structure of a conventional field effect transistor.

On a semi-insulating InP substrate 51, an undoped InAlAs layer 52 having a film thickness of 2000Å, an undoped InGaAs layer 53 having a film thickness of 300Å, an undoped InAlAs layer 54 having a film thickness of 20Å, n-type (Si addition, impurities InAlA with a concentration of 4 × 10 ¹⁸ cm ~ ³ ) and a film thickness of 150Å
s layer 55, undoped InAlAs layer 56 with a film thickness of 200 Å, n-type (Si added, 4 × 10 ¹⁸ cm to ³ ) and a film thickness of 10
A semiconductor multi-layered structure (hereinafter referred to as a multi-layered semiconductor layer) in which 0 Å InGaAs layer 57 is stacked in that order 5
8 is formed, a part of the multilayer semiconductor layer 58 is removed from the surface to a depth reaching at least the InAlAs layer 56 to form a groove 70, and a gate Schottky electrode (hereinafter referred to as a gate electrode) is formed on the bottom surface of the groove 70. 60) is formed, and the gate electrode 6 on the InGaAs layer 57 is formed.
A source ohmic electrode (hereinafter referred to as a source electrode) 61 and a drain ohmic electrode (hereinafter referred to as a drain electrode) 62 are formed at both positions sandwiching 0.

According to the field effect transistor having such a structure, in the source region 63 and the drain region 64 outside the groove 70, the InGaAs layer 53 has a high concentration (about 5 × 1).
An electron accumulation layer of 0 ¹² cm to ² ) is formed, and an appropriate amount (about 1 × 10 6) of InGaAs layer 53 is formed in the region 65 inside the groove 70.
An electron accumulation layer of ¹² cm ~ ² ) is formed. This electron storage layer is shown at 68 in FIG. Here, the width of the shaded area schematically represents the magnitude of the electron concentration. Such an electron concentration distribution is a necessary condition for reducing the source resistance and efficiently controlling the electron concentration immediately below the gate electrode by the gate electrode.

To operate this field effect transistor, the voltage applied to the gate electrode 60 is changed to change the concentration of electrons in the region 66 immediately below the gate electrode, and the electrons flowing from the source electrode 61 to the drain electrode 62 are changed. The flow rate, that is, the drain current is changed.

[0006]

The conventional field effect transistor having the structure shown in FIG. 5 has the following problems.

The uniformity and reproducibility of transistor characteristics such as threshold voltage are not good. This is because the transistor characteristics are extremely sensitive to the depth of the groove 70 and extremely high processing accuracy is required in the manufacturing process of the groove 70.

The drain breakdown voltage is small. This is because a high electric field is applied to the undoped InAlAs layer 56.

The source resistance is large. This is because there is a region 71 having an electron concentration lower than that of the source region 63 in the vicinity of the gate electrode 60 on the side of the source region 63 except under the gate electrode 60. In the region 71, since the region 66 directly below the gate electrode 60 is smaller than the region 65 inside the groove 70,
It is inevitable when manufacturing a transistor of this structure.

[0010]

The above problem is caused by the fact that the gate electrode 60 is formed on the bottom surface of the groove 70. The groove 70 has a source region 63 and a drain region 6
4 has a high concentration (about 5 × 10 ¹² cm) in the InGaAs layer 53.
~ ² ) electrons are accumulated, and the region 66 immediately below the gate electrode 60 is accumulated.
Then, an appropriate amount for the InGaAs layer 53 (about 1 × 10 ¹² cm ~ ² )
It was necessary in order to realize the state that the electrons of the above were accumulated.

The above problem arises from the fact that a high electric field is easily applied to the undoped InAlAs layer 56 because the semiconductor layer in the region 66 immediately below the gate electrode 60 is only an undoped layer or an n-type layer.

In the present invention, the formation of the groove 70 is stopped in order to solve the above problem. In order to solve the above problem, a p-type semiconductor layer such as p
A type InAlAs layer is to be inserted. Despite these changes, InG in the source and drain regions
A high concentration (about 5 × 10 ¹² cm- ² ) of electrons is accumulated in the aAs layer, and an appropriate amount (about 1 × 10 ¹² cm- ² ) of electrons is accumulated in the InGaAs layer in the region immediately below the gate electrode. In order to realize it, the structure of the field effect transistor is drastically changed as follows.

That is, according to the present invention, an n-type conductive layer including a multi-layer semiconductor layer made of a compound semiconductor, a gate electrode, a source electrode and a drain electrode, and having a part of the multi-layer semiconductor layer as an electron carrier is used. In the field effect transistor forming a channel, the multilayer semiconductor layer includes a p-type semiconductor layer, and one of the multilayer semiconductor layers from the surface of the multilayer semiconductor layer to at least the p-type semiconductor layer except a region under the gate electrode. Portions are removed to selectively form the p-type semiconductor layer directly below the gate electrode, and
A field effect transistor is proposed in which the end portion of the gate electrode in the channel direction is the same as the end portion of the p-type semiconductor layer or is outside the end portion of the p-type semiconductor layer.

[0014]

In the field effect transistor of the present invention, since the groove (70 in the prior art shown in FIG. 5) is not formed, the uniformity and reproducibility of transistor characteristics such as threshold voltage and transconductance are improved, and the source resistance is reduced. To do. Further, since the p-type semiconductor layer is provided immediately below the gate electrode, the drain breakdown voltage increases.

[0015]

EXAMPLE 1 FIG. 1 is a cross-sectional view of a field effect transistor of Example 1 of the present invention.

On a semi-insulating InP substrate 1, an undoped InAlAs layer 2 having a film thickness of 2000Å, an undoped InGaAs layer 3 having a film thickness of 300Å, and an undoped film thickness of 20
Å InAlAs layer 4, n-type (Si added, 1.1 × 10
InAlAs layer 5 having a film thickness of 120 Å in ¹⁹ cm to ³ ), InAlAs layer 6 having an undoped thickness of 10 Å, InAlAs layer 7 having a film thickness of 60 Å in p-type (Be added, 3 × 10 ¹⁹ cm to ³ ), and undoped InAlAs layer 17 with a thickness of 150Å
However, the multi-layer semiconductor layer 8 laminated in the order is formed, and the multi-layer semiconductor layer 8 is removed from the surface to a depth reaching at least the InAlAs layer 5 except the region where the gate electrode is to be formed (InAlAs layer). 5 may be partially removed) A hill 9 is formed, a gate electrode 10 is formed on the top of the hill 9 in contact with at least the entire top of the hill 9, and a gate on the InAlAs layer 5 is formed. Electrode 10
A source electrode 11 and a drain electrode 12 are formed at both positions sandwiched by.

According to the field effect transistor having such a structure, as shown in the following calculation results, InGaA is formed in the source region 13 and the drain region 14 outside the hill 9.
A high-concentration (about 5 × 10 ¹² cm- ² ) electron accumulation layer is formed in the s-layer 3, and an appropriate amount (about 1 × 10 ¹² cm- ² ) of electrons are accumulated in the InGaAs layer 3 in the region 15 inside the hill 9. Accumulation layer is formed. This electron storage layer is shown at 18 in FIG. Here, the width of the shaded portion schematically shows the magnitude of the electron concentration. Such an electron concentration distribution is a necessary condition for reducing the source resistance and efficiently controlling the electron concentration immediately below the gate electrode by the gate electrode.

FIG. 3 shows the calculation result of the etching depth dependence of the electron concentration of the electron storage layer in the field effect transistor of FIG. First, in the region without etching, that is, in the region 15 inside the hill 9, as described above, InGaAs is used.
An appropriate amount (about 1 × 10 ¹² cm ² ) of an electron storage layer is formed in the layer 3, and the undoped InAlAs layer 17 and the p-type I layer are formed.
In the region where the nAlAs layer 7 and the undoped InAlAs layer 6 are removed by etching, that is, in the source region 13 and the drain region 14 outside the hill 9, as described above,
It can be seen that a high-concentration (about 3 to 5 × 10 ¹² cm to ² ) electron accumulation layer is formed in the nGaAs layer 3. This allows
It can be seen that the above requirements are satisfied.

The reason why the electron concentration changes with the etching depth as shown in FIG. 3 will be explained qualitatively as follows. That is, when the undoped InAlAs layer 17 and the p-type InAlAs layer 7 are present, the effective Schottky barrier height is high, so the InGaAs layer 3
Has a high potential energy and a low electron concentration,
When the undoped InAlAs layer 17 and the p-type InAlAs layer 7 are removed by etching, the effective Schottky barrier height decreases, so that the InGaAs layer 3
The potential energy of becomes low and the electron concentration becomes high. From this, it can be seen that the above-mentioned necessary conditions are satisfied.

In order to operate this field effect transistor, the voltage applied to the gate electrode 10 is changed to change the electron concentration of the region 16 immediately below the gate electrode 10 so that the electrons flowing from the source electrode 11 to the drain electrode 12 are changed. The flow rate, that is, the drain current is changed.

The field effect transistor of this embodiment has the following features.

Good uniformity and reproducibility of transistor characteristics such as threshold voltage and transconductance. This is because, unlike the conventional example, the threshold voltage of the transistor does not depend on the height of the hill 9, and the fabrication process of the hill 9 does not require high processing accuracy.

The drain breakdown voltage is high. This is different from the conventional example in that a p-type InAlA having a large breakdown voltage is formed in a region to which a high electric field is applied between the gate electrode 11 and the drain electrode 12.
This is because the s layer 7 exists.

Source resistance is small. This is because, unlike the conventional example, a region (71 in FIG. 5) having a lower electron concentration than the source region 13 does not occur in the vicinity of the gate region 10 on the side of the source region 13 except under the gate electrode 10 due to the structure of the transistor. .. More specifically, since the action of the gate electrode 10 reaches the electrons accumulated in the InGaAs layer 3 through the hill 9, the region 16 directly below the gate electrode 10 and the region 15 inside the hill 9 are structurally structured in this embodiment. This is because they match.

In this embodiment, n-type InA is used in order to avoid mixing of n-type and p-type impurities due to fluctuations during the manufacturing process.
An undoped InAlAs layer 6 is provided between the 1As layer 5 and the p-type InAlAs layer 7, and an undoped InAlAs layer 1 for suppressing leakage of holes into the gate electrode 20.
7 is provided. However, these layers 6 and 17 are not essential in the transistor structure and can be omitted.

Although the present embodiment has the above-mentioned features, the problem is that the uniformity and reproducibility of the source resistance are not good. This is because a high degree of processing accuracy is required in the step of etching the other portion leaving the hill 9.
This means that the etching proceeds excessively in FIG.
It can be seen from the fact that the electron concentration sharply decreases when reaching the inside of the nAlAs layer 5. In order to solve this problem, the second embodiment will be described below.

Example 2 FIG. 2 is a sectional view of a field effect transistor of Example 2 of the present invention.

On a semi-insulating InP substrate 21, an undoped InAlAs layer 22 having a film thickness of 2000 Å, n-type (Si
InAlAs with addition of 8 × 10 ¹⁸ cm ~ ³ ) and a film thickness of 50Å
Layer 23, undoped InAlAs layer 2 with thickness 20 Å
4, undoped InGaAs layer 25 with a film thickness of 200Å,
Undoped InAlAs layer 26 having a film thickness of 20 Å, p-type (Be added, 4 × 10 ¹⁸ cm ³ ), In having a film thickness of 260 Å
A multi-layer semiconductor layer 28 in which AlAs layers 27 are stacked in that order is formed, and the multi-layer semiconductor layer 28 is formed at least from the surface except the region where the gate electrode is to be formed.
It is removed to the depth reaching the nGaAs layer 25 (InG
The aAs layer 25 may be partially removed) A hill 29 is formed, a gate electrode 30 is formed on the top of the hill 29, and a source electrode is formed on both sides of the gate electrode 30 on the InGaAs layer 25. 31 and a drain electrode 32 are formed.

According to the field effect transistor having such a structure, in the source region 33 and the drain region 34 outside the hill 29, the InGaAs layer 25 has a high concentration (about 5 × 1).
An electron accumulation layer of 0 ¹² cm to ² ) is formed, and an appropriate amount (about 1 × 10 3) is applied to the InGaAs layer 25 in the region 36 inside the hill 29.
An electron accumulation layer of ¹² cm ~ ² ) is formed. This electron storage layer is shown at 38 in FIG. Here, the width of the shaded portion schematically represents the magnitude of the electron concentration. Such an electron concentration distribution is a necessary condition for reducing the source resistance and efficiently controlling the electron concentration directly under the gate electrode by the gate electrode.

FIG. 4 shows the calculation result of the etching depth dependence of the electron concentration of the electron storage layer in the field effect transistor of FIG. It can be seen that the electron concentration increases as the p-type InAlAs layer 27 and the undoped InAlAs layer 26 are removed by etching. This allows
It can be seen that the above requirements are satisfied.

To operate this field effect transistor, the voltage applied to the gate electrode 30 is changed to change the concentration of electrons in the region 36 immediately below the gate electrode 30, and the electrons flowing from the source electrode 31 to the drain electrode 32 are changed. And the drain current is changed.

The field effect transistor of this embodiment has the following features.

Good uniformity and reproducibility of transistor characteristics such as threshold voltage and transconductance. This is because, unlike the conventional example, the transistor characteristics do not depend on the height of the hill 29, and a high processing accuracy is not required in the manufacturing process of the hill 29.

The drain breakdown voltage is large. This is different from the conventional example in that p-type InAlA having a high breakdown voltage is formed in a region to which a high electric field is applied between the gate electrode 30 and the drain electrode 32.
This is because the s layer 27 exists.

Source resistance is small. This is because, unlike the conventional example, due to the structure of the transistor, a region (71 in FIG. 5) having a lower electron concentration than the source region 33 does not occur in the vicinity of the gate electrode 30 on the side of the source region 33 except immediately below the gate electrode 30. .. More specifically, since the action of the gate electrode 30 reaches the electrons accumulated in the InGaAs layer 25 through the hill 29, the region 36 immediately below the gate electrode 30 and the region 35 inside the hill 29 are structurally structured in this embodiment. This is because they match.

In this embodiment, the undoped InAlAs layer 26 is provided and the p-type InAlAs layer 27 is separated from the electron storage layer 38 in order to improve the traveling speed of electrons. However, the undoped InAlAs layer 26 is not essential for forming a transistor and can be omitted.

Further, in this embodiment, p-type InAl
By forming a part of the As layer 27 on the gate electrode 30 side as an undoped layer, it is possible to suppress the leakage of holes to the gate electrode 30.

The embodiment of the present invention has been described above.
The values of the film thickness and the impurity concentration of each layer in the first and second embodiments are merely examples, and it is apparent that the effect of improving the transistor characteristics shown in the present invention can be obtained even if other values are used. is there. Further, it is clear that even when other semiconductor materials or impurity elements are used, the same characteristic improving effect can be obtained as long as the transistor configuration similar to that of the present invention is adopted.

[0039]

As described above, according to the present invention,
It is possible to provide a field effect transistor having excellent uniformity and reproducibility of transistor characteristics, a large drain breakdown voltage, and a small source resistance. Therefore, it is suitable for application to various integrated circuits of high speed, high frequency, and low noise.

[Brief description of drawings]

FIG. 1 is a sectional view of a field effect transistor of a first embodiment of the present invention.

FIG. 2 is a sectional view of a field effect transistor of a second embodiment of the present invention.

3 is a diagram showing a calculation result of etching depth dependency of electron concentration of an electron storage layer in the field effect transistor of FIG.

4 is a diagram showing a calculation result of etching depth dependency of electron concentration of an electron storage layer in the field effect transistor of FIG.

FIG. 5 is a cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

1 ... Semi-insulating InP substrate, 2 ... Undoped InAlAs
Layer, 3 ... Undoped InGaAs layer, 4 ... Undoped I
nAlAs layer, 5 ... n-type InAlAs layer, 6 ... undoped InAlAs layer, 7 ... p-type InAlAs layer, 8 ... multilayer semiconductor layer, 9 ... hill, 10 ... gate electrode, 11 ... source electrode, 12 ... drain electrode, 13 ... Source region, 14 ... Drain region, 15 ... Region inside hill, 16 ... Region directly under gate electrode, 17 ... Undoped InAlAs layer, 18 ...
Electron storage layer, 21 ... Semi-insulating InP substrate, 22 ... Undoped InAlAs layer, 23 ... N-type InAlAs layer, 24
... undoped InAlAs layer, 25 ... undoped InG
aAs layer, 26 ... Undoped InAlAs layer, 27 ... p
Type InAlAs layer, 28 ... Multilayer semiconductor layer, 29 ... Hill, 3
0 ... Gate electrode, 31 ... Source electrode, 32 ... Drain electrode, 33 ... Source region, 34 ... Drain region, 35 ... Region inside hill, 36 ... Region immediately below gate electrode, 38 ... Electron storage layer.

Claims (1)

[Claims] 1. A multi-layer semiconductor layer made of a compound semiconductor, a gate electrode, a source electrode, and a drain electrode, and an n-type conductive channel having an electron as a carrier is formed in a part of the multi-layer semiconductor layer. In the field effect transistor, the multilayer semiconductor layer includes a p-type semiconductor layer, and a part of the multilayer semiconductor layer from the surface of the multilayer semiconductor layer to at least the p-type semiconductor layer is removed except for a region under the gate electrode. The p-type semiconductor layer is selectively formed immediately below the gate electrode, and the end of the gate electrode in the channel direction is the same as the end of the p-type semiconductor layer or the end of the p-type semiconductor layer. A field effect transistor characterized in that it is exposed to the outside.