JPH05166810A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05166810A
JPH05166810A JP32766391A JP32766391A JPH05166810A JP H05166810 A JPH05166810 A JP H05166810A JP 32766391 A JP32766391 A JP 32766391A JP 32766391 A JP32766391 A JP 32766391A JP H05166810 A JPH05166810 A JP H05166810A
Authority
JP
Japan
Prior art keywords
photoresist
bump
semiconductor device
opening
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32766391A
Other languages
Japanese (ja)
Inventor
Yoshihiko Nemoto
義彦 根本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP32766391A priority Critical patent/JPH05166810A/en
Publication of JPH05166810A publication Critical patent/JPH05166810A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a semiconductor device which is capable of inhibiting the generation of cracks of a photoresist and forming a projected electrode in a stable manner. CONSTITUTION:A bump 6, which serves as a projected electrode to make an electrical connection to the outside, is formed on a semiconductor device 1. This bump 6 is formed in rectangular shape where an angle theta which exceeds 120 deg. is provided at the corners.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置に関し、
特にTAB(TapeAutomated Bonding)技術を用いて電極
の引き出しのために半導体素子上に形成された突起電極
(以下、バンプという)の電極形状に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to an electrode shape of a bump electrode (hereinafter referred to as a bump) formed on a semiconductor element for extracting an electrode by using a TAB (Tape Automated Bonding) technique.

【0002】[0002]

【従来の技術】図5は従来の半導体装置の一例を示す要
部斜視図であり、図において1は半導体素子、2は外部
との電気的接続用としてAu等の金属厚膜で半導体素子
1上に形成されたバンプである。
2. Description of the Related Art FIG. 5 is a perspective view showing an example of a conventional semiconductor device. In the figure, 1 is a semiconductor element and 2 is a thick metal film such as Au for electrical connection to the outside. It is a bump formed on the top.

【0003】つぎに、図6の(a)〜(f)に基づいて
上記従来のバンプ2の形成方法について説明する。ま
ず、図6の(a)に示すように、半導体素子1上に例え
ばTi−W/Auからなる金属膜3を1000Å被覆す
る。ついで、図6の(b)に示すように、フォトレジス
ト4を約25μm被覆する。その後、所望のパターンの
フォトマスク(図示せず)を用いて露光現像を行い、図
6の(c)に示すように、フォトレジスト4にフォトマ
スクのパターンと同等の開口部4aを形成する。この
時、開口部4aは、図7に示すように、矩形形状となっ
ている。さらに、金属膜3を陰極として例えばAuの電
気めっきを行い、図6の(d)に示すように、フォトレ
ジスト4の開口部4aの金属膜3上にバンプ2となるA
uを約20μm析出させる。
Next, a conventional method of forming the bump 2 will be described with reference to FIGS. 6 (a) to 6 (f). First, as shown in FIG. 6A, the metal film 3 made of, for example, Ti—W / Au is coated on the semiconductor element 1 by 1000 Å. Then, as shown in FIG. 6B, the photoresist 4 is coated to a thickness of about 25 μm. After that, exposure and development are performed using a photomask (not shown) having a desired pattern, and as shown in FIG. 6C, an opening 4a equivalent to the pattern of the photomask is formed in the photoresist 4. At this time, the opening 4a has a rectangular shape as shown in FIG. Further, for example, Au is electroplated using the metal film 3 as a cathode to form bumps 2 on the metal film 3 in the opening 4a of the photoresist 4 as shown in FIG.
u is deposited to about 20 μm.

【0004】そこで、図6の(e)に示すように、フォ
トレジスト4を剥離した後、図6の(f)に示すよう
に、露出している金属膜3を除去し、半導体素子1上
に、フォトレジスト4の開口部4aと同等の形状のAu
のバンプ2を形成している。
Therefore, as shown in FIG. 6E, the photoresist 4 is peeled off, and then the exposed metal film 3 is removed as shown in FIG. Of Au having the same shape as the opening 4 a of the photoresist 4.
Bumps 2 are formed.

【0005】ここで、厚膜のバンプ2を形成する際に
は、フォトレジスト4の膜厚はバンプ2の膜厚より厚く
形成する必要があり、10μm以上の膜厚を形成するた
め、フォトレジスト4はゴム系レジストではなく、通常
アクリル系レジストを用いている。
Here, when forming the thick film bumps 2, it is necessary to form the photoresist 4 to be thicker than the bumps 2. Since the film thickness is 10 μm or more, the photoresist is formed. No. 4 does not use a rubber resist, but normally uses an acrylic resist.

【0006】[0006]

【発明が解決しようとする課題】従来の半導体装置は以
上のように、半導体素子1上に矩形形状のバンプ2を形
成していたので、半導体素子1上に形成されたフォトレ
ジスト4の開口部4a内にバンプ2を形成する厚膜の金
属膜を析出させる際に、金属膜の析出成長がフォトレジ
スト4の開口部4aの側壁部分で強制的に阻止されるた
め、開口部4aの側壁部分が押されてフォトレジスト4
の内部に応力が生じ、この応力が開口部4aの角部に集
中して、図8に示すように、フォトレジスト4にクラッ
ク5が発生してしまう。その結果、クラック5に沿って
金属膜が成長してバンプ2間がショートしたり、隣接す
る開口部4a間のフォトレジスト4がめっき工程中に剥
離するという課題があった。
Since the conventional semiconductor device has the rectangular bumps 2 formed on the semiconductor element 1 as described above, the openings of the photoresist 4 formed on the semiconductor element 1 are formed. When depositing a thick metal film for forming the bumps 2 in the bump 4a, the deposition growth of the metal film is forcibly prevented by the side wall portion of the opening 4a of the photoresist 4, so that the side wall portion of the opening 4a is formed. Is pressed and photoresist 4
A stress is generated inside, and this stress concentrates on the corners of the opening 4a, and cracks 5 are generated in the photoresist 4 as shown in FIG. As a result, there is a problem that a metal film grows along the cracks 5 and the bumps 2 are short-circuited, or the photoresist 4 between the adjacent openings 4a is separated during the plating process.

【0007】この発明は、上記のような課題を解決する
ためになされたもので、バンプを析出成長させる際、フ
ォトレジストの開口部の角部におけるクラックの発生を
抑え、バンプ間のショートの発生を防止し、フォトレジ
ストの剥離を防止し、安定してバンプを形成できる半導
体装置を得ることを目的とする。
The present invention has been made in order to solve the above problems. When bumps are deposited and grown, the occurrence of cracks at the corners of the openings of the photoresist is suppressed and shorts between the bumps are generated. It is an object of the present invention to obtain a semiconductor device capable of preventing bumps, preventing the photoresist from peeling, and stably forming bumps.

【0008】[0008]

【課題を解決するための手段】この発明に係る半導体装
置は、半導体素子上に形成される突起電極の形状を、角
部に120°以上の角度の面取りを有する矩形形状とす
るものである。
In the semiconductor device according to the present invention, the shape of the protruding electrode formed on the semiconductor element is a rectangular shape having a chamfered corner of 120 ° or more.

【0009】[0009]

【作用】この発明においては、突起電極の角部に設けら
れた面取りが、突起電極の形成際、突起電極の析出成長
にともなってフォトレジスト内に発生する内部応力の角
部への集中を緩和するように働き、角部への応力集中に
よるフォトレジストのクラックの発生を抑える。
According to the present invention, the chamfer provided at the corner of the bump electrode relaxes the concentration of the internal stress generated in the photoresist at the corner when the bump electrode is formed due to the precipitation growth of the bump electrode. This prevents the photoresist from cracking due to stress concentration on the corners.

【0010】[0010]

【実施例】以下、この発明の実施例を図について説明す
る。 実施例1.図1はこの発明の実施例1を示す半導体装置
の要部斜視図であり、図において図5に示した従来の半
導体装置と同一または相当部分には同一符号を付し、そ
の説明を省略する。図において、6は角部に角度θの面
取り6aが設けられた矩形形状を有し、半導体素子1上
に形成されたバンプである。
Embodiments of the present invention will be described below with reference to the drawings. Example 1. 1 is a perspective view of a main part of a semiconductor device showing a first embodiment of the present invention. In the figure, the same or corresponding parts as those of the conventional semiconductor device shown in FIG. .. In the figure, reference numeral 6 denotes a bump formed on the semiconductor element 1 having a rectangular shape with chamfers 6a having an angle θ at the corners.

【0011】つぎに、上記実施例1の作製方法について
説明する。Ti−W/Auからなる金属膜3が被覆され
た半導体素子1上にフォトレジスト4を被覆した後、所
望のパターンのフォトマスクを用いて露光現像を行い、
図2に示すように、フォトレジスト4の角部に面取り部
4bを有する矩形形状の開口部4aを形成する。つい
で、金属膜3を陰極としてAuの電気メッキを行い、開
口部4aの形状と同等の形状に約20μmのAuを析出
し、その後フォトレジスト4および露出する金属膜3を
剥離除去して、半導体素子1上にバンプ6を形成する。
Next, the manufacturing method of the first embodiment will be described. After coating the photoresist 4 on the semiconductor element 1 coated with the metal film 3 made of Ti-W / Au, exposure and development are performed using a photomask having a desired pattern,
As shown in FIG. 2, a rectangular opening 4a having a chamfered portion 4b is formed at a corner of the photoresist 4. Then, Au is electroplated using the metal film 3 as a cathode to deposit about 20 μm of Au in a shape similar to the shape of the opening 4a, and then the photoresist 4 and the exposed metal film 3 are peeled off to remove the semiconductor. The bump 6 is formed on the element 1.

【0012】ここで、10μm以上の厚膜のバンプ6を
析出形成する場合、バンプ6の面取り6aの角度θを1
20°未満とすると、バンプ6の金属析出成長時に生じ
るフォトレジスト4の内部応力により、フォトレジスト
4の開口部4aの角部にクラックが発生してしまい、ク
ラック5に沿って金属膜が成長してバンプ6間がショー
トしたり、隣接する開口部4a間のフォトレジスト4が
めっき工程中に剥離してしまった。また、バンプ6の面
取り6aの角度θを120°以上とすると、バンプ6の
金属析出成長時に生じるフォトレジスト4の内部応力の
開口部4aの角部への集中が抑えられ、クラック5の発
生を防止できた。
Here, when the bump 6 having a thickness of 10 μm or more is deposited, the angle θ of the chamfer 6a of the bump 6 is set to 1
If the angle is less than 20 °, cracks occur at the corners of the opening 4a of the photoresist 4 due to the internal stress of the photoresist 4 generated during the metal deposition growth of the bump 6, and the metal film grows along the crack 5. As a result, the bumps 6 are short-circuited, or the photoresist 4 between the adjacent openings 4a is peeled off during the plating process. Further, when the angle θ of the chamfer 6a of the bump 6 is 120 ° or more, the concentration of the internal stress of the photoresist 4 generated during the metal deposition growth of the bump 6 on the corners of the opening 4a is suppressed, and the occurrence of the crack 5 is prevented. I was able to prevent it.

【0013】このように、上記実施例1によれば、半導
体素子1上に形成するバンプ6の形状を、角部に120
°以上の角度θの面取り6aを有する矩形形状としてい
るので、10μm厚以上の厚膜のバンプ6形成の際に、
フォトレジスト4の開口部4aの角部への応力集中が低
減され、クラック5の発生が抑えられ、バンプ6間のシ
ョートや電気メッキ工程中のフォトレジスト4の剥離が
なく、安定して厚膜のバンプ6を形成できるという効果
がある。
As described above, according to the first embodiment, the shape of the bump 6 formed on the semiconductor element 1 is 120 at the corner.
Since it has a rectangular shape having a chamfer 6a with an angle θ of not less than °, when forming bumps 6 of a thick film having a thickness of 10 μm or more,
Stress concentration at the corners of the opening 4a of the photoresist 4 is reduced, the occurrence of cracks 5 is suppressed, and there is no short circuit between the bumps 6 or peeling of the photoresist 4 during the electroplating process, and a stable thick film is obtained. The bump 6 can be formed.

【0014】実施例2.上記実施例1では、バンプ6の
形状を角部に面取り6aを有する矩形形状とするものと
しているが、この実施例2では、図3および図4に示す
ように、バンプ6の形状を角部に円弧6bを有する矩形
形状とするものとし、同様の効果を奏する。
Example 2. In the first embodiment, the bump 6 has a rectangular shape with chamfers 6a at the corners. However, in the second embodiment, as shown in FIGS. 3 and 4, the bump 6 has a corner shape. A rectangular shape having an arc 6b at the center is provided, and the same effect is obtained.

【0015】[0015]

【発明の効果】以上のようにこの発明によれば、半導体
素子上に形成する突起電極の形状を、角部に120°以
上の角度の面取りを有する矩形形状としているので、半
導体素子上に突起電極を形成する際に、フォトレジスト
の開口部の角部でのクラックの発生が抑えられ、突起電
極形成工程中でのフォトレジストの剥離やクラックに沿
った金属膜の析出成長による突起電極間のショートが防
止できる半導体装置が得られる効果がある。
As described above, according to the present invention, since the shape of the protruding electrode formed on the semiconductor element is a rectangular shape having a chamfer at an angle of 120 ° or more, the protruding electrode is formed on the semiconductor element. During the formation of electrodes, the generation of cracks at the corners of the photoresist opening is suppressed, and the peeling of the photoresist during the process of forming the bump electrodes and the gap between the bump electrodes due to the deposition growth of the metal film along the cracks occur. There is an effect that a semiconductor device capable of preventing a short circuit can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例1を示す半導体装置の要部斜
視図である。
FIG. 1 is a perspective view of a main part of a semiconductor device showing a first embodiment of the present invention.

【図2】この発明の実施例1を示す半導体装置における
フォトレジストの開口部の平面図である。
FIG. 2 is a plan view of an opening of a photoresist in the semiconductor device showing the first embodiment of the present invention.

【図3】この発明の実施例2を示す半導体装置の要部斜
視図である。
FIG. 3 is a main part perspective view of a semiconductor device showing a second embodiment of the present invention.

【図4】この発明の実施例2を示す半導体装置における
フォトレジストの開口部の平面図である。
FIG. 4 is a plan view of an opening of a photoresist in a semiconductor device showing a second embodiment of the present invention.

【図5】従来の半導体装置の一例を示す要部斜視図であ
る。
FIG. 5 is a main part perspective view showing an example of a conventional semiconductor device.

【図6】(a)〜(f)はそれぞれ従来の半導体装置に
おける突起電極の形成方法を示す工程断面図である。
6A to 6F are process cross-sectional views showing a method of forming a protruding electrode in a conventional semiconductor device.

【図7】従来の半導体装置におけるフォトレジストの開
口部を示す平面図である。
FIG. 7 is a plan view showing an opening of a photoresist in a conventional semiconductor device.

【図8】従来の半導体装置におけるバンプ形成時のクラ
ック発生状態を示す平面図である。
FIG. 8 is a plan view showing a state in which a crack is generated during bump formation in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子 6 バンプ(突起電極) 6a 面取り 6b 円弧(面取り) 1 semiconductor element 6 bump (protruding electrode) 6a chamfer 6b arc (chamfer)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子上に突起電極が形成されてな
る半導体装置において、前記突起電極は、角部に120
°以上の角度の面取りを有する矩形形状であることを特
徴とする半導体装置。
1. A semiconductor device in which a protruding electrode is formed on a semiconductor element, wherein the protruding electrode is 120 at a corner.
A semiconductor device having a rectangular shape having a chamfer at an angle of ° or more.
JP32766391A 1991-12-11 1991-12-11 Semiconductor device Pending JPH05166810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32766391A JPH05166810A (en) 1991-12-11 1991-12-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32766391A JPH05166810A (en) 1991-12-11 1991-12-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05166810A true JPH05166810A (en) 1993-07-02

Family

ID=18201580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32766391A Pending JPH05166810A (en) 1991-12-11 1991-12-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05166810A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220013484A1 (en) * 2020-07-08 2022-01-13 Beijing Xiaomi Mobile Software Co., Ltd. Chip, circuit board and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220013484A1 (en) * 2020-07-08 2022-01-13 Beijing Xiaomi Mobile Software Co., Ltd. Chip, circuit board and electronic device

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