JPH05165634A - Instruction prefetch device - Google Patents

Abstract

PURPOSE:To accelerate the execution of a branching instruction and to improve memory indexing efficiency by supplying a branching NoGo word in an instruction prefetch buffer to the next stage when the prediction of branching Go is failed. CONSTITUTION:When the branching Go prediction of the branching instruction is executed and a branch predictive destination address is generated, a conventionally abandonned instruction on the side of branching NoGo is held at a word continued to a branching Go predicting word in an instruction prefetch buffer 14. When it is judged that the prediction of branching Go is failed, the instruction held at the word continued to the branching Go predicting word in the instruction prefetch buffer 14 is supplied to a DC (instruction decode) stage and for the address of an IFA (instruction access) stage, the address of a word following to the branching NoGo word is generated by an address recovery function 16 and set to an instruction extracting address register 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetching apparatus, and more particularly to an instruction prefetching method for an information processing apparatus that employs a pipeline processing method for prefetching instructions using branch prediction means.

[0002]

2. Description of the Related Art Conventionally, in a pipeline processing type information processing apparatus having an instruction prefetching function of this kind of branch predicting means, a branch predicting means such as a branch prediction table or the like prefetches an instruction and, as a result, a branch instruction is executed. It is designed to run fast.

Such a system is disclosed in Japanese Patent Publication No. 50-22384.
JP-A-55-99655, JP-A-57-
It has been proposed in Japanese Patent No. 59253, etc., and has already been implemented in some information processing apparatuses.

According to these methods, a history of execution results is held for each branch instruction, and the history information (branch taken / not taken, Reflect the branch destination address),
It is designed to effectively execute instruction prefetch.

That is, such a method has an effect that a branch instruction can be executed at a high speed as long as the prediction of the instruction prefetch is appropriate.

In general, an information processing apparatus based on a pipeline control system divides an instruction execution phase into each stage described below, provides hardware for performing the function of each stage, and each instruction sequentially executes each stage cycle. It is controlled so that the instructions can be executed in every stage in a single stage cycle.

IF stage (instruction prefetch stage) A stage for fetching an instruction from a memory by an instruction fetch address.

DC stage (instruction decoding stage) A stage in which an instruction is read into the instruction register and the type of the instruction is decoded.

AD stage (address generation stage) This is a stage for generating an address required by the instruction. If it is a branch instruction, a branch destination address to which the branch instruction actually branches is generated.

OF stage (operand fetch stage) A stage for fetching an operand used for an operation.

EX stage (arithmetic stage) This is a stage for executing an arithmetic operation. In the case of a branch instruction, it is decided at this stage whether or not the branch is taken.

Further, the IF (instruction fetching) stage particularly related to the present invention is composed of a plurality of stages, and is generally divided into the following stages (which may be divided into smaller stages).

IFA stage (instruction access stage) A stage for fetching an instruction from a memory by an instruction fetch address and storing it in an instruction buffer, and at the same time a stage for indexing a branch prediction function by an instruction fetch address to generate a branch prediction destination address. ..

IFB stage (instruction supply stage) A stage for supplying the instruction of the instruction buffer to the instruction register of the next DC stage, and at the same time, supplying the branch prediction destination address generated by the branch prediction function to the IFA stage.

FIG. 3 shows the structure of a conventional IF stage.
The instruction fetch register 11 holds the address of the instruction to be prefetched, and the instruction memory 12 and the branch prediction function 13 are simultaneously indexed by this address. At the same time, the counter 17 generates the address of the subsequent instruction and sets it in the instruction fetch address register 11.

An instruction from the instruction memory 12 (this memory may be a main memory or a cache memory) is stored in the instruction prefetch buffer 14 and supplied to the DC stage. At the same time, branch prediction is performed by the branch prediction function 13 to generate a branch prediction destination address, which is set in the branch prediction destination address register 15.

In the case of branch Go prediction, the branch prediction destination address is set in the instruction fetch address register 11 from the branch prediction destination address register 15 and the prediction destination instruction is fetched. The address recovery function 16 sets a new address for fetching an instruction in the instruction fetch register 11 when the branch prediction fails.

In the conventional instruction prefetch system shown in FIG. 3,
When executing the instruction sequence shown in FIG. 4, the branch prediction of the branch instruction D is performed at the IFB stage as shown in FIG.
By the time the instructions L and M of the branch prediction destination address 100 generated in the FB stage are fetched, the instructions E and F on the branch Go side that have already fetched the instruction are discarded as invalid instructions. Therefore, there is a drawback that the indexing efficiency of the memory is reduced and the instruction supply capability is reduced.

Further, when the branch instruction D of the instruction sequence shown in FIG. 4 is predicted to branch Go and the branch prediction fails and it is determined to be branch NoGo, execution of the branch instruction D is 6T as shown in FIG.
Therefore, regarding the instruction E on the NoGo side, the timing T
In 3, the instruction is on the NoGo side even though it is fetched from the memory 12 and therefore is discarded.

When it is determined to be NoGo by executing the branch instruction D, the instruction E on the NoGo side is fetched again, so the instruction fetch operation is executed twice for the same instruction, and the instruction fetch memory There is a drawback that the index efficiency is reduced and the instruction supply capability is reduced.

Execution T number (6T) of the branch instruction shown in FIG.
As a method of reducing the above, there is a method of activating an instruction fetch in the direction opposite to the prediction when the branch destination address of the branch instruction D is determined in the AD stage as shown in FIG.

The number T of executions of the branch instruction D is 4T, but since the instruction fetch in the opposite direction to the prediction is performed without waiting for the execution result of the branch instruction D, if the prediction for the branch instruction D succeeds, The instruction fetch operation in the direction opposite to the prediction is stopped, and the prefetch in the prediction direction is continued.

However, prefetching in the prediction direction is interrupted by the instruction fetching operation in the direction opposite to the prediction, so that the memory indexing efficiency is lowered and the instruction supply capability is lowered. Further, as described above, the instruction fetch operation is executed twice for the instruction E on the NoGo side, the index efficiency of the memory is similarly reduced, and the instruction supply capability is reduced.

[0024]

SUMMARY OF THE INVENTION An object of the present invention is to provide an instruction prefetching device capable of speeding up the execution of a branch instruction when a branch Go prediction fails and improving the memory index efficiency to improve the instruction supply capability. is there.

[0025]

The instruction prefetching apparatus according to the present invention fetches an instruction from the memory by the address of the instruction fetch address register and stores it in the instruction prefetch buffer, and at the same time indexes the branch prediction means by the address to generate a branch predicted address. A pipeline having an instruction prefetch stage consisting of one stage and a second stage for supplying the instruction of the instruction prefetch buffer to the instruction decode stage of the next stage and at the same time supplying the branch prediction destination address to the instruction fetch address register. An instruction prefetching device in an information processing apparatus of a processing system, including a branch instruction predicted to branch Go by the branch prediction means when storing an instruction word including a branch instruction read from a memory in the instruction prefetching buffer. Store an instruction word in the instruction prefetch buffer, Means for continuously storing and controlling an instruction word including an instruction in the branch NoGo direction of the branch instruction as a branch NoGo word in the instruction prefetch buffer, and the branch Go predicted branch instruction is executed to cause branch prediction failure and branch When it is determined to be NoGo, the instruction of the branch NoGo word stored in the instruction prefetch buffer is supplied to the instruction decoding stage, and subsequent instruction prefetch is controlled to start from the subsequent word of the branch NoGo word. And means.

[0026]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same portions as those in FIG. 3 are designated by the same reference numerals. In this example, the register 19 that stores the branch prediction destination address of the branch NoGo word, the register 19 and the register 15
And a selection circuit 18 for selecting the output of and to supply it to the instruction fetch address register 11.

The instruction fetch address register 11 holds the address of the instruction read from the memory 12,
The holding address 2 is supplied to the memory 12, the branch prediction function 13, and the counter 17, respectively.

Instructions are read from the instruction memory 12 in units of instruction words (for example, if one instruction is 4 bytes and one word is 8 bytes, two instructions can be fetched by one read operation from the instruction memory 12), and instruction prefetching is performed. It is stored in the buffer 14. In the same cycle, the branch prediction function 13 is indexed, and in the case of branch Go prediction, when the branch prediction destination address is generated, it is set in the branch prediction destination address register 15.

In the same cycle, the instruction fetch address is added by 8 bytes to fetch the subsequent word by the counter 17 and set in the instruction fetch address register 11.

When the branch Go prediction is performed by the above operation, the instruction prefetch buffer 14 stores an instruction string of words including a branch instruction, and the branch prediction destination address register 15 stores the branch Go predicted branch. The branch prediction destination address for the instruction is set, and the instruction fetch address register 11 stores the subsequent word of the word including the branch instruction predicted to branch Go, that is, N of the branch instruction.
The address of the word containing the instruction in the oGo direction is set. In the next cycle, the instruction stored in the instruction prefetch buffer 14 is supplied to the DC stage.

The branch prediction destination address set in the branch prediction destination address register 15 in the same cycle is set in the instruction fetch address register 11 via the selection circuit 18. The branch NoGo word is read from the instruction memory 12 by the address of the branch NoGo word set in the instruction fetch address register 11 in the same cycle, and held in a word continuous to the branch Go predicted word in the instruction buffer shown in FIG. To be done. After the next cycle, the instruction fetching is continued from the branch prediction destination address set in the instruction fetching address register 11, and the instruction fetching buffer 14 supplies the instruction according to the prediction to the DC stage.

When the branch instruction is executed, the branch prediction fails, and it is determined to be the branch NoGo, the branch NoGo side held in the word consecutive to the branch Go predicted word in the instruction buffer shown in FIG. 2 is held. Is supplied to the DC stage.

In the same cycle, the address recovery function 1
6 generates the address following the branch NoGo word,
It is set in the instruction fetch address register 11. After the next cycle, the instruction fetch is continued from the address subsequent to the branch NoGo word set in the instruction fetch address register 11 and stored in the instruction prefetch buffer 14.

When the instruction sequence shown in FIG. 4 is executed by the above operation, it becomes as shown in FIG. In FIG. 7, when the branch instruction D is predicted to branch Go at timing T2 and a branch prediction target address is generated, the instructions E and F on the branch NoGo side that were conventionally discarded at timing T3 are the instructions shown in FIG. It is held in words that follow the branch Go prediction word in the prefetch buffer.

When it is determined that the branch Go prediction has failed at the timing T8, the instruction E held in the word succeeding the branch Go prediction word in the instruction prefetch buffer shown in FIG. 2 for the DC stage at the timing T9. 1, the address of the IFA stage is generated by the address recovery function 16 of FIG. 1 to generate the address of the word following the branch NoGo word, and is set in the instruction fetch address register 11 of FIG.

Therefore, as shown in FIG. 7, the number of executions T of the branch instruction D is 4T, and the memory access to the instructions E and F on the branch NoGo side is only required once. Further, even if the method of activating the instruction fetch in the opposite direction to the prediction when the branch destination address is determined in the AD stage of the branch instruction described above with reference to FIG. Moreover, the unnecessary instruction fetching operation is not necessary, and the memory index efficiency is improved.

Next, regarding the operation using the branch prediction destination address holding register 19 of the branch NoGo word of FIG.
Only the parts that are different from the above-described operation example will be described in detail.

Referring to FIG. 1, in the same cycle in which the branch Go prediction is performed and the branch NoGo word is set in a word following the branch Go prediction word in the instruction prefetch buffer shown in FIG. 2, the branch NoGo word is set. Also, the branch prediction is performed by the branch prediction function 13. Therefore, when a branch instruction exists in the branch NoGo word and the branch Go is predicted, the branch prediction function 13 generates a branch prediction destination address for the branch instruction in the branch NoGo side word. The branch prediction destination address is held in the branch prediction destination address holding register 19 of the branch NoGo word.

When the branch prediction fails and it is determined to be the branch NoGo, the instruction on the branch NoGo side is supplied from the word consecutive to the branch Go predicted word in the instruction prefetch buffer shown in FIG. In the same cycle, from the branch prediction destination address holding register 19 of the branch NoGo word, branch N
The branch prediction destination address for the branch instruction of the oGo word is given to the selection circuit 18, and this address is selected by the selection circuit 18 and set in the instruction fetch address register 11. As a result, prefetching of the instruction of the branch prediction destination address for the branch instruction in the branch NoGo word is started.

Therefore, the branch prediction is effective for the branch instruction existing in the branch NoGo word, the branch prediction rate is improved, and the function relating to the instruction prefetching can be effectively used.

FIG. 9 shows the result of execution of the instruction sequence shown in FIG. 8 in the first embodiment, and FIG. 1 shows the result of execution in the second embodiment.
0 is shown respectively.

The branch instruction B of FIG. 8 is predicted to branch Go, and the branch instruction D is a NoGo-side instruction of the branch instruction B. Instruction B failed in branch prediction, resulting in NoG
The case where the branch instruction D becomes o and the branch instruction D becomes the result Go will be described.

When the instruction shown in FIG. 8 is executed in the execution state as described above, in the first embodiment, as shown in FIG. 9, at the timing T2, the branch to the branch instruction D in the branch NoGo word is executed. Although the predicted address is generated, it is discarded because it has no means for holding it.

Therefore, when the branch instruction B fails the branch prediction and the result is NoGo, the branch instruction D is treated as the branch NoGo prediction at timing T11 because the branch prediction destination address does not exist, and the branch NoGo prediction failure occurs. Therefore, it takes 6T to execute.

The second embodiment solves the above-mentioned problem, and as shown in FIG. 10, at timing T2, the branch prediction destination address for the branch instruction D in the branch NoGo word is not discarded and the branch prediction destination address shown in FIG. By holding the branch NoGo word of the branch NoGo word in the branch prediction destination address holding register 19, the branch prediction for the branch instruction D in the branch NoGo word is possible.

When it is determined that the branch instruction B fails in branch Go prediction at timing T6, at timing T7, the branch in the branch NoGo word held in the branch prediction destination address register 19 of the branch NoGo word in FIG. 1 is branched. The branch prediction destination address for the instruction D is given to the selection circuit 18 and set in the instruction prefetch address register 11 by the selection circuit 18.

Therefore, the branch prediction for the branch instruction D in the NoGo word becomes valid, the branch Go prediction succeeds at the timing T11, and the execution of the branch instruction D is performed at 1T.

[0049]

As described above, according to the present invention,
When the branch Go prediction fails, it is possible to speed up the execution of the branch instruction and improve the memory index efficiency to improve the instruction supply capability.

Further, there is an advantage that the increase in the amount of hardware is small, and further, since the word in the instruction buffer does not have a fixed area for the branch NoGo word,
There is also an advantage that it can be effectively used unless branch Go prediction is performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an instruction storage format inside an instruction prefetch buffer.

FIG. 3 is a block diagram of a conventional instruction prefetching device.

FIG. 4 is a diagram showing an example of an instruction sequence having a branch instruction.

FIG. 5 is a time chart showing an example of execution progress when branch Go prediction by the conventional method fails in prediction.

FIG. 6 is a time chart showing another example of the execution process when the branch Go prediction by the conventional method fails in prediction.

FIG. 7 is a time chart showing an execution process when branch Go prediction fails in prediction according to the first embodiment of the present invention.

FIG. 8 is a diagram showing an instruction sequence used in an embodiment of the present invention.

FIG. 9 is a time chart showing a process of executing the instruction sequence of FIG. 8 according to the first embodiment.

FIG. 10 is a time chart showing a process of executing the instruction sequence of FIG. 8 according to the second embodiment.

[Explanation of symbols]

11 instruction fetch address register 12 instruction memory 13 branch prediction function 14 instruction prefetch buffer 15 branch prediction destination address register 16 address recovery function 17 counter 18 selection circuit 19 branch NoGo word branch prediction destination address register

Claims (2)

[Claims] 1. A first stage for fetching an instruction from a memory by an address of an instruction fetch address register and storing it in an instruction prefetch buffer, and at the same time indexing a branch prediction means by the address to generate a branch predicted address.
Information processing in a pipeline processing system having an instruction prefetch stage consisting of a second stage for supplying the instruction of the instruction prefetch buffer to the next instruction decoding stage and at the same time supplying the branch prediction destination address to the instruction fetch address register An instruction prefetching device in the device,
When the instruction word including the branch instruction read from the memory is stored in the instruction prefetch buffer, the instruction word including the branch instruction predicted to branch Go by the branch predicting unit is stored in the instruction prefetch buffer, and then the instruction word is stored. Branch No. of the branch instruction Branch No to the instruction word containing the Go direction instruction
Means for successively controlling storage in the instruction prefetch buffer as a Go word and stored in the instruction prefetch buffer when the branch Go predicted branch instruction is executed and branch prediction fails and branch NoGo is determined. Means for supplying an instruction of said branch NoGo word to the instruction decoding stage and controlling subsequent instruction prefetching to start from a subsequent word of said branch NoGo word. 2. A branch prediction target address register for storing a branch target address of a branch instruction predicted to branch Go by the branch prediction unit, and a branch NoGo word predicted by the branch prediction unit. 7. A branch NoGo word branch prediction destination address register for holding a branch prediction destination address for an existing branch instruction, and means for selecting outputs of these two registers and storing them in the instruction fetch register. 1. The instruction prefetching device described in 1.