JPH05164821A - Failure diagnostic circuit and its diagnostic method - Google Patents

Abstract

PURPOSE:To provide a failure diagnostic circuit and its diagnostic method able to improve failure detecting ability in failure diagnosis and to facilitate failure diagnosis. CONSTITUTION:A failure diagnostic circuit consists of a large scale logic circuit, and on a lattice of which constructed with signal applying lines from a shift resistor controlled by a controller, signal observing lines and selection signal lines cells are arranged. For instance, input pins 61, 62 and output pins 71, 72 on an arbitrary cell 51 are connected to an actual logic section 52 through cutoff switches 81-84 with no effect to or from other cells. And signal applying lines 21, 22 and signal observing lines 31, 32 are connected between cutoff switches 81-84 and the actual logic section 52 of the cell 51 through switches 91-94 turned on or off by signals from a selection signal line 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for diagnosing a fault in a logic circuit, and particularly in a fault diagnosing a large-scale logic circuit, a fault diagnosing circuit and a diagnosing method therefor capable of facilitating the diagnosing and improving the detecting ability. Related to effective technology.

[0002]

2. Description of the Related Art Conventionally, as a measure for improving fault detection capability in fault diagnosis, probe lines and sense lines are wired on a grid and test points are provided at each intersection.
By addressing that test point,
Some improve the observability of the internal signals of the circuit. Further, the controllability of an internal signal is improved by writing a signal to a memory element at a test point by using this addressing technique.

As a technique similar to this, for example, "1991 ACM28th ACM / IEEE D
design Automation Conference
ce Paper18.3 p282-p286 "and the like.

[0004]

However, in the prior art as described above, it is necessary to generate a test and to perform a failure simulation for each target logic circuit, which requires a long time to generate diagnostic data and a storage element. It takes a long time to initialize / set and read internal signals, and there is a problem that only low-speed diagnosis can be performed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems and to provide a failure diagnosis circuit and a diagnosis method thereof suitable for improving the failure detection capability in failure diagnosis.

Another object of the present invention is to reduce the number of steps for creating diagnostic data by using a diagnostic circuit, to eliminate the need for test generation and fault simulation for each target logic circuit, or to facilitate diagnosis by reducing the load. It is to provide a failure diagnosis circuit and a diagnosis method therefor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the fault diagnostic circuit of the present invention is a fault diagnostic circuit for a logic circuit composed of a single cell or a plurality of cells, and selecting means for selecting an arbitrary cell from the single cell or a plurality of cells, and the selection means. And a cutoff means for cutting off an output signal from the cell selected by the means to another cell and an input signal from the other cell.

Another fault diagnosis circuit of the present invention is a selection means for selecting an input pin of an arbitrary cell from the one or more cells, and a signal on the same line as the input pin of the cell selected by the selection means. A blocking means for blocking a signal between the application line and the signal observation line is provided.

Furthermore, the diagnostic method of the fault diagnostic circuit of the present invention diagnoses only cells having low controllability and observability.

Also, Another method of diagnosing a failure diagnosis circuit of the present invention is to make a diagnosis using diagnosis data that is made into a library according to the type of cell.

[0013]

According to the above-mentioned failure diagnosis circuit, the selection means and the cutoff means are provided, so that an arbitrary cell is selected and the influence on other cells is cut off, and the selected cells are simultaneously input. Apply a signal for failure diagnosis to the pin,
Moreover, the signal of the diagnosis result can be observed at the output pin.

That is, a signal application line for applying a signal for fault diagnosis to a logic circuit, a signal observation line for observing a signal, and a selection signal line as a selection means for selecting a cell to be diagnosed are wired. Then, connect the input / output pins of the cell to be diagnosed to the signal application line and the signal observation line, respectively, with a switch that is made conductive / non-conductive depending on the signal of the selection signal line,
This can be achieved by providing the cell to be diagnosed with a cutoff switch which is a cutoff means for invalidating a signal to another cell and a signal from another cell.

Then, by sending a signal to the selection signal line, the input pin and the signal application line of the cell and the output pin and the signal observation line are electrically connected by the switch, and the test pattern can be input and output from the signal application line and the signal observation line. Then, the signals from other cells are cut off, and the failure diagnosis of the selected cell can be performed independently. This improves the fault detection capability.

According to the above-mentioned other failure diagnosis circuit, the selection means and the interruption means are provided,
A signal entering an input pin of an arbitrary cell can be observed through a signal observation line, and at the same time, an arbitrary signal can be applied through the signal application line.

That is, a signal application line for applying a signal for fault diagnosis to a logic circuit, a signal observation line for observing a signal, and a selection signal line as a selection means for selecting a cell input pin are wired. Then, connect the signal input line and the signal observation line to the input pin of the cell in order from the real logic side of the cell with the switch that is turned on / off by the signal of the selection signal line, and connect the signal input line on the same input pin. Also, it is achieved by providing a switch that is a blocking means capable of blocking a signal between the signal observation lines.

Then, by sending a signal to the selection signal line, the input pin and the signal application line of the cell, the output pin and the signal observation line are made conductive by the switch, and the signal between the signal application line and the signal observation line is cut off to observe the signal. It is possible to observe signals sent from other cells from the line, and to apply arbitrary signals from the signal application line, and observe and apply signals at points where signal controllability and observability are poor. You can This improves the fault detection capability.

Further, according to the above-mentioned method for diagnosing a failure diagnosis circuit, the diagnosis circuit is applied only to cells having poor controllability and observability, so that the overhead of the diagnosis circuit can be kept low and the failure detection capability can be reduced. Can be improved.

Further, according to the above-mentioned other diagnosis method of the failure diagnosis circuit, the diagnosis data of the single cell is registered in the library for each kind of the cells forming the logic, so that the failure simulation and the preparation of the diagnosis data are unnecessary. It is possible to reduce man-hours in the logic design stage of diagnosis.

[0021]

[First Embodiment] FIG. 1 is an overall configuration diagram showing a failure diagnosis circuit having a built-in diagnosis circuit that enables diagnosis in cell units, which is an embodiment of the failure diagnosis circuit and the diagnosis method of the present invention. In the present embodiment, a detailed view showing a diagnostic circuit in the diagnosis target cell, FIG. 3 is a detailed view showing a cutoff switch between the diagnosis target cell and another cell, and FIG. 4 is a configuration showing a modification of the cutoff switch in the present embodiment. FIG. 5 and FIG. 5 are configuration diagrams showing a case where the cutoff switch for the cell to be diagnosed and another cell is arranged only on the output pin side of the circuit.

First, the configuration of the failure diagnosis circuit of this embodiment will be described with reference to FIG.

The failure diagnosis circuit of this embodiment is, for example, a failure diagnosis circuit of a large-scale logic circuit, and shift registers 11 and 12 controlled by a controller 10 are arranged.
A signal applying line 20 and a signal observing line 30 coming out of the shift register 11 and a selection signal line (selecting means) 40 coming out of the shift register 12 are wired in a grid shape, and a plurality of cells 50 are arranged on this grid.

The signal application line 20 is a signal line for applying a signal for failure diagnosis to the logic circuit, and a signal of a diagnosis result by the applied signal is observed through the signal observation line 30. In this case, the selection signal An arbitrary cell 50 to be diagnosed is selected from the plurality of cells via the line 40.

For example, the connection of the cell 50 to be diagnosed and the signal application line 20, the signal observation line 30 and the selection signal line 40 is shown in detail in FIG.
The input pins 61, 62 and the output pins 71, 72 of No. 1 sandwich the cut-off switches (cut-off means) 81-84 which can cut the influence on other cells and the influence from other cells, and the real logic unit 5
Wired to 2. Further, the signal application lines 21 and 22 and the signal observation lines 31 and 32 are made conductive / non-conductive between the cutoff switches 81 to 84 and the real logic part 52 of the cell 51 by the signal of the selection signal line 41. Wired with a pinch in between.

Next, the operation of this embodiment will be described.

First, the signal from the selection signal line 41 activates the breaking switches 81 to 84 and the switches 91 to 94.
For example, when a signal is sent to the selection signal line 41 by the shift register 12, the cutoff switches 81 to 84 are turned off, the cell 51 to be diagnosed is isolated from other cells, and at the same time, the switches 91 to 94 are turned on. The input pins 61, 62 and the output pins 71, 72 of 51 are all electrically connected to the signal application lines 21, 22 and the signal observation lines 31, 32.

In this state, the shift register 11 applies a test pattern through the signal application lines 21 and 22,
Fault diagnosis is performed by observing the output signal through the signal observation lines 31 and 32. Here, the same selection signal line 4
The cells above one are diagnosed in parallel, but it is also possible to diagnose only one cell.

Next, the cut-off switches 81 to 84 for cutting off the cell 51 to be diagnosed from other cells are shown in detail in FIG.
Normally, the cutoff switches 81 to 84 are in the on state and the real logic unit 52 is connected to another cell.

However, the cutoff switches 81 to 84 are turned off by the signal from the selection signal line 41, and the real logic section 52 is isolated from other cells. Therefore, the influence of signals from the signal application lines 21 and 22 on other cells and the influence of signals from other cells to the signal observation lines 31 and 32 can be blocked.

Therefore, according to the failure diagnosis circuit of this embodiment, the signal application lines 21 and 22, the signal observation lines 31 and 32, and the selection signal line 41 are wired, and the cut-off switches 81 to 84 are used to identify the cell 51 to be diagnosed. Since the test pattern can be applied from the signal application lines 21 and 22 and the output signal can be observed by the signal observation lines 31 and 32 by cutting off from the other cells, the real logic unit 52 in the selected cell 51. The failure diagnosis can be performed independently.

Regarding the cutoff switches 81 to 84, for example, as shown in FIG. 3, the diagnosis target cell 51a is cutoff switches 81a to 84a using tristate elements.
It is also possible to cut off by the signal from the selection signal line 41a in this case as well, so that the tristate element is disabled and the influence on other cells and the influence from other cells are cut off, and the tristate element is cut off by itself. Fault diagnosis of the logic unit 52a becomes possible.

When a plurality of cells 50 are to be diagnosed in parallel, for example, as shown in FIG.
1b and cut-off switches 81b to 84b on the output pin side of the cell 53b preceding this cell 51b, and the selection signal line 4
The interruption switches 81b to 84b are activated by the signal from the 1b, and the interruption switches 81b to 84b are activated by the cells 51b and 5b.
The parallel diagnosis of the real logic part 52b of the cell 51b is also possible by installing only the output pin side of 3b.

[0034]

[Embodiment 2] FIG. 6 shows another embodiment of the fault diagnosing circuit and the diagnosing method thereof according to the present invention, which is to observe a signal at an input pin of a cell.
It is a block diagram which shows the failure diagnostic circuit which contained the diagnostic circuit which applies and a signal.

The failure diagnosis circuit of this embodiment is a failure diagnosis circuit for a large-scale logic circuit as in the first embodiment, and the signal application lines 21c and 22c and the signal observation line output from the shift register 11 controlled by the controller 10 are used. 31c, 32
c and the selection signal line (selection means) 41c output from the shift register 12 are arranged in a cell 51c on a lattice. The difference from the first embodiment is that the input pin of any cell is selected and the input pin of this cell is selected. Is the point at which observation and application are performed.

That is, in the failure diagnosis circuit of this embodiment, as shown in FIG. 6, the signal input to the input pins 61c and 62c of the cell 51c is observed and the input pins 61c and 62c are observed.
The input pins 61c and 62c of the cell 51c are connected to the real logic section 52c of the cell 51c.
In order from the side, the signal application lines 21c and 22c and the signal observation lines 31c and 32c are connected with the switches 91c to 94c interposed therebetween, and the signals between the signal application lines 21c and 22c and the signal observation lines 31c and 32c are connected to each other. Cutoff switches 81c, 82c for cutting off are arranged.

Then, the signal from the selection signal line 41c is
Cutoff switches 81c and 82c and switches 91c to 94c
To start. For example, when a signal is sent to the selection signal line 41c, the cutoff switches 81c and 82c are turned off, the switches 91c to 94c are turned on, and the input pins 61c and 62c of the cell 51c are connected to the signal application lines 21c and 22c and the signal observation line. It is possible to conduct with 31c and 32c and to disconnect the real logic part 52c from the input of other cells.

Therefore, according to this embodiment, the signal observation line 3
Fault diagnosis can be performed by observing an internal signal that has been difficult to observe in the past through 1c and 32c, and by applying an internal signal that is difficult to control through the signal applying lines 21c and 22c.

[0039]

[Third Embodiment] FIG. 7 is a still further embodiment of the fault diagnosing circuit and the diagnosing method thereof according to the present invention, in which a diagnosing circuit capable of diagnosing in a cell unit is applied to a part of cells of all circuits. It is a block diagram which shows a circuit.

The failure diagnosis circuit of this embodiment is a failure diagnosis circuit for a large-scale logic circuit as in the first and second embodiments, and shift registers 11d and 12d controlled by a controller 10d are arranged as shown in FIG. The signal application line 20d and the signal observation line 3 which are output from the shift register 11d.
0d, a selection signal line (selection means) 40d output from the shift register 12d is wired in a grid, and a plurality of cells 50d having poor controllability and observability are arranged on the grid.
The difference from the first and second embodiments is that a diagnostic circuit is built only in a cell having poor controllability and observability for diagnosis.

That is, in the fault diagnosis circuit of this embodiment, first, the controllability and observability of each cell are calculated from the logic design data, and the above-mentioned operation is performed on the cell 50d having poor controllability and observability. As described above, a diagnostic circuit capable of observing the signal of the input pin of the cell 50d and simultaneously applying the signal to the input pin of the cell 50d is built. Then, the shift registers 11d and 12d controlled by the controller 10d
And the signal application line 2 which is output from the shift register 11d.
0d, the signal observation line 30d, and the selection signal line 40d output from the shift register 12d are wired to the cell 50d.

Diagnosis is performed by combining the circuit created as described above with a conventionally used diagnosis method. That is, during the diagnosis by the conventionally used diagnosis method, the signal is applied and observed by the diagnostic circuit incorporated in the cell 50d in the region where it is difficult to control and observe from the edge pin. The cell 50d serves both as an output edge pin for observing a signal reaching the cell 50d from the input edge pin and as an input edge pin for applying a signal up to the output edge pin.

Therefore, according to the method of this embodiment, the controllability and the observability can be improved by placing the cell 50d at a point where the signal line in the region where the observation is difficult converges. The detection ability can be improved.

Further, when the cells which can be diagnosed by the cell according to the first and second embodiments are used, all the circuits are diagnosed by the conventionally used diagnostic method, and then the control and the observation are difficult, so that the failure occurs. It is possible to make a final diagnosis result by integrating the diagnosis result of this whole circuit and the diagnosis result of the cell itself by diagnosing the cell in the area where the detection rate is bad. ..

[0045]

[Fourth Embodiment] FIG. 8 shows a data flow of a diagnostic method having a diagnostic data of a diagnostic circuit as a library, which is another embodiment of the fault diagnostic circuit and the diagnostic method of the present invention, which is capable of diagnosing in a cell unit. It is a block diagram shown.

The failure diagnosis circuit of this embodiment is the same as the first and second embodiments.
Similar to the above items 3 and 3, it is used as a failure diagnosis circuit for a large-scale logic circuit, and as shown in FIG. 8, a data table showing the cell type and the positions of the signal application line, the signal observation line, and the selection signal line with the position of the component cell as a key. 101 and signal application line data 102,
Signal observation line data 103 and selected signal line data 104
have. Separately from this, the diagnostic data 105 for each cell type is held as a circuit common data library. The diagnostic data may be, for example, the same format as that conventionally created for each LSI, created in cell units.

Then, the signal application line, the signal observation line and the selection signal line pointer in the data table 101 respectively indicate the signal application line, the signal observation line and the selection signal line used for diagnosing the cell. 102, the signal observation line data 103, and the selected signal line data 104 are searched (steps 801, 802, 803). further,
The diagnostic data of the cell type is the diagnostic data of the library 10
5 is read (step 804), and the diagnosis is performed using the signal application line, the signal observation line, and the selection signal line, which are indicated by this.

That is, when the logic is designed by using the cell as a component, the internal structure of the cell remains unchanged regardless of the type of logic circuit. Therefore, it is possible to create in advance an input test pattern for each cell type and diagnostic data such as a detected fault type and a fault position, and register it as a library.

Therefore, according to the method of the present embodiment, it is not necessary to create diagnostic data unique to each circuit, and the number of diagnostic steps in the design stage can be reduced. If a variation of the diagnostic data when there are unused pins is also prepared, it is not necessary to make a diagnostic wiring for the unused pins.

The invention made by the inventor of the present invention has been specifically described above based on the first to fourth embodiments, but the present invention is not limited to the above-mentioned embodiments, and various modifications are possible without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the fault diagnosis circuit of the first embodiment, the case where the breaking switches 81b to 84b are installed only on the output pin side of the cells 51b and 53b in the parallel diagnosis of the plurality of cells 50 has been described. The present invention is not limited to the above-mentioned embodiment, but can also be applied to the case where the cells are installed only on the input pin side and a plurality of cells are diagnosed in parallel.

In the above description, the case where the invention made by the present inventor is applied to the failure diagnosis circuit and the diagnosis method used in the field of application, especially the large-scale logic circuit is mainly described, but the invention is not limited thereto. However, it is widely applicable to fault diagnosis of other logic circuits such as ultra-large scale and medium scale.

[0053]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). Selection means for selecting an arbitrary cell from a single cell or a plurality of cells, and an output signal from the cell selected by this selection means to another cell and an input signal from another cell are cut off. By including a shut-off means for shutting off an influence on other cells by selecting an arbitrary cell, a signal for failure diagnosis is applied to the input pin and output to the selected cells at the same time. Since the signal of the diagnostic result can be observed at the pin, it is possible to apply and observe the input / output signal in an independent state from other cells to the cell that was difficult to control and observe with the input / output from the edge pin. Therefore, high failure detection capability can be obtained.

(2). Selection means for selecting an input pin of an arbitrary cell from a single cell or a plurality of cells, and a signal between a signal application line and a signal observation line on the same line as the input pin of the cell selected by this selection means Since the signal entering the input pin of an arbitrary cell can be observed through the signal observation line by applying the interruption means for interrupting, the application of the arbitrary signal can be performed through the signal application line. With this, it becomes possible to apply an arbitrary signal to the input pin of the cell, which was difficult to control and observe, at the same time as observing the input signal from another cell, and it is possible to obtain a high fault detection capability.

(3). By diagnosing only cells having low controllability and observability, cells having a dedicated function for diagnosis can be narrowed down, so that the overhead of the diagnostic circuit can be kept low. In addition, it is possible to improve the detection rate while suppressing the occupation rate of the diagnostic circuit on the circuit.

(4). Diagnosis is performed by using the diagnostic data stored in the library according to the type of cell, so that each cell as a component has diagnostic data corresponding to the cell type. The failure simulation and the creation of diagnostic data, which have been required, are no longer required, and the number of diagnostic steps in the logic design stage can be reduced.

(5) According to the above (1) to (4), it is possible to obtain the fault diagnosis circuit and its diagnosis method suitable for improving the fault detection capability in the fault diagnosis.

(6) According to the above (1) to (4), by using the diagnostic circuit, the number of man-hours for creating the diagnostic data is reduced, the test generation for each target logic circuit is made unnecessary, and the fault simulation is facilitated to facilitate the diagnosis. It is possible to obtain a failure diagnosis circuit and a diagnosis method thereof that can be realized.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing a failure diagnosis circuit having a built-in diagnosis circuit that enables diagnosis in cell units, which is Embodiment 1 of a failure diagnosis circuit and a diagnosis method thereof according to the present invention.

FIG. 2 is a detailed diagram illustrating a diagnostic circuit in a diagnostic target cell in the first embodiment.

FIG. 3 is a detailed view showing a cutoff switch between a diagnosis target cell and another cell in the first embodiment.

FIG. 4 is a configuration diagram showing a modified example of the cutoff switch according to the first embodiment.

FIG. 5 is a configuration diagram showing a case in which a cutoff switch between a cell to be diagnosed and another cell is arranged only on the output pin side of the circuit in the first embodiment.

FIG. 6 is a configuration diagram showing a failure diagnostic circuit incorporating a diagnostic circuit for observing a signal at an input pin of a cell and applying a signal, which is Embodiment 2 of the failure diagnostic circuit and the diagnostic method therefor according to the present invention.

FIG. 7 is a configuration diagram showing a failure diagnosis circuit in which a failure diagnosis circuit and a diagnosis method according to a third embodiment of the present invention, which enables diagnosis in cell units, is applied to a part of cells of all circuits. is there.

FIG. 8 is a configuration diagram showing a data flow of a diagnostic method having a diagnostic data of a diagnostic circuit as a library, which is a fourth embodiment of the fault diagnostic circuit and the diagnostic method of the present invention, which enables diagnosis in cell units.

[Explanation of Codes] 10, 10d Controller 11, 11d Shift Register 12, 12d Shift Register 20, 20d Signal Application Line 21, 21c Signal Application Line 22, 22c Signal Application Line 30, 30d Signal Observation Line 31, 31c Signal Observation Line 32 , 32c signal observation line 40, 40d selection signal line (selection means) 41, 41a, 41b, 41c selection signal line (selection means) 50, 50d cell 51, 51a, 51b, 51c cell 52, 52a, 52b, 52c real logic Part 53b Cell 61, 61c Input pin 62, 62c Input pin 71 Output pin 72 Output pin 81, 81a, 81b, 81c Breaking switch (breaking means) 82, 82a, 82b, 82c Breaking switch (breaking means) 83, 83a, 83b Breaking switch (breaking means) 84, 84a, 84b Breaking Switch (breaking means) 91, 91c switch 92, 92c switch 93, 93c switch 94, 94c switch 101 data table 102 signal application line data 103 signal observation line data 104 selection signal line data 105 diagnostic data

Claims (4)

[Claims] 1. A failure diagnostic circuit for a logic circuit composed of a single or a plurality of cells, comprising: selecting means for selecting an arbitrary cell from the single or a plurality of cells; and a cell selected by the selecting means. An output signal to another cell, and a blocking means for blocking an input signal from another cell are provided, and an arbitrary cell is selected to block the influence on the other cell.
A failure diagnosis circuit, wherein a signal for failure diagnosis is applied to an input pin at the same time with respect to the selected cells, and a signal of a diagnosis result is observed at an output pin. 2. A failure diagnosis circuit for a logic circuit composed of a single or a plurality of cells, comprising: selecting means for selecting an input pin of an arbitrary cell from the single or a plurality of cells.
The input pin of the cell selected by the selecting means is provided with a blocking means for blocking a signal between the signal applying line and the signal observing line on the same line, and at the same time the signal entering the input pin of the arbitrary cell is observed through the signal observing line. A failure diagnosis circuit characterized in that an arbitrary signal is applied through a signal application line. 3. The diagnostic method of the fault diagnostic circuit according to claim 1 or 2, wherein the diagnostic is performed only on cells having low controllability and observability. 4. The diagnostic method of the fault diagnostic circuit according to claim 1, wherein the diagnostic method is performed by using diagnostic data that is made into a library according to a cell type.