JPH05152298A - Wiring formation - Google Patents

Abstract

PURPOSE:To form a wiring of two-layer structure having resistance to both EM and SM without corrosion and complication of a process by making a wiring amorphous and by thermally treating it thereafter. CONSTITUTION:After a wiring thin film is formed on a foundation insulating layer 4, it is processed to a specified pattern and a wiring layer 1 is formed. A crystal grain diameter of the wiring layer 1 in the process depends on thermal treatment conditions after film formation; approximately, it is an order from several tenths of mum to several mum. Then, ion implantation is performed, and crystal grain boundary is broken as far as about half a depth of a thickness of the wiring layer 1 and an amorphous layer 3 is formed. Thereafter, heat treatment is carried out at about 400 deg.C for about 20 to 30min, the amorphous layer 3 is recrytallized and the wiring layer 1 is formed to two-layer structure. Since the formed wiring layer 1 does not have a bamboo grain boundary which thoroughly crosses inside a wiring due to its two-layer structure and each of an upper layer and a lower layer has bamboo structure, both EM resistance and SM resistance can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a wiring forming process.

[0002]

2. Description of the Related Art As semiconductor devices become finer, reliability of wiring films (especially Al alloy films) decreases due to electromigration (hereinafter abbreviated as "EM") and stress migration (hereinafter abbreviated as "SM"). Is becoming a big problem. As a conventional EM measure, other metal impurities (for example, Cu, Ti, P) are contained in the wiring film Al.
It is considered that the so-called bamboo knot (hereinafter referred to as "bamboo") structure is formed by mixing d) or by increasing the crystal grain size.

Further, as a measure against SM, of course, as a measure against the stress of the insulating film covering the wiring film and the material, as well as against the EM, mixing of metal impurities and control of crystal grain size are considered. In addition, while the laminated film of the Al alloy and the refractory metal or the film formation of Al is taken out of the apparatus once,
A method of forming a wiring having a two-layer structure by forming a thin oxide film on the surface and further depositing Al on the thin oxide film is considered.

[0004]

However, as described above, the Al alloy containing impurities has a problem of corrosion, and the bamboo structure, which is an EM countermeasure, has a problem of poor SM resistance. In addition, the stacked film and the method of taking it out in the middle also have a problem in stability due to corrosion and complicated processes.

It is an object of the present invention to provide a method for forming a highly reliable wiring which is resistant to both EM and SM without corrosion or complicated process.

[0006]

The wiring forming method of the present invention comprises a step of ion-implanting the wiring with an energy that reaches a predetermined depth of the wiring to make the wiring amorphous to a predetermined depth. After the step, a heat treatment is performed to recrystallize the wiring in the amorphous state.

[0007]

By performing the ion implantation by using the wiring forming method having the above-mentioned structure, a part of the wiring layer becomes amorphous, and the subsequent heat treatment causes the wiring portion in the amorphous state to undergo grain growth to form a two-layer structure. The wiring which has is formed.

[0008]

The present invention will be described in detail below based on an example.

FIG. 1 shows a manufacturing process chart of an embodiment of the present invention. In FIG. 1, 1 is a wiring layer (Al alloy), 2 is a grain, 3 is an amorphous layer, and 4 is a base insulating layer (SiO _2).
Etc.).

Next, the manufacturing process will be described. First,
After forming a wiring thin film on the base insulating layer 4, it is processed into a predetermined pattern to form the wiring layer 1 (FIG. 1A). The crystal grain size of the wiring layer 1 at this time depends on the heat treatment conditions after film formation, but is generally about 0. It is on the order of several μm to several μm.

Next, ion implantation is performed under the following conditions to destroy the crystal grain boundaries to a depth approximately half the thickness of the wiring layer 1 to form the amorphous layer 3. For example, when the thickness of the wiring layer 1 is 1 μm, Al is ion-implanted, the acceleration energy is about 350 KeV, and Si is ion-implanted.
About 400 KeV, and when Ti and Cu are ion-implanted, about 200 KeV and the dose amount is 10 ¹⁵ to 10
Perform at ¹⁶ ions / cm ² or more.

Then, heat treatment is performed at about 400 ° C. for about 20 to 30 minutes to recrystallize the amorphized layer 3 to form the wiring layer 1 in a two-layer structure.

Although the two-layer structure has been described in the above embodiments, the present invention is not limited to this. Further, in the above embodiment, ion implantation or the like is performed after the wiring pattern is processed. However, even if the wiring pattern processing is performed after performing the ion implantation or the like after forming the wiring thin film, the same effect as in the above embodiment is obtained. Play.

[0014]

As described in detail above, by using the present invention, it is possible to form a wiring having a two-layer structure without corrosion or complication of the process.

Further, by having a two-layer structure, there is no bamboo grain boundary that completely traverses the wiring, and since the upper layer and the lower layer each have a bamboo structure, both EM resistance and SM resistance can be improved. You can

When Ti or Cu is ion-implanted, the effect of mixing impurities can be expected as described above, and the EM resistance and SM resistance can be further improved.

[Brief description of drawings]

FIG. 1 is a wiring formation process diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Wiring layer 2 Grain 3 Amorphous layer 4 Base insulating layer

Claims (1)

[Claims] 1. A step of ion-implanting the wiring to a predetermined depth of the wiring to make the wiring amorphous state to a predetermined depth, and after the step, heat treatment is performed to re-heat the wiring in the amorphous state. And a step of crystallizing the wiring.