JPH0514930B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to a system using a microprocessor, and particularly to a subroutine execution control system for a copying machine. (Prior Art) Conventionally, in a copy control device equipped with a microprocessor, different software was designed for each device (model) with a different mode, and debugging was performed. However, such a control system has the drawbacks of a long software design period and a long debugging period, as well as a problem of reduced reliability. (Purpose) The present invention has been made in view of the shortcomings of the conventional example, and by using common software across multiple devices of a similar scale with different operation modes, the software development and design period can be reduced. The purpose is to shorten the debugging period and improve reliability. (Structure) The structure of the present invention will be described below based on illustrated embodiments. FIG. 1 shows a subroutine management table of the present invention.
FIG. 2 shows a priority determination register that determines whether or not a subroutine can be executed by comparing it with the priority status of the subroutine management table, and FIG. 3 shows a software configuration block for explaining the present invention. It is a diagram. The main routine, subroutine group, and subroutine management table shown in FIG. 3 are provided in a read-only memory element (RM), and the priority determination register is provided in a read/write memory element (RAM). FIG. 1a shows the contents at each address (addresses 10 to 19), ie, the priority status of subroutine A, or the start address of subroutine A. Also, b in the same figure corresponds to each address in a.
It is a combination of 0.1 signals. Further, in FIG. 3, 1 indicates a main routine, 2 indicates a subroutine group, 3 indicates a subroutine management table, and 4 indicates a priority determination register.
Note that the signal flow is as shown in the figure. Next, an outline of the operation will be described with reference to the block diagram of FIG. 3. The main routine 1 first sets the priority determination register 4 to "00000001" and then
Perform an AND with the priority status “00000001” of subroutine A shown in (10) of management table 3,
Since the result is not 0, the program branches to the start address (0C210H) of subroutine A shown in (11) below. Next, the priority status "00000010" of subroutine B shown in (12) is ANDed, and since the result becomes 0, there is no branching to the next subroutine B shown in (13). As described above, subroutines A, Y, and Z are executed in the first scan. In the final subroutine of the management table 3, ie, Z in FIG. 1, the management table 3 is again set to start from the top (10), and the priority determination register 4 is shifted to the left by 1 bit. That is, it is set to "00000010". In this manner, subroutines B, Y, and Z are executed in the second scan. Similarly, in the third scan, subroutines X, Y, and Z are executed. Also 4
In the second scan, Y and Z are executed. The following table summarizes the number of scans and execution routines.

【table】

[Table] In this way, by defining the priority of subroutines in terms of execution speed for each subroutine on the management table 3, operations that require precision can be selectively managed. FIG. 4 is a schematic flowchart for explaining the above control operation. That is, after turning on the power, first clear the entire area of RAM where the priority determination register is provided (S
-1), an initial value is set in the priority determination register (S-2). Next, set the value of the pointer to management table 3.
is set to the value of the start address of the first subroutine (S-3). In the next step S-4, the set value of the priority determination register is ANDed with the priority status value of the subroutine indicated by the pointer.
Determine whether it is 0. If the result is Yes, 2 is added to the value of the pointer to point to the value of the start address of the next subroutine in the management table 3 (S-5), and then the process returns to step S-4.
If the determination result is No, 1 is added to the value of the pointer (S-6), and the process branches to the subroutine pointed to by the pointer (S-7). Then, it is determined whether the subroutine is the final subroutine (S-
8) If the judgment result is No, add 1 to the value of the pointer and point to the value of the start address of the next subroutine in management table 3 (S-
9), return to step S-4. If the determination result is Yes, the set value of the priority determination register is shifted to the left by 1 bit (S-10), and then the process returns to step S-4. (Effects) The present invention is as described above, and according to the present invention, by appropriately setting the first encoding information, it is possible to share software even in different devices. Therefore, it is possible to shorten the software development design period and the software debugging period, and it is expected that the software reliability will be improved. Furthermore, it has the effect of improving control accuracy.

[Brief explanation of drawings]

FIG. 1 shows a subroutine management table of the present invention, where a shows the content of the address, b shows the content of the 0.1 signal, FIG. 2 shows the priority limited register, and FIG. 3 shows the subroutine management table of the present invention. The control block diagram according to the embodiment, FIG. 4, is its operation flowchart. 3... Subroutine management table.

Claims (1)

[Scope of Claims] 1. A first storage means for storing a plurality of control procedures to be controlled, and a plurality of bits of first encoded information representing execution selection information of the control procedure corresponding to the control procedure. and a third storage means for storing second encoded information having the same number of bits as the first encoded information, of which only one bit is set to a high level. a storage means for all the first encoded information;
calculation means for sequentially calculating the logical product of each bit of the encoded information and the second encoded information; and a high-level bit of the second encoded information stored in the second storage means. encoded information updating means for sequentially shifting the position; and according to the calculation result calculated by the calculation means for all the second encoded information updated by the encoded information updating means, the calculation means a control device that sequentially executes the control procedure corresponding to the first encoded information when the first encoded information is outputted a high level signal.