JPH05145536A - Alternate signal circuit provided with multi-function - Google Patents

Abstract

PURPOSE:To provide the alternate signal circuit which is capable of reducing power consumption to a lower level by providing an interrupt detection means and an error detection means to the alternate signal circuit provided with multifunction generating an alternate signal so as to investigate a cause quickly when a fault takes place and providing a clock stop means to the circuit. CONSTITUTION:The circuit consists of a count means 11 counting an inputted clock signal, a selection means 12 selecting a '0' level or a '1' level and outputting the result by using an output of the counter means 11 as a control signal. An interruption detection means 20 detecting an output interruption of an alternate signal and an error detection means 30 detecting it that the signal outputted from the alternate signal circuit 10 is unmatched with a prescribed pattern and a clock stop means 40 stopping a clock signal inputted to the alternate signal 10 when the operation of the alternate signal circuit 10 is not required are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multifunctional alternating signal circuit for generating an alternating signal. The alternating signal circuit is a circuit that generates a pattern of designated "1" and "0", and is a circuit that is widely used in communication devices, electronic devices, and the like.

In such an alternating signal circuit, when an abnormality occurs, it is required to have a function of promptly investigating the cause of the abnormality. Furthermore, when such an alternating signal circuit is incorporated in an LSI, the LS
In order to reduce the power consumption of I, it is required to have a clock stop function when this alternating signal circuit is not used.

[0003]

2. Description of the Related Art FIG. 3 shows a diagram for explaining a conventional example.
(A) shows a circuit configuration of a conventional example, and 10 in the figure is an alternating signal circuit composed of a hexadecimal counter 11A and an 8/1 selector 12A.

(B) shows an example of the alternating signal output from the alternating signal circuit of (A). In (A), the hexadecimal counter 11A counts the input clock signal CK. The output of the counting result is the terminals QA, QB, QC,
Output from QD. Terminal Q of hexadecimal counter 11A
A, QB, and QC are connected to the control terminals A, B, and C of the 8/1 selector 12A, the input terminal 0 of the 8/1 selector 12A is connected to + 5V, and the input terminals 1 to 7 are connected to 0V. ..

Table 1 shows the relationship between the input and output of the 8/1 selector 12A.

[0006]

[Table 1] That is, 8 is input by the hexadecimal counter 11A.
Inputs connected to the input terminals 0 to 7 of the / 1 selector 12A are sequentially selected and output.

Here, only when the input from the hexadecimal counter 11A is 000, the 8/1 selector 12A outputs "0".
Is output, and in all other cases, "1" is output.

The counter is a hexadecimal counter 11A.
As the output terminal, Q of the most significant digit is used.
Although there is D, the output of QD is "0" when the count value is 0 to 7 and "1" when the count value is 8 to 15, and at that time, QA,
Since QB and QC repeat the same value, it is not necessary to use QD.

By the above operation, the alternating signal shown in FIG. 3B is output.

[0010]

In the above-mentioned conventional example, even if the alternating signal circuit 10 malfunctions, the error cannot be detected, and when the line is disconnected, it becomes inoperable.
When the alternating signal circuit 10 fails, it takes a long time to find the cause because the output is cut off but the output break cannot be detected.

Further, when this function is incorporated in an LSI, the alternating signal circuit 10 is used even when this function is not used.
As it operates, the power consumption increases. The present invention provides an alternating signal circuit capable of promptly determining the cause when a failure occurs by providing the disconnection detecting means and the error detecting means, and by reducing the power consumption by providing the clock stopping means. Try to make it happen.

[0012]

FIG. 1 is a block diagram for explaining the principle of the present invention. Reference numeral 10 in the figure is an alternating signal composed of a counting means 11 for counting the input clock signal CK, and a selecting means 12 for selecting and outputting "0" level and "1" level using the output of the counting means 11 as a control signal. Circuit.

Further, 20 is provided in the alternating signal circuit 10,
A disconnection detecting means for detecting the output disconnection of the alternating signal, 30 is an error detecting means for detecting that the signal output by the alternating signal circuit 10 does not match a predetermined pattern, and outputting it, and 40 is an alternating signal circuit. When the operation of 10 is not required, it is a clock stopping means for stopping the clock signal CK input to the alternating signal circuit 10, and these means solve the problem.

[0014]

By counting the input clock signal CK by the counting means 11 and controlling the selection means 12 by the output,
"1" connected to the input terminal of the selection means 12,
"0" is selected and output to generate a specified pattern.

In this operation, the disconnection detecting means 20 monitors the output of the selecting means 12 and outputs an disconnection detection signal when the output disconnection is detected, and the error detecting means 30 outputs the output of the counting means 20. When the error is detected by comparing the pattern to be generated from the pattern with the pattern output from the selection means 12, an error detection signal is output to facilitate the investigation of the cause when the failure occurs.

Further, when this function is incorporated into an LSI, if the function of the alternating signal circuit 10 is not used,
By stopping the clock by the clock stopping means 40, it is possible to reduce power consumption.

[0017]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
The alternating signal circuit 10 including the hexadecimal counter 11A and the 8/1 selector 12A in the figure has the same structure as that described in the conventional example.

Reference numeral 21 is a monostable multivibrator (hereinafter referred to as MMB) as the disconnection detection means 20 described in the principle diagram, and 41 is an AND circuit (hereinafter referred to as an AND circuit) as the clock stop means 40.

Further, a NOR circuit (hereinafter referred to as NOR circuit) 31 and an inverter (hereinafter referred to as INV) 3
2. Exclusive OR circuit (hereinafter referred to as EX-OR circuit)
The error detection means 30 is constituted by 33.

It is assumed that the alternating signal generated in this embodiment repeatedly generates the pattern in which "0" is 1 bit and "1" is 7 bits described in the conventional example. 8 /
The 1-selector 12A generates a specified pattern by selecting and outputting "0" or "1" according to the signal input from the hexadecimal counter 11A.

As the MMB 21 for detecting disconnection, for example, L
8LS selector 12A using SI 74LS123
By connecting the output of 1 to the terminal 1 and fixing the terminal 3 to "1", since the input signal does not transition when the output is cut off, the MMB21 is not triggered and the output terminal 4 outputs "1" as a cutoff detection signal. Is output.

Further, the output QA of the hexadecimal counter 11A,
QB and QC are input to the NOR circuit 31. here,
When all three outputs are "0", "1" is output, and in other cases, "0" is output. The output of the NOR circuit 31 is inverted by the INV 32 and input to one terminal of the EX-OR circuit 33. The output of the 8/1 selector 12A is input to the other terminal of the EX-OR circuit 33, and when the 8/1 selector 12A is operating normally, the two inputs match, so EX- OR circuit 3
3 outputs "0".

That is, when the two inputs do not match, "1" is output as the error detection signal. Also, A
One input terminal of the ND circuit 41 is connected to the clock, and the other input terminal is connected to the clock control signal INH. Normally, the clock control signal INH is set to "1" and when this function is stopped, it is set to "0" to inhibit the input of the clock CK to stop the operation of the alternating signal circuit 10 and reduce the power consumption. Let

[0024]

According to the present invention, by providing the alternating signal circuit with the disconnection detecting means and the error detecting means, it becomes easy to find the cause when the alternating signal circuit fails. further,
The power consumption can be reduced by providing the clock stop means.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating a conventional example.

[Explanation of symbols]

10 Alternate Signal Circuit 11 Counting Means 11A Hexadecimal Counter 12 Selection Means 12A 8/1
Selector 20 Disconnection detecting means 21 MMB 30 Error detecting means 31 NOR circuit 32 INV 33 EX-O
R circuit 40 clock stop means 41 AND circuit

Claims (3)

[Claims] 1. A counting means (11) for counting an input clock signal CK, and "0" as an output of the counting means (11) as a control signal.
Selector for selecting and outputting the level and the "1" level (1
A multifunctional alternating signal circuit including a disconnection detecting means (20) for detecting an output disconnection of an alternating signal in an alternating signal circuit (10) according to 2). 2. The error detecting means (30) for detecting that the signal output from the alternating signal circuit (10) does not match a predetermined pattern and outputting the error detection means (30). Multi-function alternating signal circuit. 3. The clock stop means (40) for stopping the clock signal input to the alternating signal circuit (10) when the operation of the alternating signal circuit (10) is not required. The multifunctional alternating signal circuit according to Item 1.