JPH05145429A - Variable length decoder - Google Patents

Abstract

PURPOSE:To obtain the variable length decoder decoding variable length coding data with a high bit rate. CONSTITUTION:The decoder is provided with a serial parallel conversion section 11 converting serial input data 102 into parallel data, a processing clock generating section 12, a final succeeding node number generating section 6 generating a feedback signal to implement repetitively decoding and decoding index generating sections 7, 8, 9, 10 outputting a decoded index. Thus, the bit rate of variable length coding data to be decoded is considerably increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length decoder for decoding variable length coded data.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional variable length decoder. For example, Mitsubishi Electric Technical Report Vol. 6
0, No. 10 is a diagram in which the inside of the variable length decoding block of the block diagram on the receiving side in "FIG. 3. Configuration of video codec" shown on page 40 of 10 (1986.10.) Is expanded.

In the figure, 2 is an initialization unit for initializing the next node number by a reset signal, 3a and 3b are D type flip-flops for constructing a synchronous circuit, and 4 is necessary for performing variable length decoding continuously. Next node number generation unit 5 for generating a next node number is a decoding index generation unit for generating a decoding index.

Next, the operation will be described.

First, prior to the description of the specific operation of the conventional example, the structure of the variable length code and the concept of the decoding method will be briefly described. The variable-length code generally has a tree structure. For example, a fixed-length 3-bit index as shown in FIG. 3 and a corresponding 1-bit to 7-bit variable-length code are shown in FIG. It has a tree structure as shown in. A tree branch branches at each node corresponding to a bit value of "0" or "1", and a variable with a fixed-length index value at the end of the traced branch. It corresponds to the long code. For example, the variable length code “001” corresponds to the index 2 that starts from the node number 0 in FIG. 4 and reaches the node number 1 and the node number 2.

The variable length decoding is achieved by repeating the operation of tracing the tree structure as shown in FIG. 4 from the node number 0 to the end of the branch having the fixed length index according to the input variable length encoded data. ..

With this decoding method in mind, the operation of the conventional variable length decoder shown in FIG. 5 will be described. The input 1-bit serial variable-length coded data 102 is
The data is latched by the D-type flip-flop 3a by a clock 101 having a bit transmission rate (hereinafter, referred to as a bit rate) of the data, and is input as decoding data 302 to the next node number generating unit 4 and the decoding index generating unit 5. On the other hand, the initialization unit 2 uses the real node number 201
At the time of reset, the reset signal 103 outputs the starting node number, that is, the node number 0 in FIG. 4, and normally outputs the next node number 401 from the next node number generation unit 4. The real next node number 201 is latched by the D-type flip-flop 3 a like the variable length encoded data 102, and is input as the current node number 301 to the next node number generation unit 4 and the decoding index generation unit 5. The next node number generation unit 4 traces the variable length code tree described above from the current node number 301 and the decoding data 302, obtains the node number to move to next, and outputs it as the next node number 401.

Explaining it concretely in the example of FIG. 4, for example, when the current node number 301 is 0 and the decoding data 302 is 0, 1 is set as the next node case 401, and the current node number 301.
Is 2 and the decryption data 302 is 0, the next node number is 4
3 is output as 01, and so on. Further, for example, when the current node number 301 is 0 and the decoding data 302 is 1, the index 0 is decoded, but at this time, in order to continue the decoding operation, the next node number 4
0 is output as 01.

The decoding index generator 5 outputs a detection flag 501 indicating that the index has been decoded and a decoding index 502 which is the decoded index only when the end of the variable length code tree is reached. Then, the detection flag 501 and the decoding index 502.
Is a D-type flip-flop 3 according to the clock 101.
It is latched at b and output as the output detection flag 311 and the output decoding index 312.

As described above, the output detection flag 311 and the output decoding index 312 are sequentially output by repeating the same operation every clock while feeding back the next node number 401 starting from the reset by the reset signal 103. It FIG. 6 is a timing chart showing the above operation for the example of the variable length code shown in FIGS. 3 and 4, and the variable length coded data 102 is “0, 1, 1, 0, 0, 0, 0, 1”. , ... ”is input, the decoding index 502 is“ 1, 0,
4, ... ”Is coded. As is clear from this figure, the decoding index 502 is decoded at the minimum, one clock cycle of the clock 101.

[0011]

Since the conventional variable length decoder is configured as described above, only one bit of variable length coded data can be processed in one clock, and therefore a variable length code having a high bit rate can be processed. The clock frequency must be increased to process encoded data, but the operating speed of the elements used for processing is limited, so there is also a limit to increasing the bit rate of variable-length encoded data that can be processed. There were challenges.

The present invention has been made to solve the above problems, and an object thereof is to obtain a variable length decoder capable of decoding variable length encoded data having a high bit rate.

[0013]

In order to achieve the above object, the variable length decoder according to the present invention is provided with the following elements. (A) A serial / parallel conversion unit that converts variable-length encoded data of serial input into N-bit parallel by a clock equal to its bit transmission rate, and (b) generates a decoding processing clock with a cycle N times that of the above clock. A processing clock generator for supplying to the synchronizing circuit, (c) current node number and parallel decoding for outputting the next node number fed back to perform the iterative decoding operation and the parallel variable-length coded data latched and output by the synchronizing circuit. Final-next-node-number generation unit that generates and feeds back the last-next-node number for every N bits based on the data for use, and (d) outputs in parallel each index decoded based on the current node number and the parallel decoding data. A predetermined number of decoding index generation units.

[0014]

In the variable length decoder constructed as described above,
By converting the variable-length coded data to be input into a plurality of bits in parallel through the serial / parallel converter,
By performing the decoding operation with a slow processing clock corresponding to the above data rate generated in the processing clock generation unit due to the decrease in data rate, it becomes possible to decode variable length coded data with a high bit rate. Also, the plurality of decoding index generation units decodes the plurality of decoding indexes within the same processing clock.

[0015]

EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a variable length decoder in the case where the variable length coded data is parallel-converted into 4 bits by applying the present invention. The variable length decoder corresponds to the conventional example shown in FIG. Are assigned the same reference numerals and explanations thereof are omitted. In the figure, 6 is decoding data 30 input in 4-bit parallel.
A final next node number generation unit that finally generates a next node number when 3 is decoded from the current node number according to the variable-length code tree, and 7 is decoding data 303 input in 4-bit parallel to the current node. A first decoding index generation unit that generates a decoding index that is detected first when the number is decoded according to the variable-length code tree,
8 is a second decoding index generation unit that generates a decoding index that is detected second as with the first decoding index generation unit 7, and 9 is decoding that is detected third as with the first decoding index generation unit 7. Similarly to the first decoding index generation unit 7, the third decoding index generation unit 10 generates a fourth decoding index generation unit that generates a decoding index detected fourth, and 11 is a variable length coding of serial input. A serial / parallel conversion unit (hereinafter referred to as an S / P conversion unit) that converts data into 4-bit parallel by an input clock equal to the bit rate, 12 is a 1/4 required for decoding processing from the input clock.
It is a processing clock generation unit that generates a processing clock having a frequency of 4 times the cycle.

Next, the operation will be described.

The structure of the variable length code and the concept of the decoding method are the same as the contents described in the prior art, and therefore will be omitted.

The input 1-bit serial variable-length coded data 102 is converted into 4 by the S / P converter 11 by the clock 101 having the same bit rate as the input data.
Bit-parallel parallel variable-length coded data 1101
Is converted to. Further, the clock 101 is divided into 1/4 by the processing clock generation unit 12
01 is distributed to each part of the D-type flip-flops 3a and 3b forming the synchronous circuit.

The parallel variable length coded data 1101
Is latched by the D type flip-flop 3a according to the processing clock 1201 described above, and the parallel decoding data 3
03 as the final next node number generation unit 6, the first decoding index generation unit 7, the second decoding index generation unit 8, and the third
It is input to the decoding index generation unit 9 and the fourth decoding index generation unit 10. On the other hand, the real secondary node number 201 similar to that described in the description of the prior art is also latched by the D type flip-flop 3a, and the final secondary node number generating unit 6 and the first to fourth decoding index generation are performed as the current node number 301. Input to parts 7-10.

Next, the final next node number generator 6 traces the variable length code tree for 4 bits from the input current node number 301 and the 4-bit parallel decoding data 303, and finally traces. Node number is next node number 40
Output as 1. For example, in the example of the variable length code tree shown in FIG. 4, when the current node number is 0 and the parallel decoding data is 4 (= 0, 1, 0, 0), the variable length code tree is Follow. (Node number 0) ↓ '0' branch node number 1 ↓ '1' branch index 1 detected (restart from node number 0) ↓ '0' branch node number 1 ↓ '0' branch node number 2 This At this time, the node number 2 is output as the next node number 401. Further, when it ends with the detection of the index without ending with the node number, the node number 0 is output as the next node number 401.

On the other hand, the first decoding index generating section 7
A first detection flag 701 indicating that the first detected index is the first detected index by tracing the variable length code tree for 4 bits from the input current node number 301 and the 4-bit parallel decoding data 303 It is also output as the first decoding index 702. Here, if no index is detected, the first
The detection flag 701 and the first decoding index 702 are not output. The second decoding index generation unit 8 uses the first decoding index
Similar to the decoding index generation unit 7, the second detected index is output as the second decoding index 802 together with the second detection flag 801. Here, when the number of detected indexes is 1 or less, the second detection flag 801 and the second decoding index 802 are not output.

The third decoding index generator 9 is also the first
Similar to the decoding index generation unit 7, the third detected index is output as the third decoding index 902 together with the third detection flag 901. Here, if the number of detected indexes is two or less, the third detection flag 901 and the third decoding index 902 are not output.

Similarly to the first decoding index generating unit 7, the fourth decoding index generating unit 10 outputs the fourth detected index as the fourth decoding index 1002 together with the fourth detection flag 1001. here,
If the number of detected indexes is 3 or less,
Fourth detection flag 1001 and fourth decoding index 100
2 is not output.

The above operation is performed by the reset signal 103.
The decoded index is sequentially output by repeating the processing clocks while feeding back the next node number 401 starting from the reset by.

FIG. 2 is a timing chart when the above operation is performed for the example of the variable length code shown in FIGS. 3 and 4, and the variable length coded data 102 is "0, 1, 1.
"1,0,0,0,0,1, ..." is input,
"1, 0, 4, ..." Is decoded as the decoding index. As is clear from this figure, the decoding index is decoded at the minimum, in one clock cycle of the processing clock 1201, that is, in four clock cycles of the clock 101.

As described above, the variable-length coded data 102 is converted from serial to 4-bit parallel while the variable-length decoding operation is performed, so that the processing clock 1201 is processed with a clock having a cycle four times that of the clock 101. It becomes possible.

In the first embodiment, from 1 bit to 4 bits
The case has been described as an example where the variable length decoding operation is performed while performing serial / parallel conversion to bits, but the present invention is not limited to this, and it can be expanded to perform variable length conversion while performing serial / parallel conversion from 1 bit to N bits. A decoding operation can also be performed. In this case, the processing clock has a cycle N times the input clock.

In the first embodiment, an example in which four decoding index generation units, ie, first to fourth, are provided has been described. However, depending on the contents of the variable-length code, four decoding indexes can be simultaneously generated from the parallel decoding data. May not be decoded. In such a case, the decoding index generation unit may be appropriately reduced.

[0030]

As described above, according to the present invention, serially input variable-length coded data is converted into N-bit parallel by a clock having a bit rate equal to that of the input data, so that the variable-length encoded data can be changed at a clock cycle slower than the input clock. It becomes possible to perform long decoding, and it is possible to obtain a variable length decoder in which the bit rate of the variable length encoded data to be processed is greatly increased as compared with the conventional technique.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a variable length decoder showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the variable length decoder shown in FIG.

FIG. 3 is a diagram showing an example of a variable length code.

FIG. 4 is a diagram showing the variable length code example of FIG. 3 in a tree shape.

FIG. 5 is a block diagram showing a conventional variable length decoder.

6 is a timing chart showing the operation of the variable length decoder of FIG.

[Explanation of symbols]

 2 initialization unit 3a D type flip-flop (synchronous circuit) 3b D type flip-flop (synchronous circuit) 6 final next node number generation unit 7 first decoding index generation unit 8 second decoding index generation unit 9 third decoding index generation unit 10 4th decoding index generation part 11 S / P conversion part (serial / parallel conversion part) 12 Processing clock generation part

Claims (1)

[Claims] 1. A variable length decoder comprising: (a) serial / variable length encoded data converted into N-bit parallel by a clock having a bit transmission rate equal to that of the serial input; Parallel conversion section, (b) a processing clock generation section for generating a decoding processing clock having a cycle N times that of the above clock and supplying it to a synchronous circuit, (c) a next node number fed back for performing an iterative decoding operation, and the above A final next node number generation unit for generating and feeding back a final next node number for every N bits based on the current node number and parallel decoding data latched and output by the parallel variable-length coded data, and (d) ) A predetermined number of decoding indexes for outputting in parallel each index decoded based on the current node number and the parallel decoding data. Box generation unit.