JPS62239623A - Circuit for generating period redundancy check - Google Patents

Abstract

PURPOSE:To reduce the cost and power consumption by generating a period redundancy check (CRC) code to a parallel data so as to eliminate the need for the consitution using a high speed device. CONSTITUTION:A parallel data inputted by a latch part 21 is stored tentatively and the subtraction of modulo 2 is applied to an output data of the latch part 21 by a subtraction section 22. The term of the k-th order in the generation polynomial whose coefficient ak is not zero being an output of the subtraction section 22 is connected to the term of the k-th order of the latch part 21 by feedback. A decode section 23 decodes the output of the subtraction section 22. Thus, the CRC code is processed to the parallel data and the need of the constitution using the high speed device is eliminated and the cost and power consumption are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cyclic redundancy check code generation circuit for digital information transmission. In particular, the present invention relates to a cyclic redundancy check (hereinafter referred to as CRC) code generation circuit for detecting errors in parallel data signals.

〔overview〕

The present invention enables a CRC code generation circuit for digital information transmission to generate a CRC code for parallel data, thereby eliminating the need for a high-speed device and reducing cost and power consumption. It is something.

[Conventional technology]

FIG. 5 is a block diagram of a conventional cyclic redundancy check code generation circuit.

As shown in Figure 5, a conventional CRC code generation circuit consists of n shift registers and (m-1) exclusive OR gates, where the degree of the generator polynomial is n and the number of non-zero terms is m. The circuit was constructed using

This circuit inputs serially input data from the part corresponding to the X00 term of the shift register, sequentially shifts it to the higher order terms, and when the final data is input to the Xo term, the CRC code is changed to n. appears in the shift registers.

[Problem that the invention seeks to solve]

However, since such conventional CRC code generation circuits generate CRC codes for serial data, they cannot generate CRC codes for parallel data unless a parallel-to-serial conversion circuit is used. I couldn't do it. Therefore, the CRC code generation circuit must be constructed using high-speed devices corresponding to the increase in clock speed due to parallel-to-serial conversion, resulting in an increase in circuit cost and power consumption.

The present invention solves the above-mentioned drawbacks, and aims to provide a periodic redundancy check code generation circuit that does not need to be constructed using high-speed devices, is inexpensive, and consumes little power.

[Means for solving problems]

The present invention includes a latch section (11) that receives parallel data and temporarily stores this data, a subtraction section (12) that performs modulo 2 subtraction on the output data of this latch section, and The next term of the generator polynomial is its coefficient am
The present invention is characterized in that it comprises a circuit that connects a term in which is not zero in feedback to the next term of the latch section, and a decoding section (13) that decodes the output of the subtracting section.

[For production]

The parallel data inputted in the latch section is temporarily stored, and the output data of this latch section is subjected to modulo 2 subtraction in the subtraction section. Among the outputs of this subtraction section, the next term of the generator polynomial whose coefficient ak is not zero is feedback-connected to the next term of the latch section. The decoding section decodes the output of the subtraction section. By the above operation, CRC is applied to parallel data.
It can process codes, does not need to be configured using high-speed devices, is inexpensive, and consumes less power.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block configuration diagram of a cyclic redundancy check code generation circuit according to the present invention, and is for explaining the configuration of the circuit. In FIG. 1, parallel data is input to a latch section 11 and temporarily held. The output of the latch section 11 is connected to the input of a modulo 2 subtraction section 12, and modulo 2 subtraction is performed. Among the outputs of the modulo-2 subtraction section 12, the next term of the generator polynomial whose coefficient ak is not zero is feedback-connected to the next term of the latch section 11. The output of the modulo 2 subtraction section 12 is connected to the decoding section 13, where it is decoded and a CRC code is output. Now, assuming that n and m are positive integers and the n-th degree generator polynomial % is sent in l-bit parallel in U columns,
The configuration of each circuit section in the block diagram shown in FIG. 1 will be explained.

[1] The configuration of the latch section 11 will be explained.

In order to process 2-bit parallel data, it is composed of latch circuits in units of 1 x 1 column.

+11 If (2n+1)<β, two columns are required because 2·(n+1) bits must be processed at once.

(2) When (2n + 1) ≧ β If (S) is defined as representing the largest integer less than S, the latch circuit processes ((2n + 1) bi-nodes at a time, so + 1)/l) + 1 column is required. Here (((2n+ 1)/l)+ 1)
- In the case of ff1=2n+l, the calculation of the CRC code ends when the U-th column, which is the last column of data, enters the latch circuit of the last column of the latch unit 11, but (((2n+1)
/1)+1)-12 is not divisible by 2n+1 and in the case of item (1), when the U+1st column whose data is the column vector of rOJ enters the final stage latch circuit of latch section 1, , in the case of item (1), the CRC code of the data is obtained with 2n+1-12 digits raised from the original data, and
In case 2), the CRC code of data without carry is determined. By passing this through the decoding section 13, the desired CRC code can be obtained.

[2] The configuration of the modulo 2 subtraction unit 12 will be explained.

FIG. 2 is a circuit diagram of a unit modulo 2 subtraction circuit of the cyclic redundancy check code generation circuit of the present invention. If the next coefficient am of the generator polynomial is rOJ, the next gate is removed and connected to the next input so that it becomes the blowout output.

(1) When (2n+1)<l, the primary output of the previous stage is connected to the next input, and the circuit is composed of n+1 stages of unit modulo 2 subtraction circuits. FIG. 3 is a circuit diagram of a two-stage modulo-2 subtraction circuit of the cyclic redundancy check code generation circuit of the present invention.

(2) When (2n + 1)≧β, it is composed of one stage of unit modulo 2 subtraction circuit.

The blowout output at the final stage of the multi-stage modulo 2m arithmetic circuit configured as described above is sent to the modulo 2 subtraction section 120 as the blowout output.

[3] The configuration of the feedback loop 14 will be explained.

(1) When (2n+1)<f, the output from the 2·(n+1)+n-1-1st order to the 0th order of the modulo 2 subtraction unit 12 is converted from the mth order to m −(2·(n
+1) +n-1-1) Next, connect the corresponding sets.

(2) When (2n+1)≧l, the outputs from the 2n-1st order to the 0th order of the modulo-2 subtraction unit 12 are connected in correspondence with the m-th order to the m-2n+1st order of the latch unit 11.

(4) The configuration of the decoding section 13 will be explained.

The original CRC code can be obtained using the output of the modulo 2 subtractor and an exclusive OR gate.

Letting the CRC polynomial to be found be R(X), then Q (X
It can be written as l = P(Xl -5(X) + R(X),
Q caused by adding extra “0” data
If the carry of (X) is r digits, the output obtained from the modulo 2 subtraction circuit will be the remainder of R(X)·X'' divided by P (Xl).

Since there are various cases of r and P(×), rather than generalizing the circuit configuration of the decoding section, it is better to
Since it is easier to construct a circuit from the result of actually executing division according to (x), the circuit construction is not shown.

FIG. 4 is a circuit diagram of a periodic redundancy check code generating circuit according to the first embodiment of the present invention, in the case where the generating polynomial is P(Xl-X'+X + 1 and 4-bit parallel data. 21 is a latch section, 22 is a modulo 2 subtraction section, 23 is a decoding section, and 24 is a feedback loop.

The operation of the cyclic redundancy check code generation circuit having such a configuration will be explained. First, latch circuit 21. ．． The initial values of 21□ are all set to "0", and the last data string is the latch circuit 21! latch circuit 21. A CRC code is obtained when all "0"s are entered.

〔Effect of the invention〕

As explained above, the present invention can generate a CRC code for parallel data, does not require configuration using a high-speed data device, is inexpensive, and has an excellent effect of reducing power consumption. There is. Therefore, if a serial-to-parallel conversion circuit is used before this circuit, serial high-speed data can be converted to parallel data and CRC data can be converted at low speed.
This has the advantage of being able to process codes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cyclic redundancy check code generation circuit according to the present invention. FIG. 2 is a circuit diagram of a unit modulo 2 subtraction circuit of the cyclic redundancy check code generation circuit of the present invention. FIG. 3 is a circuit diagram of a two-stage connected modulo-2 subtraction circuit of the cyclic redundancy check code generation circuit of the present invention. FIG. 4 is a circuit diagram of a periodic redundancy check code generation circuit according to a first embodiment of the present invention. FIG. 5 is a block diagram of a conventional cyclic redundancy check code generation circuit. 11.21... Latch section, 12.22... Modulo 2 subtraction section, 13.23... Decoding section, 14.24.
...feedback loop, 21. ．． 21□...Latch circuit, 40.50...Exclusive OR gate, 60.
...Shift register. Patent Applicant NEC Corporation 2 Agent Patent Attorney Nao Takashi Ide Embodiment Block Configuration Diagram Figure 1 Input Output Input Output Actual @ Example Unit Modulo 2 Circuit Embodiment 2 Stage Modulo 2 Circuit 2nd Figure 3
Figure - Actual 8fl Figure 4 Conventional example East Figure 5

Claims (1)

[Claims] (1) A latch section (11) into which parallel data is input and temporarily stores this data; a subtraction section (12) that performs modulo 2 subtraction on the output data of this latch section; It is characterized by comprising a circuit that connects the latch section in feedback to the next term for the Kth term of the polynomial whose coefficient a_k is not zero, and a decoding section (13) that decodes the output of the subtraction section. Cyclic redundancy check code generation circuit.