JP3083532B2 - Information signal decoding device - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial application field) The present invention embeds a codeword encoded to a variable length corresponding to a plurality of symbols in a fixed bit length unit. The present invention relates to an information signal decoding device that decodes an information signal sent as coded data.

(Prior Art) In an information compression system, there is an encoding system in which codewords of various lengths are allocated according to the probability of a generated symbol. As described above, an encoded data sequence having a variable length is transmitted or stored. In such a case, it is necessary to pack the bit length according to the transmission medium and the storage medium.

Therefore, in the case of decoding encoded data that is packed as a fixed bit length despite being an encoded data sequence having a variable bit length, an information signal decoding device as shown in FIG. 7 is conventionally used. And decrypted it.

The conventional information signal decoding device shown in FIG. 7 comprises a parallel / serial converter 21 for converting a parallel input signal into a serial signal, and a serial signal for reconverting the output serial signal of the parallel / serial converter 21 into parallel. A serial / parallel converter 22, a decoding table 23 for decoding the output of the serial / parallel converter 22, and a control unit 24 for controlling these units. The decoding table 23 is designed in advance according to the code word to be decoded, and is realized by a memory or the like.

In this conventional information signal decoding device, for example, L
When coded data 25 packed with bits as one unit is input, it is loaded into the parallel / serial converter 21, converted into serial data, and transferred to the serial / parallel converter 22. This transfer is continued until all the bits of the serial / parallel converter 22 are filled with the encoded data.

At this time, since the data of the parallel / serial converter 21 becomes empty every time the data is shifted by L bits, the control unit 24 generates a load signal 26 to load the next encoded data into the parallel / serial converter 21. . At this time, the load signal 26 is also used as a data request signal 27.

The serial / parallel converter 22 has the size of the maximum number of bits of the code word, and when all the bits are filled with the coded data, the decoding table 23 decodes the first word, and the decoded data 28 and the code The long signal 29 is output.

The control unit 24 generates a decoding notification signal 30, and further outputs a parallel / serial converter 21 and a serial / parallel converter 22.
, A shift signal 31 corresponding to the code length is generated. Also at this time, when the data of the parallel / serial converter 21 becomes empty, the next data is loaded.

When the shift is completed, the next word is decoded, and the encoded data is sequentially decoded in this manner.

(Problems to be Solved by the Invention) However, such a conventional information signal decoding device has the following two problems.

The first problem is that the input line of the decoding table 23 in FIG. 7 requires only the maximum word length of the input coded data. It requires large logic circuits or memories.

The second problem is that the decoding speed is lower than the operation speed (clock frequency) of the circuit. This is because a decoded word is shifted by a code length times from when a certain word is decoded until the next word is decoded.

In order to solve the second problem, there is a method in which the shift is performed collectively by using a barrel shifter or the like. However, in such a case, a problem that the circuit scale is extremely increased occurs. Problem solving was difficult.

According to the present invention, it is possible to perform decoding processing of encoded data having a large maximum word length without increasing the circuit scale.
It is another object of the present invention to provide an information signal decoding device capable of improving the decoding speed.

[Structure of the Invention] (Means for Solving the Problems) According to an information signal decoding apparatus of the present invention, codewords of variable bit lengths corresponding to a plurality of symbols are packed in a fixed bit length unit and sequentially input. For a coded data to come, a state register for storing a bit pattern of an undecoded data portion that could not be decoded in the previous decoding process as a state, and a bit pattern of the newly input coded data. A state transition circuit for generating a value which becomes a new state this time based on a combination with the state stored in the state register; a bit pattern of the newly input encoded data; A decoding information output circuit for generating information of decoded data based on a combination with the state stored in the register; and It is obtained by a decoded data generator for generating the issue data.

(Operation) According to the above configuration, every time coded data in a fixed bit length unit is input, a new bit data is generated based on a combination of the bit pattern of the coded data and the bit pattern of the previous undecoded data portion. , A bit pattern of a portion to be undecoded data is generated, and information of the decoded data is generated.

In this way, for a coded data sequence sequentially packed and packed with coded data having a variable length in a fixed bit length unit, decoded data portions that can be decoded are sequentially output and decoded for each input. The bit pattern of the undecoded data part that could not be obtained is combined with the next encoded data and decoded.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an information signal decoding apparatus according to this embodiment. This information signal decoding device includes a state transition circuit 1 for handling undecoded data and a decoded information output circuit 2 for handling decoded data, as two large components constituted by a ROM. A status register 3 for storing the bit pattern of the obtained undecoded data as a status (code), and a decoded data generator 4 for converting the decoded information output from the decoded information output circuit 2 into decoded data and outputting the decoded data. I have.

The state transition circuit 1 is a circuit that converts a bit pattern of undecoded data generated in the course of decoding into a code (hereinafter, referred to as a state) in advance, and includes a state / undecoded data converter 5 and an undecoded data transition. Unit 6 and the undecoded data /
And a state converter 7.

The decoded information output circuit 2 comprises a state / undecoded data converter 8 having the same function as the state / undecoded data converter 5 and a decoded information generator 9.

In FIG. 1, reference numeral 10 denotes encoded data which is sent by packing variable-length encoded data in fixed bit length units, and 11 corresponds to decoded data from the decoded information output circuit 2. Indicates signal information, 12 is the circuit clock,
Reference numeral 13 denotes decoded data output from the decoded data generator 4.

Next, the operation of the information signal decoding device will be described.

For the sake of simplicity, a small code will be used as an example. The number of information source symbols is s0 to s7, the codewords for each of the symbols s0 to s7 are as shown in the symbol / codeword table SCTBL shown in FIG. MSB shall be packed in order. That is, as shown in FIG. 3, if the sequence of the information source symbols is s0, s4, s6, s1, these codewords are actually (00), (110), (11110), (01 )In Although,
Since the coded data 10 is packed and sent in 3-bit length units, the corresponding coded data sequences are (001), (101), (111), and (001).

Generally, a binary code that can be decoded instantaneously can be represented by a binary tree, but in this embodiment, it can be represented by a binary tree as shown in FIG. In FIG. 4, the numbers (0, 1) written on each branch correspond to the bits of the code word. The codewords of the symbols s0 to s7 are obtained by sequentially arranging numbers written on each branch of the path from the root (top node) c0 to the symbol. Here, the symbols c0 to c6 of the respective nodes represent states corresponding to the undecoded data, and the assignment of the states is arbitrary. The undecoded data corresponding to each state is obtained by sequentially arranging numbers written on each branch of the path from the route c0 to the state.

Therefore, if the code word is (01), the binary tree shown in FIG. 4 can reach from the root c0 to the symbol s1 via the node c1, and if the code word is (1110), the root c0 to the node c2 , c4, and c5 to reach the symbol s5.

Also, if the undecoded data is (0), the route c0 is reached to the node c1, and the undecoded data (0) can be coded as the state c1, and if the undecoded data is (111), the route c0 To the node c5 via the nodes c2 and c4, and the undecoded data (111) can be coded as the state c5.

In the following, taking the case where the encoded data 10 has an input shown in FIG. 3 as an example, the operation of decoding by this information signal decoding device will be described, and the function of each unit will be described.

First, since there is no undecoded data in the initial state, the state is
c0 (none), and the state register 3 stores the state c0. This state c0 is input from the state register 3 to the state / undecoded data converter 5 (and 8), and in response to this input, the state / undecoded data converter 5 has empty current undecoded data. , Ie, state c0, to the undecoded data transition unit 6. Here, when the first encoded data (001) is input, the undecoded data transition unit 6 outputs the information (state c0) from the state / undecoded data converter 5 and the encoded data ( 001) to generate undecoded data. That is, according to FIG. 4, the first two bits (00) can reach the symbol s0 from the root c0 via the node c1 and can be decoded. However, the remaining one bit (1) cannot be decoded. , Undecoded data. This undecoded data (1) is
Output to the state converter 7. If no undecoded data is generated, the current contents stored in the status register 3 remain.

The undecoded data / state converter 7 converts the input undecoded data into a state. That is, undecoded data (1)
Then, the binary tree shown in FIG. 4 is traced to reach the node c2 from the root c0, which is the initial state, and obtain the state c2 as a code corresponding to the undecoded data (1). The state c2 is input to the state register 3.

The current contents stored in the state register 3 are updated to the state c2 by the input of the next clock 12, and used at the time of decoding the next encoded data.

On the other hand, the state / undecoded data converter 8 has the same function as the state / undecoded data converter 5, and outputs the state value c0 (none) of the state register 3 at that time to the decoded information generator 9.

The decoded information generator 9 obtains the state c0 obtained from the state / undecoded data converter 8 and the encoded data (001), and
Starting from 0, the first two bits (00) pass through c0-c1 to the symbol s0, and the decoded information 11 corresponding to the symbol s0
Generate Here, the reason why the decoded information generator 9 does not directly output the decoded signal is that a plurality of symbols may be decoded by one decoding process as shown in a later example. The decoded information 11 is a parameter to be passed to the decoded data generator 4, for example,
Is a symbol table such as a ROM, it becomes the address information of the symbol table.

The decoded data generator 4 receives such decoding information 11, converts it into decoded data 13, and outputs a signal of the symbol s0.

So far, the operation of the information signal decoding apparatus of FIG. 1 has been described based on the binary tree shown in FIG. 4. However, in the case of realizing it with actual hardware, the state transition circuit 1 and the decoded information output The circuit 2 is configured using a table such as a ROM. Then, the state data table shown in FIG.
By using the CTBL and the decoded data table DTBL shown in FIG. 6, it is possible to obtain the same result as tracing the above-described binary tree to reach the symbol.

That is, the state transition circuit 1 determines the next state value c2 from the combination of the state value c0 (none) of the state register 3 and the input encoded data (001) based on the state data table CTBL of FIG. It is extracted and output, and this is stored in the status register 3.

Further, the decoding information output circuit 2 determines the previous state value c0 of the state register 3 based on the decoding data table DTBL in FIG.
From the combination of (none) and the input coded data (001), information for outputting the decoded data s0 is generated.

Subsequently, when the second encoded data (101) shown in FIG. 3 is input, the state value c2 of the status register 3 and the input encoded data (101 ), The next state value c2 is determined. Similarly, the state value c2 of the state register 3 and the encoded data (10
From the combination with 1), the decoded data s4 is determined.

Further, when the third encoded data (111) is input, a state value c6 is determined from a combination of the already updated state value c2 of the state register 3 and the encoded data (111). It is held in the status register 3 as the next status value.

However, in the case of this combination, the corresponding column is blank in the decoded data table DTBL of FIG.
No decrypted data will be generated. Therefore, in this case, only the state value is updated to c6.

Next, when the fourth encoded data (001) is input,
From the combination of this and the state value c6 held in the state value register 3, the next state value c0 and the decoded data s6s1 are determined. The decoded data s6s1 is two pieces of data, and outputs corresponding signal information to the decoded data generator 4,
Here, decoded data of the symbols s6 and s1 is output.

Thus, variable length codewords (00), (110), (1
1110) and (01) are sequentially input as coded data (001), (101), (111), and (001) in a fixed bit length unit, and these are set as decoded data s0, s4, s6, and s1. Decoding can be performed sequentially.

[Effects of the Invention] As described above, according to the present invention, decoding processing of one piece of encoded data can be performed each time encoded data is input, and thus decoding speed can be improved. In addition, since the number of state values held internally is determined by the number of symbols, it is possible to decode coded data having a large maximum word length without increasing the memory size. It can be composed of a large-scale circuit.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention, FIG. 2 is a data table showing a symbol-codeword contrast relationship used in the above embodiment, and FIG. 3 is a series of symbols used in the above embodiment. FIG. 4 is an explanatory diagram showing a conversion relationship to an encoded data sequence, FIG. 4 is an explanatory diagram of a binary tree used in the above embodiment, and FIG.
FIG. 6 is a state value data table used in the above embodiment, FIG. 6 is a decoded data table used in the above embodiment, and FIG. 7 is a circuit block diagram of a conventional example. 1 state transition circuit 2 decoded information output circuit 3 state register 4 decoded data generator 5 state / undecoded data converter 6 undecoded data transition 7 undecoded Data / state converter 8: State / undecoded data converter 9: Decoded information generator, 10: Encoded data 11: Decoded information, 12: Clock 13: Decoded data

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Claims (1)

(57) [Claims] 1. Code data of variable bit lengths corresponding to a plurality of symbols are packed in a fixed bit length unit and coded data sequentially inputted can be decoded in a previous decoding process. Based on a combination of a status register that stores the bit pattern of the undecoded data portion that did not exist as a status, a bit pattern of the newly input encoded data, and a status stored in the status register. A state transition circuit for generating a new state value; information on decoded data based on a combination of the bit pattern of the newly input encoded data and the state stored in the state register. An information signal comprising: a decoded information output circuit for generating a decoded data; and a decoded data generator for generating decoded data from the information of the decoded data. No. equipment.