JP3229690B2 - Variable length code decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder for a variable-length code such as a Huffman code used in various high-efficiency coding devices.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional variable-length code decoder. In this decoder, as shown in FIG.
There are eight types of output symbols of “〜” to “7”, and one symbol “0” to “7” is assigned to each of seven types of variable length codes consisting of 1 to 5 bits.

FIG. 4 shows the contents of the symbol output table 13 in the decoder of FIG. That is, in the symbol output table 13, for each of the seven types of variable length codes,
A bit length, a variable length code and an output symbol are stored.

The input bit string sent to the decoder is input to the shift register 11 one bit at a time. Each time an input bit string is input to the shift register 11 one bit at a time, the content of the counter 2 is incremented by one. Then, a variable-length code and a symbol corresponding to the number of bits according to the content of the counter 2 are read out from the symbol output table 13 and output.

The variable length code output from the symbol output table 13 is sent to a comparator 14, and the symbols output from the symbol output table 13 are sent to a symbol output circuit 15. The comparator 14 determines whether or not the variable length code from the symbol output table 13 matches the contents of the shift register 11. If they match, the symbol input to the symbol output circuit 15 is output as a decoder output, and the shift register 11 and the counter 12 are reset.

From the symbol output table 13 to the comparator 1
4 does not match the contents of the shift register 11, the variable length code and the symbol for the next candidate having the same bit length are output from the symbol output table 13 and the same operation is performed. Is repeated.

As a result of performing the above operation on the variable length codes of all the candidates of the same bit length, if there is no code that matches the contents of the shift register 11, the next one bit from the input bit string is The content is taken into the shift register 11 and the content of the counter 12 is updated. And
A variable length code corresponding to the updated content of the counter 12 is output from the symbol output table 13 and compared with the content of the shift register 11. Then, the same operation as described above is repeated.

[0008]

The conventional decoder shown in FIG. 5 has a problem that the average decoding processing time per one symbol (one variable length code) becomes longer, and
Since the decoding processing time per symbol is not constant,
There is a problem that some timing adjustment needs to be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable length code decoder capable of shortening the average decoding processing time per symbol and keeping the decoding processing time per symbol constant.

[0010]

SUMMARY OF THE INVENTION A variable length code decoder according to the present invention is a variable length code decoder for decoding a bit sequence composed of a plurality of variable length codes into fixed length symbols. A storage unit in which a bit sequence corresponding to the maximum code length of the code is fetched and stored, a decoding unit for obtaining a symbol and a bit length for a variable length code corresponding to the content of the storage unit based on a table created in advance, Updating means for fetching a bit string from the input bit string by the bit length determined by the decoding means into the storage means, and updating the contents of the storage means to new contents of the maximum code length, as the decoding means, for each different predetermined data of the maximum code length assigned to each variable length code, respectively, to each other different
And one-to-one correspondence with symbols for variable-length codes
And it is indexed on the basis of the stored table,
First to find an index for the contents of the storage means
A decoding unit and, for each index, a second symbol and bit length for the index determined by the first decoding unit, based on a table storing data of the symbol and bit length for the corresponding variable length code. And a decoding unit.

[0011]

[0012]

[0013]

The bit string corresponding to the maximum code length of the variable length code is fetched from the input bit string and stored in the storage means. The symbol and bit length for the variable length code corresponding to the contents of the storage means are obtained based on a table created in advance. The determined symbol is output as a decoder output. On the other hand, a bit string is fetched from the input bit string by the determined bit length into the storage means, the content of the storage means is updated to a new content of the maximum code length, and a similar operation is performed on the updated content. Will be

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a variable length code decoder.
In this decoder, there are eight types of output symbols "0" to "7" as shown in FIG.
One symbol “0” for each type of variable length code
~ "7" is assigned. The diagram on the left side of FIG. 4 shows a procedure for creating a variable-length code.

This decoder comprises a counter circuit 1, a shift register 2, an index ROM 3, and a decoding ROM 4.
It is composed of In this decoder, the shift register 2 is loaded with the number of bits of the variable length code having the maximum code length, that is, 5 bits, out of the seven types of variable length codes.

The contents of the index ROM 3 are shown in FIG. For each of the seven types of variable-length codes, a 5-bit data or a 5-bit data group that includes a variable-length code as it is and can take a 5-bit code string with the first bit of the variable-length code as the most significant bit is a shift register Each is assigned as output data. Then, different index numbers are stored in the index ROM 3 in relation to each shift register output data.

In this example, the output data of the shift register for the variable length code "1" is 10000 to 11111.
However, the shift register output data for the variable length code “01” includes 01000 to 01111, and the variable length code “00”.
The shift register output data for 11 ″ is 0011
0-00111 are shift register output data for the variable-length code “0010”.
However, the variable-length code itself is assigned to the shift register output data for each of the other four types of 5-bit variable-length codes.

As the index for the shift register output data assigned to each variable length code, the same number as the symbol corresponding to each variable length code shown in FIG. 4 is used for convenience of explanation. .

The contents of the decoding ROM 4 are shown in FIG. The decoding ROM 4 stores a symbol and a bit length in relation to each index in the index ROM 3. The symbol for each index is a symbol for the variable length code corresponding to each index, and the bit length for each index is the bit length of the variable length code corresponding to each index (see FIG. 4).

The input bit string sent to the decoder is converted by the counter circuit 1 into a maximum bit length (N
= 5) The minute is controlled to be loaded into the shift register 2. Contents (0 to 3) loaded into the shift register 2
1 is transmitted to the index ROM 3. From the index ROM 3, an index (3-bit data of 0 to 7) corresponding to the sent shift register output is output.

The index output from the index ROM 3 is sent to the decoding ROM 4. ROM for decryption
From 4, the symbols “0” to “7” and the bit length M corresponding to the sent index are read. The symbol read from the decoding ROM 4 is output as a decoder output.

The bit length M read from the decoding ROM 4 is sent to the counter circuit 1 and controlled so that the contents of the shift register 2 are updated by M bits. That is, M bits of data from the input bit string are sent to the shift register 2, and the contents of the shift register 2 are updated to new 5-bit data. Then, based on the updated contents of the shift register 2, the decoding process for the next variable length code is performed in the same manner as described above. By repeating the above operation, the input bit string is decoded.

[0024]

According to the above embodiment, since there is no loop processing during the decoding processing for one symbol as in the conventional example shown in FIG. 5, high-speed decoding processing is possible, and the average decoding processing time per symbol is reduced. Can be shortened. Further, the decoding processing time per symbol can be made constant. Further, since there is no loop processing during the decoding process for one symbol and the symbol read from the decoding ROM 3 becomes the decoder output as it is, the conventional comparator 14 and symbol output circuit 15 shown in FIG. And the circuit configuration is simplified.

[0026]

According to the present invention, the average decoding processing time per symbol can be shortened and the decoding processing time per symbol can be made constant.

[Brief description of the drawings]

FIG. 1 is an electric block diagram showing an embodiment of a variable length code decoder according to the present invention.

FIG. 2 is a schematic diagram showing contents of an index ROM.

FIG. 3 is a schematic diagram showing contents of a decoding ROM;

FIG. 4 is a schematic diagram illustrating a relationship between a variable-length code and a symbol and a procedure for creating the variable-length code.

FIG. 5 is an electric block diagram showing a conventional variable-length code decoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter circuit 2 Shift register 3 Index ROM 4 Decoding ROM

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/42

Claims (1)

(57) [Claims] 1. A variable-length code decoder for decoding a bit sequence composed of a plurality of variable-length codes into fixed-length symbols, wherein a bit sequence of the maximum code length of the variable-length code is fetched from an input bit sequence and stored. Storage means, a symbol and a bit length for a variable length code corresponding to the contents of the storage means, based on a table created in advance, and a bit string from the input bit string by the bit length determined by the decoding means. the capture in the storage means comprises updating means for updating the new content of the maximum code length of the contents of said memory means, said decoding means, assigned to the variable length code respectively
For each predetermined data different from each other by the maximum code length,
Different from each other and one pair with the symbol for the variable length code
One based on the table that stores the corresponding index
The index for the contents of the storage means
And a first decoding unit for each index.
And bit length data for variable length codes
Is obtained by the first decoding unit based on the table in which
Symbol and bit length for given index
And a second decoding unit that obtains the following .