JPH05145107A - Optical semiconductor device - Google Patents

Optical semiconductor device

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Publication number
JPH05145107A
JPH05145107A JP3302026A JP30202691A JPH05145107A JP H05145107 A JPH05145107 A JP H05145107A JP 3302026 A JP3302026 A JP 3302026A JP 30202691 A JP30202691 A JP 30202691A JP H05145107 A JPH05145107 A JP H05145107A
Authority
JP
Japan
Prior art keywords
type
epitaxial layer
region
substrate
cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3302026A
Other languages
Japanese (ja)
Other versions
JP3086514B2 (en
Inventor
Keiji Mita
恵司 三田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP03302026A priority Critical patent/JP3086514B2/en
Publication of JPH05145107A publication Critical patent/JPH05145107A/en
Application granted granted Critical
Publication of JP3086514B2 publication Critical patent/JP3086514B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To develop a further integrated circuit from a high sensibility cathode common type photodiode group by partially increasing the thickness of the N type region which serves as a cathode. CONSTITUTION:An epitaxial layer 14 is adopted for a common cathode. On the surface of the epitaxial layer are formed a plurality of P<+> type anode regions 17, thereby forming photodiode groups. There are formed N type well regions 19 having low concentration impurities respectively on the surface of a board 13 equivalent to each of the anode regions 17.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数個のカソードコモ
ン型ホトダイオードと周辺回路とを一体化した光半導体
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device in which a plurality of cathode common type photodiodes and peripheral circuits are integrated.

【0002】[0002]

【従来の技術】受光素子と周辺回路とを一体化してモノ
リシックに形成した光半導体装置は、受光素子と回路素
子とを別個に作ってハイブリッドIC化したものと異な
り、コストダウンが期待でき、また、外部電磁界による
雑音に対して強いというメリットを持つ。そのため、こ
のような装置は電気信号を光信号に変換して伝送する光
通信用としての用途のみならず、CDやLD等の光学的
記憶装置のピックアップ用としての用途にまで拡大する
動きがある。
2. Description of the Related Art An optical semiconductor device in which a light-receiving element and a peripheral circuit are integrated to form a monolithic device can be expected to reduce costs, unlike a hybrid IC in which a light-receiving element and a circuit element are separately formed. , It has a merit that it is strong against noise caused by an external electromagnetic field. Therefore, there is a movement to expand such an apparatus not only for optical communication for converting an electric signal into an optical signal for transmission but also for use as a pickup for an optical storage device such as a CD or LD. .

【0003】従来の光ピックアップ用の光半導体装置
(ディスクリート)は、N型基板の表面にP型領域を形
成してPN接合ホトダイオードとし、6個のホトダイオ
ードPD1〜PD6を図3に示すように配置したもので
ある。PD1とPD6はトラッキング用のホトダイオー
ドであり、信号検出用のビームがトラックからずれない
よう制御するために設けられている。PD2〜PD4は
フォーカス用のホトダイオードであり、盤に記録された
信号を電気信号に変換すると同時に、PD2〜PD4の
各々の光電流を比較して光ビームのフォーカスが合致し
ているか否かを判定するために設けられている。
In a conventional optical semiconductor device (discrete) for an optical pickup, a P-type region is formed on the surface of an N-type substrate to form a PN junction photodiode, and six photodiodes PD1 to PD6 are arranged as shown in FIG. It was done. PD1 and PD6 are tracking photodiodes, and are provided for controlling the beam for signal detection so as not to shift from the track. PD2 to PD4 are photodiodes for focusing, which convert the signals recorded on the board into electrical signals and, at the same time, compare the photocurrents of PD2 to PD4 to determine whether the light beams are in focus. It is provided to do so.

【0004】このような光ピックアップ用ホトダイオー
ド群をIC化する場合、P型基板がGND(接地電位)
となることから、N型エピタキシャル層をP+分離領域
で分離し、基板とエピとのPN接合をホトダイオードと
したアノードコモン型の方が製造上のメリットがある。
しかしながら、従来のディスクリート製品が全てカソー
ドコモンで製作され、回路技術もカソードコモンに対応
して開発されてきた経緯から、上記ホトダイオードをI
C化する場合もカソードコモン型にする要求が強い。
When such a photodiode group for optical pickup is integrated into an IC, the P-type substrate is GND (ground potential).
Therefore, the anode common type in which the N type epitaxial layer is separated by the P + isolation region and the PN junction between the substrate and the epi is used as a photodiode is more advantageous in manufacturing.
However, from the background that all conventional discrete products were manufactured with common cathode and circuit technology was developed corresponding to common cathode,
There is a strong demand for a cathode common type when converting to C.

【0005】そこで、上記要求に応えるべくカソードコ
モン型のホトダイオード群を形成した例が図4である。
即ち、P型基板(1)上に形成したN型エピタキシャル
層(2)をP+型分離領域(3)で分離して共通のカソ
ード領域とし、エピタキシャル層(2)の表面に6個の
+型アノード領域(4)を形成したものである。
Therefore, FIG. 4 shows an example in which a cathode common type photodiode group is formed to meet the above demand.
That is, the N-type epitaxial layer (2) formed on the P-type substrate (1) is separated by the P + -type separation region (3) to form a common cathode region, and six P layers are formed on the surface of the epitaxial layer (2). The + type anode region (4) is formed.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、CDピ
ックアップ用等に利用される波長780nmの光はシリ
コン表面から15〜20μ位の深さまで十分に到達でき
るので、深く侵入した光をどの程度光電流として回収で
きるかがホトダイオードの感度を左右することになる。
そのため、P型基板を共通アノードとしたアノードコモ
ン型は基板深部で発生した光生成キャリアを光電流に寄
与できるので感度が高いのに対し、図4のカソードコモ
ン型は基板(1)深部で発生した光生成キャリアが無効
電流となってしまうので感度が低いという欠点があっ
た。
However, since the light having a wavelength of 780 nm used for CD pickup and the like can sufficiently reach the depth of about 15 to 20 .mu.m from the silicon surface, how much deeply penetrating light is converted into a photocurrent. Whether it can be recovered or not will affect the sensitivity of the photodiode.
Therefore, the anode common type using the P-type substrate as the common anode can contribute to the photocurrent by the photo-generated carriers generated in the deep portion of the substrate, while the cathode common type in FIG. Since the photo-generated carriers become a reactive current, there is a drawback that the sensitivity is low.

【0007】尚、エピタキシャル層(2)の厚みを厚く
すれば変換効率が向上するが、エピタキシャル層(2)
の厚みは共存する他の素子(NPNトランジスタ等)の
特性に大きく関係し、また微細加工の点からも単純に厚
くすることはできない。
Although the conversion efficiency is improved by increasing the thickness of the epitaxial layer (2), the epitaxial layer (2)
Is greatly related to the characteristics of other coexisting elements (NPN transistor, etc.), and cannot be simply increased from the viewpoint of fine processing.

【0008】[0008]

【課題を解決するための手段】本発明は上述した欠点に
鑑み成されたもので、ホトダイオード群を形成する複数
個のP+型アノード領域(17)の下部に、各々のアノ
ード領域(17)と対応するように基板(13)表面か
ら拡散形成したN型ウェル領域(19)を具備すること
により、入射光に対する感度が高く且つ各ダイオード間
のクロストークを向上したカソードコモン型のホトダイ
オードを提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks. Under the plurality of P + -type anode regions (17) forming a photodiode group, each anode region (17) is formed. By providing an N-type well region (19) diffused from the surface of the substrate (13) so as to correspond to the above, a common cathode type photodiode having high sensitivity to incident light and improved crosstalk between the diodes is provided. To do.

【0009】[0009]

【作用】本発明によれば、P+型アノード領域(17)
の下部に各々N型ウェル領域(19)を有するので、N
型ウェル領域(19)の分だけカソードとなる領域の厚
みを増大できる。また、P+型アノード領域(17)の
各々にN型ウェル領域(19)を設けるので、ウェル領
域(19)の間のP型基板(13)で発生した光生成キ
ャリアは光電流に寄与できず、無効電流となる。
According to the present invention, the P + type anode region (17)
Since each has an N-type well region (19) underneath,
The thickness of the region serving as the cathode can be increased by the amount of the mold well region (19). In addition, since the N + well region (19) is provided in each of the P + -type anode regions (17), photo-generated carriers generated in the P-type substrate (13) between the well regions (19) can contribute to photocurrent. Instead, it becomes a reactive current.

【0010】[0010]

【実施例】図1に本発明のホトダイオード内蔵ICの断
面構造を示す。同図は、図2のPD1〜PD6を形成し
たホトダイオード部(11)と周辺回路の一部としての
NPNトランジスタ部(12)を示している。図1にお
いて、(13)はP型シリコン半導体基板、(14)は
基板(13)上に気相成長法にて形成したN型エピタキ
シャル層、(15)は基板(13)表面に形成したN+
型の埋め込み層、(16)はエピタキシャル層(14)
を接合分離するP+型分離領域である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a sectional structure of an IC with a built-in photodiode according to the present invention. The figure shows a photodiode section (11) forming PD1 to PD6 of FIG. 2 and an NPN transistor section (12) as a part of a peripheral circuit. In FIG. 1, (13) is a P-type silicon semiconductor substrate, (14) is an N-type epitaxial layer formed on the substrate (13) by a vapor phase growth method, and (15) is N formed on the surface of the substrate (13). +
Type buried layer, (16) is epitaxial layer (14)
Is a P + -type isolation region for junction isolation.

【0011】分離領域(16)で囲まれたエピタキシャ
ル層(14)の表面には図3に示すパターンで複数個の
+型アノード領域(17)を形成し、アノード領域
(17)とエピタキシャル層(14)とのPN接合でト
ラッキング用ホトダイオードPD1,PD6とフォーカ
ス用ホトダイオードPD2〜PD4を形成する。トラッ
キング用ホトダイオードPD1,PD6とフォーカス用
ホトダイオードPD2〜PD4の間のエピタキシャル層
(14)表面およびホトダイオード群を囲むエピタキシ
ャル層(14)表面には、両ホトダイオードを分離し且
つカソードの取出しとなるN+型カソードコンタクト領
域(18)を形成する。カソードとなるエピタキシャル
層(14)が全ホトダイオード共用であるので、これら
のホトダイオードはカソードコモン型として構成され
る。
On the surface of the epitaxial layer (14) surrounded by the isolation region (16), a plurality of P + type anode regions (17) are formed in the pattern shown in FIG. 3, and the anode region (17) and the epitaxial layer are formed. The tracking photodiodes PD1 and PD6 and the focusing photodiodes PD2 to PD4 are formed by the PN junction with (14). Epitaxial layer between the tracking photodiode PD1, PD6 and focusing photodiode PD2~PD4 (14) surface and the epitaxial layer (14) surface surrounding the photodiode group, N + -type which is a and the cathode of the extraction were separated both photodiodes A cathode contact region (18) is formed. Since the epitaxial layer (14) serving as the cathode is shared by all the photodiodes, these photodiodes are constructed as a cathode common type.

【0012】ホトダイオード部(11)下の基板(1
3)表面には、夫々がP+型アノード領域(17)と対
応する位置に設けたN型ウェル領域(19)を複数個形
成する。N型ウェル領域(19)は、エピタキシャル層
(14)側へのはい上りを抑え、基板(13)内部に十
分深く拡散されている形状とする。分離領域(16)で
囲まれた他のエピタキシャル層(14)の表面には、P
型ベース領域(20)、N+型エミッタ領域(21)お
よびN+型コレクタコンタクト領域(22)を形成して
NPNトランジスタ(12)とする。ホトダイオード部
(11)とNPNトランジスタ部(12)とでエピタキ
シャル層(14)の不純物濃度が合致しなければ、その
不純物濃度をホトダイオード部(11)に合致させ、N
PNトランジスタ部(12)はN型のウェルを拡散形成
して不純物濃度を増大した構成としても良い。
The substrate (1) below the photodiode portion (11)
3) On the surface, a plurality of N-type well regions (19) are formed at positions corresponding to the P + -type anode regions (17). The N-type well region (19) has a shape that suppresses rising to the epitaxial layer (14) side and is diffused sufficiently deep inside the substrate (13). The surface of the other epitaxial layer (14) surrounded by the isolation region (16) has P
A type base region (20), an N + type emitter region (21) and an N + type collector contact region (22) are formed to form an NPN transistor (12). If the impurity concentration of the epitaxial layer (14) does not match between the photodiode portion (11) and the NPN transistor portion (12), match the impurity concentration with the photodiode portion (11), and
The PN transistor section (12) may have a structure in which an N type well is diffused to increase the impurity concentration.

【0013】エピタキシャル層(14)の表面は酸化シ
リコン(SiO2)等の絶縁膜(23)で被覆され、A
l電極(24)を配設することで各素子の素子間接続を
行っている。ホトダイオード部(11)上の絶縁膜(2
3)は反射防止膜としての適切な膜厚に選択され、ホト
ダイオード部(11)以外の領域は余分な光入射がない
ように図示せぬ遮光膜で被覆されている。そして、例え
ば波長780nmの信号光がホトダイオード部(11)
に到達できるよう、窓付きのパッケージ又は前記波長の
光が透過可能な樹脂モールドパッケージに収納されて光
半導体装置となる。
The surface of the epitaxial layer (14) is covered with an insulating film (23) such as silicon oxide (SiO 2 ).
By providing the l electrode (24), the elements are connected to each other. Insulating film (2) on the photodiode part (11)
3) is selected to have an appropriate film thickness as an antireflection film, and a region other than the photodiode portion (11) is covered with a light shielding film (not shown) so as to prevent excessive light incidence. Then, for example, the signal light having a wavelength of 780 nm is supplied to the photodiode section (11).
So as to reach the optical semiconductor device.

【0014】以上の本発明による光半導体装置は、基板
(13)表面にN型ウェル領域(19)を具備するの
で、ホトダイオード部(11)では実質的にエピタキシ
ャル層(14)の膜厚を厚くしたのと等価になり、ウェ
ル領域(19)の分だけカソードとなるN型領域の厚み
を拡大できる。例えば、エピタキシャル層(14)の膜
厚が6μ、入射光が前記波長780nmの光であるとす
ると、その光はエピタキシャル層(14)の表面から1
5〜20μ位の深さまで達するので、N型ウェル領域
(19)の拡散深さを8〜10μとしておけば、入射光
が到達する領域の殆どをN型カソードとすることがで
き、入射光の殆どを光電流に寄与させることができる。
Since the optical semiconductor device according to the present invention described above is provided with the N-type well region (19) on the surface of the substrate (13), the thickness of the epitaxial layer (14) is substantially increased in the photodiode portion (11). This is equivalent to the above, and the thickness of the N-type region serving as the cathode can be increased by the amount of the well region (19). For example, assuming that the thickness of the epitaxial layer (14) is 6 μm and the incident light is the light having the wavelength of 780 nm, the light is 1 from the surface of the epitaxial layer (14).
Since the depth reaches about 5 to 20 μ, if the diffusion depth of the N-type well region (19) is set to 8 to 10 μ, most of the region where the incident light reaches can be the N-type cathode and the incident light Most can contribute to photocurrent.

【0015】このように拡散深さが深いN型ウェル領域
を実現するため、本願の装置は例えば以下のフローによ
り製造することができる。先ず基板(13)表面にN型
ウェル領域(19)形成用の選択マスクを形成し、選択
マスクによりリン(P)等のN型不純物をドーズ量10
13程度選択的にイオン注入し、基板(13)全体を高温
長時間熱処理してN型ウェル領域(19)を十分な深さ
にまで拡散する。その後は、N+型埋込層(15)の形
成、エピタキシャル層(14)の形成、P+型分離領域
(16)の形成、ベース拡散、エミッタ拡散という一般
的なプロセスで製造される。このようにN型ウェル領域
(19)を最初に拡散形成しておくことにより、エピタ
キシャル層(14)側へのはい上りが殆ど無い構造が得
られる。また、低不純物濃度のN型ウェル領域(19)
が容易に深く形成されるよう、基板(13)の比抵抗を
6〜12Ω・cm、又は40〜60Ω・cmと一般的な
ものより低不純物濃度の基板(13)を使用すると良
い。尚、ベース領域(20)とアノード領域(17)を
同時工程で、エミッタ領域(21)とカソードコンタク
ト領域(18)を同時工程で夫々形成すると、製造工程
を簡略化できる。
In order to realize the N-type well region having a large diffusion depth as described above, the device of the present application can be manufactured by the following flow, for example. First, a selection mask for forming the N-type well region (19) is formed on the surface of the substrate (13), and an N-type impurity such as phosphorus (P) is dosed with the selection mask at a dose of 10
About 13 ions are selectively implanted, and the entire substrate (13) is heat-treated at high temperature for a long time to diffuse the N-type well region (19) to a sufficient depth. After that, the N + type buried layer (15) is formed, the epitaxial layer (14) is formed, the P + type isolation region (16) is formed, and the base diffusion process and the emitter diffusion process are performed. By thus diffusing and forming the N-type well region (19) first, it is possible to obtain a structure in which there is almost no rise to the epitaxial layer (14) side. Also, a low impurity concentration N-type well region (19)
The substrate (13) having a specific resistance of 6 to 12 Ω · cm or 40 to 60 Ω · cm, which is lower in impurity concentration than a general substrate, is preferably used so that the substrate can be formed deep easily. The manufacturing process can be simplified by forming the base region (20) and the anode region (17) in the same process and the emitter region (21) and the cathode contact region (18) in the same process.

【0016】このようなホトダイオード群の性能を示す
1つの指標として、隣接するホトダイオード間の分解能
を表すクロストローク特性がある。クロストローク特性
は、図3の拡大断面図で示すようにアノード領域(1
7)とアノード領域(17)の間の領域で発生した光生
成キャリア(25)が拡散によってどちらが一方のアノ
ード領域(17)に達しアノード電流として検出される
ことに起因する。従って、このような領域で発生する光
生成キャリア(25)の量が少なければ、そして発生し
た光生成キャリア(25)がアノード領域(17)に達
しなければ、クロストーク特性を改善できる。尚、ホト
ダイオード内蔵ICは、基板(13)を接地電位(GN
D)にすると共に、カソードとなるエピタキシャル層
(14)に+5V程度、アノード領域(17)に+3V
程度の電位を印加してホトダイオードを逆バイアス状態
で動作させる。
As one index showing the performance of such a photodiode group, there is a cross stroke characteristic representing the resolution between adjacent photodiodes. As shown in the enlarged cross-sectional view of FIG.
This is because the photo-generated carriers (25) generated in the region between 7) and the anode region (17) reach one of the anode regions (17) by diffusion and are detected as an anode current. Therefore, if the amount of photogenerated carriers (25) generated in such a region is small and if the generated photogenerated carriers (25) do not reach the anode region (17), the crosstalk characteristics can be improved. For the IC with a built-in photodiode, the substrate (13) is connected to the ground potential (GN
D), about + 5V in the epitaxial layer (14) which becomes the cathode, and + 3V in the anode region (17).
The photodiode is operated in a reverse bias state by applying a potential of the order.

【0017】本発明の構造によれば、N型ウェル領域
(19)が部分的に除去されていることによって、アノ
ード領域(17)とアノード領域(17)の間の領域は
カソードとなるN型領域の厚みがウェル領域(19)を
設けた部分の厚みより小さくなる。まして、基板(1
3)からのはい上り拡散の分(27)によってその厚み
が一層小さくなる。よってカソードでの光生成キャリア
(25)の発生が少ない。また、ウェル領域(19)で
挾まれたP型基板(13)においても光生成キャリア
(26)が発生するが、ここで発生した光生成キャリア
(26)は基板(13)とエピタキシャル層(14)間
のダイオード電流となり、ホトダイオードの電流には関
与しない。従って、ウェル領域(19)を全面に形成す
るよりはクロストーク特性を改善できる。
According to the structure of the present invention, the N-type well region (19) is partially removed, so that the region between the anode regions (17) and (17) serves as a cathode. The thickness of the region is smaller than the thickness of the portion where the well region (19) is provided. Furthermore, the substrate (1
The thickness is further reduced by the amount (27) of upward diffusion from 3). Therefore, the generation of photogenerated carriers (25) at the cathode is small. Photogenerated carriers (26) are also generated in the P-type substrate (13) sandwiched between the well regions (19). The photogenerated carriers (26) generated here are generated in the substrate (13) and the epitaxial layer (14). ), The diode current, and does not contribute to the photodiode current. Therefore, the crosstalk characteristic can be improved rather than forming the well region (19) on the entire surface.

【0018】[0018]

【発明の効果】以上に説明した通り、本発明によればア
ノード領域(17)の個々にN型ウェル領域(19)を
有するので、光吸収率の高い高感度のカソードコモン型
のホトダイオード群をIC化できる利点を有する。しか
も、個々にN型ウェル領域(19)を設けたので、隣接
するホトダイオード間のクロストークを低減できる利点
をも有する。
As described above, according to the present invention, since each anode region (17) has an N-type well region (19), a group of high-sensitivity cathode common type photodiodes having a high light absorption rate can be provided. It has the advantage of being integrated into an IC. Moreover, since the N-type well regions (19) are individually provided, there is an advantage that crosstalk between adjacent photodiodes can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を説明するための断面図。FIG. 1 is a sectional view for explaining the present invention.

【図2】本発明を説明するための拡大断面図。FIG. 2 is an enlarged sectional view for explaining the present invention.

【図3】ホトダイオード群を示す平面図。FIG. 3 is a plan view showing a photodiode group.

【図4】従来例を説明するための断面図。FIG. 4 is a cross-sectional view for explaining a conventional example.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 受光用ホトダイオードと周辺回路とを一
体化した光半導体装置であって、 一導電型の半導体基板の上に形成した逆導電型のエピタ
キシャル層と、 前記エピタキシャル層の表面に互いに近接して形成した
複数個の一導電型のアノード領域と、 前記基板の表面に、各々が個々のアノード領域と対応す
るように複数個形成した逆導電型低不純物濃度のウェル
領域とを具備することを特徴とする光半導体装置。
1. An optical semiconductor device in which a photodiode for light reception and a peripheral circuit are integrated, wherein an epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type and a surface of the epitaxial layer are close to each other. A plurality of one-conductivity-type anode regions formed as described above, and a plurality of reverse-conductivity-type well regions of low impurity concentration formed on the surface of the substrate so as to correspond to the individual anode regions. An optical semiconductor device characterized by:
【請求項2】 前記逆導電型のウェル領域が前記基板の
表面から下方向に深く形成されていることを特徴とする
請求項1記載の光半導体装置。
2. The optical semiconductor device according to claim 1, wherein the well region of the opposite conductivity type is formed deeper downward from the surface of the substrate.
【請求項3】 前記エピタキシャル層の他の領域に縦型
バイポーラトランジスタを具備することを特徴とする請
求項1記載の光半導体装置。
3. The optical semiconductor device according to claim 1, further comprising a vertical bipolar transistor in another region of the epitaxial layer.
JP03302026A 1991-11-18 1991-11-18 Optical semiconductor device Expired - Fee Related JP3086514B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03302026A JP3086514B2 (en) 1991-11-18 1991-11-18 Optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03302026A JP3086514B2 (en) 1991-11-18 1991-11-18 Optical semiconductor device

Publications (2)

Publication Number Publication Date
JPH05145107A true JPH05145107A (en) 1993-06-11
JP3086514B2 JP3086514B2 (en) 2000-09-11

Family

ID=17904010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03302026A Expired - Fee Related JP3086514B2 (en) 1991-11-18 1991-11-18 Optical semiconductor device

Country Status (1)

Country Link
JP (1) JP3086514B2 (en)

Also Published As

Publication number Publication date
JP3086514B2 (en) 2000-09-11

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