JPH05144765A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05144765A
JPH05144765A JP30742991A JP30742991A JPH05144765A JP H05144765 A JPH05144765 A JP H05144765A JP 30742991 A JP30742991 A JP 30742991A JP 30742991 A JP30742991 A JP 30742991A JP H05144765 A JPH05144765 A JP H05144765A
Authority
JP
Japan
Prior art keywords
film
oxide film
bpsg film
opening
bpsg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30742991A
Other languages
Japanese (ja)
Inventor
Kiyoshi Morimoto
清 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP30742991A priority Critical patent/JPH05144765A/en
Publication of JPH05144765A publication Critical patent/JPH05144765A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent doping to a region where boron or phosphorus or the like is diffused during heat treatment from a BPSG film. CONSTITUTION:After an aperture is opened in a BPSG film 5 to expose a diffused region 2 on a silicon substrate 1, an upper oxide film 6 is formed. Moreover, an aperture is opened on the upper oxide film 6 in such a manner that the upper oxide film 6 is left at the surface of BPSG film 5 and the side surface of aperture. Thereafter, the heat treatment is carried out to form aluminum wirings. Thereby, fluctuation of resitances in the diffused region and precipitation of silicon in the aluminum wiring process can be controlled, as much improving reliability of a semiconductor device.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特にBPSG膜の開孔方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of opening a BPSG film.

【0002】[0002]

【従来の技術】図3,図4は、従来のBPSG(Boro-Ph
ospho Silicate Glass)膜に開孔を形成する工程を示す
断面図である。これらの図において、1はシリコン基
板、2はN+ あるいはP+ の拡散領域、3は熱酸化膜、
4はゲート電極や配線(以下、配線という)、5はBP
SG膜である。
2. Description of the Related Art FIGS. 3 and 4 show conventional BPSG (Boro-Ph).
It is sectional drawing which shows the process of forming an opening in an ospho Silicate Glass) film. In these figures, 1 is a silicon substrate, 2 is a diffusion region of N + or P + , 3 is a thermal oxide film,
4 is a gate electrode or wiring (hereinafter referred to as wiring), 5 is BP
It is an SG film.

【0003】まず、図3(a),(b)のフローについ
て説明する。図3(a)のように、配線4が形成された
シリコン基板1全面に絶縁膜としてBPSG膜5を形成
して、平坦化の為に熱処理によってBPSG膜5をリフ
ローする。次に、図3(b)のように、シリコン基板1
上に形成された拡散領域2との接合のためにBPSG膜
5を開孔する。
First, the flow of FIGS. 3A and 3B will be described. As shown in FIG. 3A, a BPSG film 5 is formed as an insulating film on the entire surface of the silicon substrate 1 on which the wiring 4 is formed, and the BPSG film 5 is reflowed by heat treatment for planarization. Next, as shown in FIG. 3B, the silicon substrate 1
A BPSG film 5 is opened for bonding with the diffusion region 2 formed above.

【0004】また、図4(a),(b)のフローでは、
図4(a)のように、図3(a)と同様にBPSG膜5
を形成した後、図4(b)のように、BPSG膜5を開
孔するのに、最初にウエットエッチングを行い、次に、
異方性のドライエッチングを行うと、開孔部が上に開い
た形になり、次工程のアルミ配線工程でのアルミ配線の
被覆性が向上する。上記のように、BPSG膜5を開孔
した後、熱処理を施してアルミ配線(図示せず)が形成
される。
Further, in the flow of FIGS. 4 (a) and 4 (b),
As shown in FIG. 4A, the BPSG film 5 is formed similarly to FIG.
4B, the wet etching is first performed to open the BPSG film 5, and then the BPSG film 5 is formed.
When anisotropic dry etching is performed, the opening portion is opened upward, and the coverage of aluminum wiring in the next aluminum wiring step is improved. As described above, after the BPSG film 5 is opened, heat treatment is performed to form aluminum wiring (not shown).

【0005】[0005]

【発明が解決しようとする課題】従来のBPSG膜5の
開孔工程は以上のようにして行われているので、次工程
の熱処理の際にBPSG膜5のボロン,リンが開孔部の
拡散領域2にオートドーピングして、拡散領域2の抵抗
のばらつきを生じさせたり、アルミ配線工程でのシリコ
ン析出を助長させたりするなどの問題点があった。
Since the conventional opening process of the BPSG film 5 is performed as described above, the boron and phosphorus of the BPSG film 5 are diffused at the opening part in the heat treatment of the next process. There are problems such as auto-doping in the region 2 to cause variations in the resistance of the diffusion region 2 and to accelerate the deposition of silicon in the aluminum wiring process.

【0006】本発明は、上記のような問題点を解消する
ためになされたもので、BPSG膜の形成後の熱処理時
のBPSG膜からのボロン,リンのオートドーピングを
防ぐことができ、信頼性の高い開孔を有する半導体装置
が得られる製造方法を提供することを目的とする。
The present invention has been made in order to solve the above-mentioned problems, and it is possible to prevent the autodoping of boron and phosphorus from the BPSG film during the heat treatment after the formation of the BPSG film. It is an object of the present invention to provide a manufacturing method capable of obtaining a semiconductor device having a high aperture.

【0007】[0007]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、BPSG膜を開孔したあと、開孔部を含
むBPSG膜を保護するための酸化膜を上積みして熱処
理を行い配線を形成するものである。
According to the method of manufacturing a semiconductor device of the present invention, after forming a hole in a BPSG film, an oxide film for protecting the BPSG film including the hole is stacked and heat treatment is performed. Is formed.

【0008】[0008]

【作用】本発明における半導体装置の製造方法は、BP
SG膜の表面,開孔部の側面および開孔部に露出した拡
散領域の表面が酸化膜で被覆されることから、後工程の
熱処理時にBPSG膜のボロン,リンの拡散領域へのオ
ートドーピングを防ぐことができる。
According to the method of manufacturing a semiconductor device of the present invention, the BP
Since the surface of the SG film, the side surface of the opening, and the surface of the diffusion region exposed in the opening are covered with the oxide film, the boron and phosphorus diffusion regions of the BPSG film can be automatically doped during the heat treatment in the subsequent process. Can be prevented.

【0009】[0009]

【実施例】以下、本発明の一実施例を図について説明す
る。図1(a)〜(d)は本発明の半導体装置の製造方
法の主要工程を示す断面図である。図1において、図
3,図4と同一符号は同じものを示し、6は前記BPS
G膜5の開孔後に形成された上積み酸化膜である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1A to 1D are sectional views showing the main steps of the method for manufacturing a semiconductor device of the present invention. In FIG. 1, the same reference numerals as those in FIGS. 3 and 4 denote the same components, and 6 denotes the BPS.
It is an overlying oxide film formed after the opening of the G film 5.

【0010】次に、図1のフローについて説明する。図
1(a)に示すように、配線4上に絶縁膜としてBPS
G膜5を形成した後、平坦化のために熱処理によってB
PSG膜5をリフローする。次に、図1(b)に示すよ
うに、シリコン基板1上に形成された拡散領域2との接
合のために、BPSG膜5を開孔する。次に、図1
(c)に示すように、上積み酸化膜6を形成して、BP
SG膜5の表面および開孔部の側面と底面、つまり露出
した拡散領域2の表面をこの上積み酸化膜6で被覆す
る。さらに、図1(d)に示すように、拡散領域2との
接合のために、上積み酸化膜6を開孔する。その際、B
PSG膜5の開孔部分よりも小さくなるように上積み酸
化膜6を開孔する。このように、BPSG膜5,上積み
酸化膜6を開孔した後、熱処理を施してアルミ配線が形
成される。
Next, the flow of FIG. 1 will be described. As shown in FIG. 1A, BPS is formed on the wiring 4 as an insulating film.
After the G film 5 is formed, a B heat treatment is performed for planarization.
The PSG film 5 is reflowed. Next, as shown in FIG. 1B, the BPSG film 5 is opened for bonding with the diffusion region 2 formed on the silicon substrate 1. Next, FIG.
As shown in (c), an overlying oxide film 6 is formed and BP
The surface of the SG film 5 and the side and bottom surfaces of the opening, that is, the exposed surface of the diffusion region 2 is covered with this overlying oxide film 6. Further, as shown in FIG. 1D, the upper oxide film 6 is opened for bonding with the diffusion region 2. At that time, B
The upper oxide film 6 is opened so as to be smaller than the opening of the PSG film 5. In this way, after the BPSG film 5 and the overlying oxide film 6 are opened, heat treatment is performed to form aluminum wiring.

【0011】図2(a)〜(d)は本発明の他の実施例
を示す工程断面図である。まず、図2(a)に示すよう
に、絶縁膜としてBPSG膜5を形成した後、平坦化の
ために熱処理によってBPSG膜5をリフローする。次
に、図2(b)に示すように、シリコン基板1上に形成
された拡散領域2とのために、BPSG膜5を開孔す
る。次に、図2(c)に示すように、上積み酸化膜6を
形成して、BPSG膜5の表面および開孔部の側面を上
積み酸化膜6で被覆する。さらに、図2(d)に示すよ
うに、拡散領域2との接合のために、異方性のドライエ
ッチングによりBPSG膜5の表面と開孔部の側面に上
積み酸化膜6が残るように開孔する。このように、BP
SG膜5,上積み酸化膜6を開孔した後、熱処理を施し
てアルミ配線が形成される。
2A to 2D are process sectional views showing another embodiment of the present invention. First, as shown in FIG. 2A, after forming the BPSG film 5 as an insulating film, the BPSG film 5 is reflowed by heat treatment for planarization. Next, as shown in FIG. 2B, the BPSG film 5 is opened for the diffusion region 2 formed on the silicon substrate 1. Next, as shown in FIG. 2C, an overlying oxide film 6 is formed, and the surface of the BPSG film 5 and the side surface of the opening are covered with the overlying oxide film 6. Further, as shown in FIG. 2D, in order to bond with the diffusion region 2, an opening is performed by anisotropic dry etching so that the stacked oxide film 6 remains on the surface of the BPSG film 5 and the side surface of the opening. Make a hole. In this way, BP
After the SG film 5 and the overlying oxide film 6 are opened, heat treatment is performed to form aluminum wiring.

【0012】図2の実施例では、異方性エッチングによ
り、BPSG膜5の表面や開孔部の側面に上積み酸化膜
6が残るように開孔したが、開孔部の側面だけに残るよ
うにエッチングしてもよい。
In the embodiment shown in FIG. 2, anisotropic etching is performed so that the overlying oxide film 6 remains on the surface of the BPSG film 5 and the side surface of the opening, but it is left only on the side surface of the opening. May be etched.

【0013】[0013]

【発明の効果】以上説明したように、本発明によれば、
BPSG膜の表面および開孔部の側面が上積み酸化膜で
被覆されているので、後工程の熱処理時におけるBPS
G膜からのボロン,リンの拡散領域へのドーピングを防
ぐことができ、拡散領域の抵抗のばらつきや、アルミ配
線工程でのシリコン析出を抑えることができる効果があ
る。
As described above, according to the present invention,
Since the surface of the BPSG film and the side surface of the opening are covered with the overlying oxide film, the BPS at the time of heat treatment in the subsequent process
It is possible to prevent the diffusion of boron and phosphorus from the G film into the diffusion region, and suppress variations in resistance in the diffusion region and silicon deposition in the aluminum wiring process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法の一実施例を示
す工程断面図である。
FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

【図2】本発明の他の実施例を示す工程断面図である。FIG. 2 is a process sectional view showing another embodiment of the present invention.

【図3】従来の半導体装置の製造方法を示す工程断面図
である。
3A to 3D are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

【図4】従来の他の例を示す工程断面図である。FIG. 4 is a process sectional view showing another conventional example.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 拡散領域 3 熱酸化膜 4 配線 5 BPSG膜 6 上積み酸化膜 1 Silicon substrate 2 Diffusion region 3 Thermal oxide film 4 Wiring 5 BPSG film 6 Stacked oxide film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に絶縁膜として形成された
BPSG膜に開孔部を形成し、この開孔部に形成される
配線層と前記半導体基板に形成された拡散領域とのコン
タクトをとる半導体装置の製造方法において、前記BP
SG膜に開孔部を形成した後、前記BPSG膜の表面お
よび開孔部の側面を上積み酸化膜を形成して被覆した
後、熱処理を施し配線を形成する工程を含むことを特徴
とする半導体装置の製造方法。
1. An opening is formed in a BPSG film formed as an insulating film on a semiconductor substrate, and a wiring layer formed in the opening is contacted with a diffusion region formed in the semiconductor substrate. In the method of manufacturing a semiconductor device, the BP
After forming an opening in the SG film, a step of forming an overlying oxide film on the surface of the BPSG film and the side surface of the opening to cover it, and then performing a heat treatment to form a wiring. Device manufacturing method.
JP30742991A 1991-11-22 1991-11-22 Manufacture of semiconductor device Pending JPH05144765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30742991A JPH05144765A (en) 1991-11-22 1991-11-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30742991A JPH05144765A (en) 1991-11-22 1991-11-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05144765A true JPH05144765A (en) 1993-06-11

Family

ID=17968960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30742991A Pending JPH05144765A (en) 1991-11-22 1991-11-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05144765A (en)

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