JPS637463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.

In recent years, semiconductor devices have become increasingly highly integrated and densely packed, leading to miniaturization of impurity diffusion region patterns, hole patterns in insulating films, conductive film patterns, etc., as well as multilayer conductive films. It's becoming like that. However, in the prior art, miniaturization of the pattern of the conductive film and multilayering of the conductive film are not compatible. In other words, in order to prevent disconnection of the upper conductive film at the stepped portion of the lower conductive film, the side surface of the lower conductive film is connected to the base of the lower conductive film. In order to prevent the step from becoming vertical, we created an incline to prevent the step from becoming a sharp junction. However, this method does not allow vertical patterning of the conductive film, so it is not suitable for realizing miniaturization. A method conventionally used to prevent these defects is to use a phosphor glass film as an interlayer insulating film between the lower and upper conductive films, and after forming this phosphor glass film,
There is a method of smoothing the steps by causing the material to flow through high-temperature treatment around ℃. However, this method also has limitations in that it requires the use of a phosphorus glass film and that it must be treated at a high temperature of around 1000°C, which limits its range of use. That is, in addition to the phosphorus glass film, interlayer insulating films include oxide films and alumina films produced by vapor phase growth, and oxide films and nitride films produced by plasma chemical reactions. These insulating films have effective properties that phosphorous glass films do not have. For example, it is thermally stable, a thick film can be easily obtained, it has good adhesion to a conductive film, and it has excellent moisture resistance. Furthermore, since high-temperature treatment at around 1000°C is required, changes in circuit element characteristics due to re-diffusion in the impurity diffusion region are unavoidable, and metal films such as aluminum films cannot be used as the lower conductive film. occurs.

A similar problem also occurs at the stepped portion of the opening provided in the interlayer insulating film for electrical connection between the lower conductive film and the upper conductive film.

FIG. 1 is a sectional view of an example of a conventional semiconductor device. A first layer of metal wiring 13, 13' is selectively formed on the upper surface of a thermal oxide film 12 which covers a semiconductor substrate 11 including a plurality of circuit elements (not shown) and has selectively provided openings. The metal wiring 1 is formed in
3 and 13' and covering the other thermal oxide films 12, an interlayer insulating film 14 made of a vapor-grown oxide film is formed, and a first A second layer metal interconnect 16 is formed that is electrically connected to the second layer metal interconnect 13 and extends over the interlayer insulating film 14 .

In such a conventional semiconductor device structure, the stepped portion 17 of the opening 15 provided in the interlayer insulating film 14
are tapered, but because the stepped portions 18, 18', 18'' that occur between the tops of the first layer metal wiring 13, 13' and other areas are steep, This has the disadvantage that thin portions occur in the second layer metal wiring 16, which makes the second layer metal wiring 16 more likely to break, which hinders miniaturization.

An object of the present invention is to provide a multilayer interconnection in which the interlayer insulating film is not limited to phosphor glass, which allows the stepped portions of interconnection connections to be sloped without requiring high-temperature treatment, eliminates disconnection, and allows miniaturization. An object of the present invention is to provide a method for manufacturing a semiconductor device having a structure.

The method for manufacturing a semiconductor device of the present invention includes the steps of providing an opening in a first insulating film that covers a semiconductor substrate, and forming a hole that covers at least a portion of the opening and extends over the first insulating film. a step of selectively providing a first conductive film; a step of depositing a second insulating film covering the first conductive film and other regions; After the step of providing an opening that reaches the film and depositing a third insulating film that covers the opening and the rest of the second insulating film, at least the third insulating film is irradiated with a high-speed ion beam. The method includes a step of removing part or the third insulating film and at least a part of the second insulating film.

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 2a to 2e are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 2a, openings are selectively provided in the thermal oxide film 32 covering the semiconductor substrate 31 including a plurality of circuit elements (not shown in the figure), and at least one of the openings is The first layer of metal wiring 3 covering the
3, 33' are selectively formed, and then the first layer metal wiring 33, 33' and other thermal oxide films 32 are formed.
A nitride film 34 is formed by a first plasma chemical reaction to cover the surface of the substrate. If the first layer wiring is formed with a semiconductor thin film such as a polycrystalline silicon film instead of a metal film, at least some of the circuit elements in the semiconductor substrate may be contaminated with impurities after the semiconductor thin film is deposited. It is also possible to form by adding and pressing. Further, the optimal thickness of the nitride film formed by plasma chemical reaction is approximately 1.0 μm. Further, at this stage, the stepped portions 38, 38', 38'', and 38 in question are steep.

Next, as shown in FIG. 2b, an opening 35 is formed in the nitride film 34 formed by a plasma chemical reaction to reach the first layer metal wiring 33. Then, as shown in FIG.

Next, as shown in FIG.
form. The optimal thickness of the nitride film 39 formed by the plasma chemical reaction at this time is approximately 0.5 μm.

Next, as shown in FIG. 2d, a high-speed ion beam is applied to the entire surface to etch a portion of the thickness of the nitride film 39 that has been formed up to the previous step. This process removes the steep steps 38, 3 before etching.
8', 38'', 38 and the step portions 37, 37' of the openings provided in the nitride film become substantially flat surfaces with a gentle and constant inclination angle.The insulating film thus formed is denoted by 301. Insulating film 30
1 may consist of nitride films 34 and 39,
In some cases, the nitride film 39 is removed and only the nitride film 34 is formed. When the films 34 and 39 are both nitride films as in this embodiment, it becomes difficult to distinguish between them. This is because when a suitable material is etched with a high-speed ion beam, the etching rate changes depending on the angle relative to the direction of incidence of the ion beam.For normal insulating films, this angle is approximately 45
It takes advantage of the property that the etching speed is maximized in terms of depth. That is, when etching is performed by applying an ion beam perpendicularly to the surface of the semiconductor substrate, the steep steps on the semiconductor substrate are etched into a substantially flat surface having an inclination angle of about 45 degrees. Furthermore, if the direction of incidence of the ion beam is deviated from the direction perpendicular to the surface of the semiconductor substrate and it is applied obliquely, the angle of inclination of the stepped portion becomes smaller than 45 degrees and becomes even gentler. In this example, the ion beam is applied vertically,
A film thickness of approximately 0.5 μm is etched on the flat surface.
Therefore, after the etching is completed, the surface of the first layer metal wiring 33 is automatically exposed at the bottom of the previously provided opening.

Next, as shown in FIG. 2e, a second layer of metal wiring 36 is formed to cover the opening 35 and the interlayer insulating film 301 made of the nitride film produced by the plasma chemical reaction. As mentioned in Fig. 3d, the step 3
8, 38', 38'', 38 and openings 37, 3
Since the surface 7' is a flat surface having approximately the same gentle inclination angle, the problem of the second layer metal wiring does not occur.

In the description of the above embodiments, circuit elements within the semiconductor substrate have been omitted, but the present invention is applicable to bipolar transistors, field effect transistors,
Active elements such as PN junction diodes and metal-semiconductor diodes, passive elements such as resistors and capacitors, and combinations of these elements are all applicable. or,
Regarding the first, second and third insulating films, thermal oxide film, thermal nitride film, oxide film by vapor phase growth, nitride film,
Any insulating film including an alumina film, a phosphorus glass film, an oxide film formed by a plasma chemical reaction, a nitride film, or the like can be applied. Furthermore,
In addition to metal thin films, the first and second conductive films may be semiconductor thin films, metal-semiconductor alloy thin films, or conductive films containing these.

As explained above, according to the present invention, the interlayer insulating film is not limited to phosphorus glass, and the stepped portion of the wiring connection portion can be sloped without requiring high-temperature treatment, and the semiconductor device eliminates disconnection. can be manufactured.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an example of a conventional semiconductor device, and FIGS. 2 a to 2e are sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention. 11...Semiconductor substrate, 12...Thermal oxide film, 1
3, 13'...Metal wiring, 14...Interlayer insulating film,
15...Opening part, 16...Metal wiring, 17...Step part, 18, 18', 18''...Step part, 31...Semiconductor substrate, 32...Thermal oxide film, 33, 33'... Metal wiring, 34...Nitride film, 35...Opening part, 36
...Metal wiring, 37,37'...Step part, 38,3
8', 38'', 38... step part, 39... nitride film,
301...Insulating film.

Claims (1)

[Claims] 1. Providing an opening in a first insulating film covering a semiconductor substrate, and selectively providing a first conductive film covering at least a portion of the opening and extending over the first insulating film. a step of depositing a second insulating film covering the first conductive film and other areas;
A step of providing an opening in the second insulating film that reaches at least the first conductive film, and depositing a third insulating film that covers the opening and the rest of the second insulating film. A method for manufacturing a semiconductor device, comprising the step of removing at least a portion of the third insulating film or the third insulating film and at least a portion of the second insulating film using a high-speed ion beam.