JPS586149A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To form a layer insulating film without limiting its material to phosphorus glass and requiring treatment at a high temperature by forming both a boundary stepped section and a stepped section shaped by an opening section by flat surfaces with approximately equal predetermined angles of inclination. CONSTITUTION:Metallic wiring 23, 23' are formed to the upper surface of a thermal oxide film 22. A stepped layer insulated film 24 is shaped so as to coat the upper sections of the metallic wiring 23, 23' and another thermal oxide film 22. Metallic wiring 26 is molded onto the layer insulating film 24, and connected electrically to the metallic wiring 23 through the opening section 25 formed to the layer insulating film 24. In this case, the stepped sections 28, 28', 28'' of the surface of the layer insulating film 24 generated among the upper sections of the metallic wiring 23, 23' and the upper section of another thermal oxide film 22 and the stepped section 27 of the opening section 25 shaped to the layer insulating film 24 are formed by the approximately flat surfaces with the approximately predetermined angles of inclination.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and relates to an interlayer insulating film O! in a multilayer wiring structure. The present invention relates to a semiconductor device in which a stepped portion on one surface and a stepped portion around a large opening provided in a diagonal insulating film have approximately equal gentle inclination angles, and a method for manufacturing the same.

In recent years, semiconductor devices have become increasingly highly integrated and densely packed, and along with this, impurity diffusion region patterns, hole patterns in insulating films, conductive film patterns, etc. have been miniaturized, and a single conductive film is multilayered. It looks like this. However, in the prior art, miniaturization of the pattern O of the conductive film and multilayering of the conductive film are not compatible. In other words, in order to prevent disconnection of the upper conductive film at the 0-stage part of the lower conductive film in the conventional multilayer conductive film, the side surface of the lower conductive film is connected to the base of the lower conductive film. We have tried to prevent the steps from becoming steep by increasing the slope so that they are not vertical. However, since this method involves vertical patterning of the conductive film, it is not suitable for realizing miniaturization. A method conventionally used to prevent these defects by using a ring glass film is to use a ring glass film as an interlayer insulating film between the lower and upper conductive films, and after forming the ring glass film, toooc There is a method of smoothing the stepped portion by causing it to flow through high-temperature treatment in the vicinity. However, this method also has limitations in that it requires the use of a phosphor glass film and in that it must be treated at a high temperature of around 10,000 ℃, so its range of use is limited. That is, in addition to the phosphor glass film, interlayer insulating films include oxide films produced by vapor phase growth, aluminum films, and oxide films and nitride films produced by plasma chemical reactions.

In addition, these insulating films have effective characteristics that are not found in KFi phosphorus glass films. For example, it is thermally stable, allows a thick film to be obtained, has good adhesion to the conductive film, and has excellent moisture resistance. In addition, due to the need for high temperature treatment near KIJOOc), circuit element 041 due to re-diffusion of the impurity diffusion region
Changes in properties are unavoidable, and further problems arise, such as the inability to use a metal film such as an Arun film as the lower conductive film.

A similar problem occurs at the stepped portion of the opening in the ninth interlayer insulating film for electrical connection between the lower conductive film and the upper conductive film.

Figure 1 is a sectional view of an example of a conventional semiconductor device. A first layer of metal wiring 13.13' is selectively formed on the upper surface of a thermal oxide film 12 that covers a semiconductor substrate 11 including a plurality of circuit elements (not shown) and has nine openings. An interlayer insulating film 14 made of an oxide film grown in a vapor phase is formed on the metal wiring 13°1s'0 and covering the other thermal oxide films 12.
is formed, and a second layer extending over the first interlayer insulating film 14 is electrically connected to the first layer metal wiring 13 through an opening 15 selectively provided in the interlayer insulating film 14. Metal wiring 16 is formed.

In such a conventional semiconductor device structure, the step portion 17 of the hole portion 15 provided in the interlayer insulating film 14 is tapered, but the first layer metal film 4913.13'
Step III, 1B that occurs between the top of and other areas
Because '1B' is steep, a thin part occurs in the second layer metal wiring 16 formed on this, and the second layer metal wiring 16 is likely to be disconnected. The drawback is that it becomes a hindrance.

The present invention eliminates the above-mentioned drawbacks, provides a semiconductor device having a multilayer wiring structure in which the interlayer insulating film is not limited to phosphor glass, can be formed without requiring high-temperature treatment, and can be miniaturized, and a method for manufacturing the same. be.

The semiconductor device of the present invention includes: a semiconductor substrate including a plurality of circuit elements; a tenth insulating film covering the semiconductor substrate and having a plurality of selectively provided openings; a plurality of first conductive films electrically connected to and selectively provided extending over the tenth insulating film; and a twentieth insulating film covering the tenth conductive film and other regions; Decorative note selectively provided in the second insulating film, electrically connected to at least the first conductive film through the opening, and selectively extending over the second insulating film. In a semiconductor device having a plurality of second conductive films, at least four portions of the surface of the second insulating film at a boundary step extending from the top of the first conductive film to other regions and the second insulating film. -kl
I! At least a part of the step formed by the hole is Kf
It is characterized by being composed of one flat surface having a constant angle of inclination that is equal to the angle of inclination.

The method for manufacturing a semiconductor device of the present invention includes the steps of providing an opening in a first insulating film that covers a semiconductor substrate, and a first insulating film that covers at least a portion of the first insulating film and is located on a tenth insulating film. a step of selectively providing a conductive film; a step of depositing a twentieth insulating film covering the first conductive film and other regions;
A 30th insulating film was deposited on the second insulating film to cover at least the openings reaching the first conductive film and covering the remaining openings and the rest of the second insulating film. After that, the method includes a step of removing at least part of the third insulating film or III of the third insulating film and at least the second insulating film using a high-speed ion beam.

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a sectional view of an embodiment of the O semiconductor device of the present invention. A first layer of metal wiring 23, 23' is formed on the upper surface of a thermal oxide film 22D having selectively provided openings covering the semiconductor substrate 21 including a plurality of @-path elements (not shown). A nine-layer insulating film 24 made of a nitride film formed by a plasma chemical reaction is selectively formed on the first layer metal wirings 23, 23' and covering the other thermal oxide films 22. A second layer O metal wiring 26 is selectively provided in the interlayer insulating film 24 and is electrically connected to the first layer metal wiring 23 through the opening 25 and extends over the interlayer insulating film 24. is formed. In Jin's embodiment, the first layer of metal film l
A stepped portion 28°28', 2 on the surface of the glabella insulating film 240 that occurs between the tops of I23 and 23' and the other tops of the thermal oxide film 22.
g and the stepped portion 2 of the 91 hole portion 25 provided in the interlayer insulating film 24.
The film thickness of the second layer metal wiring 26 formed on ζ0 is approximately the same at either the stepped portion or the flat portion. The abrasive stone can also be formed uniformly.

A structure suitable for miniaturization has been realized.

FIGS. 3(51) to 3(C) are cross-sectional views at the ninth main manufacturing process for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 3(a)K, a plurality of one-way elements (
Thermal oxide film 3 covering the semiconductor substrate 31 including (omitted in the figure)
Apertures are selectively provided in 2, and at least one first layer metal wiring 33°33' is selectively formed to cover the aperture, and then the first layer @0 metal wiring 33, A nitride film 34 is formed by a first plasma chemical reaction to cover the surface of the thermal oxide film 33' and other thermal oxide films 320. If the first layer wiring is formed not with a metal film but with a semiconductor thin film such as a polycrystalline silicon film, at least a part of the Oll path elements in the semiconductor substrate may be formed after the semiconductor thin film is deposited. It is also possible to form by adding impurities and pressing them. Further, the optimal thickness of the nitride film formed by plasma chemical reaction is approximately 1.0 mm.

Also, at the ζO stage, the problem step portions 38°3B', 38'
, 3B' is steep.

Next, as shown in FIG.
A nitride film 39 is formed by a Gutsuma chemical reaction. Due to the plasma chemical reaction at this time, the film thickness of the nitride film 39 is approximately 0.5
An ugly voice is best.

Next, as shown in FIG. 3-), a high-speed ion beam is applied to one surface of the metal body to etch part of the thickness of the nitride film 390 that has been formed up to the pre-etched surface. Due to ζ0 treatment, a steep 5-sided stepped portion 311.38' was created before ψ-etching.

3m', 3@'' and stepped portion 3 of the opening provided in the nitride film
7, 37' becomes a bald flat surface with a gentle and constant inclination angle. The insulating film thus formed has a thickness 301. The insulating film 301 may consist of nitride films 34 and 39, or the nitride film 39 may be removed and the nitride film 3
In some cases, it consists of 40 pieces.

When the films 34 and 39 are both nitride films as in this embodiment, it becomes difficult to distinguish between them. This is because when etching a suitable material with a high-speed ion beam, the etching rate changes depending on the angle with respect to the direction of incidence of the ion beam.For normal conjunctival membranes, this angle is about 4 seconds. This is done by taking advantage of the property that the etching speed is maximized with Ii.

In other words, when etching is performed by emitting an ion beam perpendicular to the surface of the semiconductor substrate, the steep steps on the semiconductor substrate are approximately 45 mm deep.
A plate having an inclination angle of 100 degrees will be etched on one surface of the buried plane. Furthermore, if the incident direction of the ion beam O is removed from the perpendicular direction to the semiconductor substrate surface and is applied obliquely,
The inclination angle of the stepped part is 481) smaller, and even more gradual I
Ill. In this embodiment, the ion beam is applied vertically to etch a film with a thickness of about 0.S .mu.m on the flat surface. Therefore engineering! After the drilling is finished, the bottom of the previously prepared hole 1 is automatically removed.
At fK, the surface of the first layer metal wiring 330 is exposed.

Next, as shown in FIG.
, 38', 311', 38'' and aperture 37.3
7' is #! If the surface is rounded to a flat surface with an equal gentle slope, problems with the second layer metal wiring will not occur.

In the description of the above embodiments, circuit elements within the semiconductor substrate have been omitted, but the present invention is applicable to bipolar transistors, field effect transistors, PN junctions, diodes,
Active elements such as metal-semiconductor diodes, passive elements such as resistors and capacitors, and combinations of these elements are all applicable. Also, the first, second. In the 30th insulating film, thermal oxide film, thermal nitride film, oxide film by vapor phase growth, nitride film, Al2 film, phosphorus glass film, oxide film by plasma chemical reaction, nitride film, etc. Furthermore, any insulating film containing fins can be applied. Furthermore, as for the first and second conductive films, in addition to metal thin films, semiconductor thin films, metal-semiconductor alloy thin films, and conductive films containing these can be applied.

As described in detail above, according to the present invention, a semiconductor device having a multilayer interconnection structure that can be miniaturized can be obtained, so the effects are significant.

[Brief explanation of drawings]

Fig. 2 is a diagram of a conventional semiconductor device O-OFr11ml, Fig. 2 is an owrrra diagram of an embodiment of the semiconductor device of the present invention,
FIGS. 3(a) to 3(@) are OWR views showing the main X&manufacturing process for explaining one embodiment of the method for repairing a semiconductor device of the present invention. 11... Semiconductor substrate, l... Thermal oxide film,
13゜13'...Metal wiring, 14...
Interlayer insulating film, 15...Opening part, 16...
・Metal wiring, 11...Stepped part, 18°18', 1
8...Step part, 21...Semiconductor f11
[, Snow 2, ... thermal oxide film, 23.23'...
...Metal wiring, 24...Interlayer insulating film, 25...
...Opening part, 26...Metal wiring, 27...
・・・・・・Double part, zs, zs', ts ・・・・・・l
Part 1. 31...Semiconductor substrate, 3t...Thermal oxidation @,
SS. 33'...Metal wiring, 34...Nitride film, 3B...One hole, 36...Metal wiring, 37.17'...・Stepped part, 38.38', 38
', 38''...Step part, 3s...Nitrogen film, 301...Insulating film. Figure 2

Claims (1)

[Scope of Claims] (11) A semiconductor substrate including several O circuit elements; a tenth insulating film covering the semiconductor substrate and having a plurality of selectively provided OII holes; a first conductive film electrically connected to the semiconductor substrate through the conductive film and selectively provided extending over the tenth insulating film;
a second insulating film covering the conductive film and other regions; 2
Several large pots are extended over the insulating film and selectively coated.
In a semiconductor device having a 0 conductive film, the 20th insulating film O1! is located at the boundary step extending from the conductive film in the first region to the other regions.
At least a portion of the surface and at least a portion of the step formed by the opening provided in the second insulating film are both uneven.
A semiconductor device comprising a flat surface having a constant angle of inclination. (2) providing an opening in a tenth insulating film covering the semiconductor substrate;
selectively providing a tenth conductive film extending over the insulating film; depositing a twentieth insulating film covering the tenth conductive film and other areas; After forming an opening that reaches the tenth conductive film and depositing a third soe film covering the opening and the rest of the second insulating film, a high-speed ion beam is applied to at least the third
1. A method for manufacturing a semiconductor device, comprising a step 1 of removing a part of the insulating film or a 30th insulating film, and a step 1 of removing at least a part of the insulating film of the tuna 2.