JPH05143751A - Interface circuit for ic - Google Patents

Abstract

PURPOSE:To miniaturize a package by bisecting the switch of plural bits, connecting resistance networks to the respective divided switches, collecting them into two lines and limiting the number of pins in an IC to two pins. CONSTITUTION:In an interface circuit for address setting, a switch 11 of four bits sets the 16 kinds of addresses. Resistance networks 12a and 12b constitute an external circuit together with the switch 11 and corresponding to the switching state of the switch, the four kinds of voltages are respectively generated in input lines 13 and 14 and inputted to pins A and B of the IC. On the other hand, a reference potential is applied from a constant voltage output circuit 1 7 respectively to the comparators of two-bit output circuits 16a and 16b in a digital demodulator 15, and a potential set by switching the switch 11 is impressed through the pins A and B to the side of a comparative input and converted to two-bit logic same as the switching state of the switch 11 by a logic circuit. This output is inputted to an address coincidence detection circuit 18, and logical coincidence is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small IC interface circuit, and more particularly to a technique for designating a plurality of bits for address setting with a small number of pins used.

[0002]

2. Description of the Related Art In order to reduce the size of an IC package, how to reduce the number of pins used is an important issue. By the way, the inventor has disclosed a multi-connection sensor for connecting a plurality of photoelectric sensors and the like in parallel and collectively controlling them (JP-A-3-71716).
The overall configuration is as shown in FIG. Here, a state is shown in which 16 sensors 1a to 1p are connected in parallel, and address switches S0 to S15 having addresses 0 to 15 are provided in order. This address switch is composed of a 4-bit dip switch and an address counter. Reference numeral 2 denotes a demodulator for driving the sensor groups 1a to 1p, and 3 is a drive circuit for supplying electric power to the sensor groups 1a to 1p, and 4 is a drive circuit 3 for generating power supply pulses. , And a control circuit for outputting 16 detection signals to the next stage computer or the like.
CMP1 and CMP2 are comparators, respectively, which set threshold values for the signal levels sequentially output from the sensors 1a to 1p. 5 and 6 are a pair of power supply lines,
Although 5 is on the positive side and 6 is on the negative side, the power line 5 on the positive side and the output lines of the sensors 1a to 1p are made common here.

[0003]

As described above, when connecting a plurality of sensors, it is necessary to set an address for specifying each sensor. In addition, the sensor I
If C is used and 16 types of addresses are set with 4 bits as in the conventional example, four pins are required. However, when 4 pins are allocated for address setting, about 10 pins are required in addition to the power supply pin and the signal output pin, and the package becomes large accordingly, which hinders the miniaturization of the IC. There is a problem to do.

The present invention focuses on these problems.
While maintaining the function of setting 16 addresses, a 4-bit switch is integrated into two lines,
It is an object of the present invention to provide an interface circuit that can reduce the size of a package by using two pins.

[0005]

In order to achieve the above-mentioned object, the interface circuit of the present invention divides an N-digit switch into two and connects a resistor network to each of them.
It has an external circuit that draws one line from each of these resistance networks to generate a plurality of potentials corresponding to the open / closed state of the switch. Further, it has an internal circuit including two sets of a plurality of comparators having reference potentials corresponding to the plurality of potentials, and a digital demodulator for logically processing the outputs of these comparators and performing a binary output,
A means of applying a potential to each of two sets of a plurality of comparators from two lines and performing a binary output in accordance with the open / closed state of the switch from the digital demodulator was used.

[0006]

The N-digit switch has a function of setting the address of the IC. The resistance network converts the open / closed state of the switch into a voltage value, and this external circuit performs a D / A conversion function of converting an N-bit digital value into two kinds of analog values. This has the effect of reducing the number of IC pins. Further, a reference potential corresponding to the potential generated by the resistance network is given to the comparator in advance, and an A / D conversion function of converting the value given in analog into digital by logically processing the reference potential is performed. .. Through such an action, the digital demodulator outputs a signal that matches the open / closed state of the switch.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 2 is a specific example of an interface circuit for setting an address, 11 is a 4-bit switch,
It is for setting 16 types of addresses. 12
Reference numerals a.12b are resistance networks having the same value, each of which is connected to a 2-bit switch from the switch 1, and generates four kinds of voltages on the input lines 13 and 14 by a combination of 2-bit switches. A
B is a pin of the IC, to which the input lines 13 and 14 are connected. The switch 11 and the resistor network 12a.1
2b constitutes an external circuit of the interface circuit of the present invention. In addition, these circuits perform the function of converting a 4-bit digital signal into two types of analog signals,
The number of lines is being reduced.

Next, of the interface circuits, pin A
-The internal circuit of the IC connected to B will be described. 1
5 is 4 kinds of 2 types of analog signals input to pins A and B
This is a digital demodulator for demodulating into a bit digital signal, and a 2-bit output circuit 16a for outputting a 2-bit signal by internally arranging three comparators in parallel and forming a logic circuit by these outputs.・ 16
b, a constant voltage output circuit 17 for applying three reference potentials to the three comparators of the 2-bit output circuits 16a and 16b, respectively. 18 are 16 kinds of outputs which are total outputs from two 2-bit output circuits,
This is an address coincidence detection circuit for comparing 4-bit inputs from a main counter (not shown) inside the IC and performing coincidence output when these coincide.

Next, the operation of the interface circuit of the present invention will be described with reference to the resistance value and voltage value shown in FIG. The resistor network 12a is composed of resistors having three different values, and a constant voltage of 3.9V is applied. Here, the resistance network 12 of the switch 11
Four types of voltages are generated in the line 13 depending on the open / closed states of the two switches corresponding to a. That is, when the switch is open, 3.9V is generated, and when the first switch is closed, 2.3 is present on the line 13 which is the midpoint thereof.
A partial voltage of 4V is produced. Further, if only the second switch is closed, a partial pressure of 1.75V is generated, and if both are closed, a partial pressure of 1.35V is generated. Therefore, a potential corresponding to the four open / closed states of the two switches is generated in the line 13, and the pin A
Entered in. The same applies to the resistance network 12b side. Next, the three comparators of the 2-bit output circuit 16a have constant voltage output circuits 17 to 1.55V, respectively.
The reference potential of 2.05V and 3.12V is given,
The potential set by opening and closing the switch 11 is applied to the comparison input side via the pin A. Since there are four types of output relations of the three comparators, these are converted into the same 2-bit logic as the open / closed state of the switch 11 by the logic circuit. The operation on the side of the 2-bit output circuit 16b is similar to this. In this way, the total 4-bit output from the two 2-bit output circuits 16a and 16b is input to the address coincidence detection circuit and compared with the 4-bit signal from the main counter, which is an internal circuit of the IC, and when the logic coincides. The output is matched only to. As a result, the detection operation of the sensor can be performed only when the set address and the main counter match.

It should be noted that the resistance value and the voltage value are merely examples, and it is needless to say that the resistance value and the voltage value can be arbitrarily set within the range where there is no restriction in the circuit design, and the resistance values in the resistance network are completely paired. Of course, there is no need to do it. However, in this case, the constant voltage output circuits must be separately provided or the potentials must be separately provided corresponding to respective resistance values. Further, although the reference potential of the comparator is applied to the positive side input terminal, the basic idea is the same even if input to the negative side. Further, in the present embodiment, a 4-bit signal is converted into a 2-input analog signal, and this is converted into the original 4
Although it is demodulated into a bit signal, a 6-bit signal may be pin-input as a 2-input analog signal depending on the configuration of the resistor network.

[0011]

In the interface circuit of the present invention, an N-bit binary signal is divided into two and converted into two kinds of analog signals by a resistance network and input to the internal circuit of the IC. Since demodulation is performed, only two IC pins are sufficient regardless of the number of address bits. Therefore, it is possible to achieve reduction of pins, which is an important subject for downsizing of ICs, and it is very effective means especially in a photoelectric sensor circuit of a mode to be incorporated in a device and a multiple connection sensor shown as a conventional example. Can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a multi-connection sensor using a circuit of the present invention,

FIG. 2 is a circuit diagram showing an interface circuit of the present invention.

[Explanation of symbols]

 11 Switch 12a ・ 12b Resistor network 13 ・ 14 Line 15 Digital demodulator A ・ B pin

Claims (1)

[Claims] 1. An N-digit switch is divided into two, a resistance network is connected to each, and one line is drawn from each of these resistance networks to generate a plurality of potentials corresponding to the open / closed state of the switch. In addition to having an external circuit, it has an internal circuit including two sets of a plurality of comparators having reference potentials corresponding to the plurality of potentials, and a digital demodulator that logically processes the outputs of these comparators and outputs a binary value. Then, an interface circuit of the IC is characterized in that a potential is applied to each of the two sets of the plurality of comparators from the line and binary output is performed from the digital demodulator in accordance with an open / closed state of the switch.