JPH0279010A - Reader for tri-state digital encoder - Google Patents

Abstract

PURPOSE:To read an encoded value directly with simple circuit constitution by providing an encoder means and a detecting means which detects the encoded value according to the output of the encoder means at respective logic levels. CONSTITUTION:Data supplied to input terminals (a) and (b) of the tri-state digital encoder K have invariably opposite logical levels through the operation of an inverter A. Output terminals 1 - (n) of the encoder K, on the other hand, are pulled up, so they enter an 'H' state in an 'open state' regardless of the input data. In other states, the logic levels of the input terminals of the connected encoder K are outputted as they are and supplied to and stored in an interface circuit IF. Consequently, the output-side level of the encoder K which is stored can be read and processed by a central arithmetic unit CPU when necessary. Consequently, the output of the encoder K is readable without requiring any special circuit element.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a reading device for a 3-state digital encoder, and in particular, to a reading device for a 3-state digital encoder, which dynamically moves within a certain distance range such as the zoom lens of a still camera, and reads current position information. This relates to a device that reads output data of an encoder that outputs (focal length information in the case of a zoom lens).

(Prior Art) The case of reading the output of a conventionally used encoder is shown in FIGS. 5 and 6. In order to make the explanation clear, a 2-bit encoder will be explained below as an example.

First, as shown in FIG.
Connect to each. Also, output terminal 1 to the encoder
．． 2 has four resistors R1, R2, R3 and R of different values.
Connect 4 respectively. The next stage analog /
The input side of the digital converter (hereinafter referred to as A/D converter) B is supplied with one of nine voltage levels obtained by dividing the reference voltage V ear by a combination of four resistors. Become. Therefore, this voltage value going up the A/D conversion converter is digitized to obtain an encoded value.

In addition, in the example shown in Fig. 6, output terminal 1 of the encoder
．． 2 into four equal value resistors R1, R2゜R3 and R4
By pulling up and down at , in the "open state" of the output terminal 12, v , , rx 1 /2
,■ in the "H" state. 1. In “L” state, GND 3
voltage levels are obtained and each of these voltage levels is input into a window comparator, thus resolving the original two voltage levels.
The bit signal is converted into a double 4-bit digital value to detect the encoded value.

(Problems to be Solved by the Invention) According to the two conventional encoder output reading means described above, not only do the circuit configurations for reading become complicated, but also the reference voltage of an accurate value and the A resistor with a certain value is required, and there are many restrictions due to the multiplication of the number of bits.

In view of the above problems, the present invention provides a reading device for a 3-state digital encoder that can easily read the output of the encoder with an extremely simple circuit configuration that does not require special elements and without increasing the number of bits. The purpose is to

(Means and operations for solving the problem) The reading device of the 3-state digital encoder of the present invention has a logic level "HZ".
11 L II and "open state" encoder means for expressing 3n patterns by combining three digital values (n bits), and two logic levels for two input terminals of this encoder. and detection means for detecting an encoded value based on the output of the encoder means at each given logic level.

According to the present invention, first, in order to eliminate the need for circuit elements such as an A/D converter and a window comparator for reading the encoder output, these circuit elements are removed. In order to include the "open state" in either the "H" or "L" state on the logic level, a resistor is used to pull it up. However, with this circuit configuration, the pattern that can be read from the output of the n-bit digital encoder is There are only 2'' patterns, and not all of the 3'' patterns formed by the 3-state encoder can be read.

Therefore, we focused on the input terminal of the encoder, which conventionally gave a unique voltage level, and gave it two contradictory logic level inputs "H" or "L" and "L" or "H".This idea As is clear from FIG. 1, the data applied to input terminals a and b of the 3-state digital encoder are always at opposite logic levels due to the action of inverter A.On the other hand,
Output terminals 1, 2, 3, ..., n to the encoder are each pulled up, so in the "open state" they are in the "H" state regardless of the input data, and in cases other than the "open state" outputs the logic level of the input terminal of the connected encoder as it is and supplies it to the interface circuit IF so that it can be stored. The thus stored logic level on the output side of the encoder can be recalled and processed by the central processing unit CPU as required.

Because of this, it is difficult to determine which conductor pattern the output terminals 1 and 2 of the 3-state digital encoder are connected to.
Alternatively, it is possible to determine whether it is in the "open state" by a combination of the logic levels of MHn or "L".

(Embodiment 1) Hereinafter, an apparatus for reading the output from a 2-bit 3-state digital encoder of the present invention will be described based on an embodiment with reference to FIG. The input terminals of the encoder sliding on the two conductor patterns (a) and (b) are a and b, and the output terminal is 1.
．． Set it to 2. Output terminal 1.2 to encoder is resistor R1
, R2, so it always outputs a logic level "H" in an open state. On the other hand, when the output terminals 1.2 of the encoder are electrically connected to the conductor pattern (a), the logic levels input to the input terminals a and b are output as they are.

As is clear from the above, according to the present invention, logic level "H" is applied to input terminals a and b of the encoder.
The combination of two sets of 2-bit output data obtained when inputting "L" and "L" has a unique value corresponding to the encoded value from 1 to 9. Therefore, there is no need for special circuit elements for reading encoded values (and no need to increase the number of input/output bits).

(Embodiment 2) FIG. 3 shows an embodiment in the case of an 8-bit digital encoder. In this example, each pit output terminal 1 of the encoder
By simply connecting pull-up resistors R1 to R8 to 8, respectively, two sets of 8-bibt data can be read in the same manner as described above, and thereby an encoded value can be obtained.

(Embodiment 3) Also, the output terminals 1 and 2 of the encoder can be pulled down as in the embodiment shown in FIG.
The embodiment is the same as the embodiment shown in FIG. 2, except that the "open state" becomes the logic level "L".

(Effects of the Invention) As described above, the reading device for a 3-state digital encoder according to the present invention does not require special elements (it directly reads encoded values with a minimum number of bits using an extremely simple circuit configuration). It has the important practical advantage of being able to

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a reading device for a 3-state digital encoder of the present invention, Fig. 2 is a block diagram showing an embodiment of a reading device for a 3-state digital encoder of the present invention, and Fig. 3 similarly shows another example. FIG. 4 is a block diagram showing a modified example of a reading device for a three-state digital encoder according to the present invention, and FIGS. 5 and 6 are explanatory diagrams showing a reading device for a conventional encoder. K... 3-state encoder A... Inverter IF... Interface circuit cpu...
・Central processing units a, b... Input terminals (K) 1, ~n...
- Output terminal (K) R1-Rn...Resistance/resistance patent applicant Olympus Optical Industry Co., Ltd. Figure 1 K...3-state encoder A...Inverter 1F...Interface circuit CPLJ...Central processing Devices a, b...input terminals (K) Fig. 3 Fig. 4 Fig. 5 Fig. 6 ref2

Claims (1)

[Claims] 1. Encoder means for expressing 3^n patterns by combining three digital values of logic levels "H", "L" and "open state" with a plurality of bits (n bits); 1. A reading device for a three-state digital encoder, comprising: detecting means for applying two logic levels to one input terminal and detecting an encoded value based on the output of the encoder means at each logic level.