JPH05143363A - Interruption processing system - Google Patents

Abstract

PURPOSE:To remove restriction to an instruction to be set to a delay slot and to effectively utilize the delay slot by attaining interruption from a delay slot for a branch instruction. CONSTITUTION:A branch address 15 formed by the D stage of a branch instruction is transferred to a memory control device 11, temporarily stored in a register 23, selected by a selector 25, and then stored in a register 26 indicating the instruction location of the D stage. When no branch an interruption occurrs, the succeeding instruction location is stored in the same register 26. The contents of the register 26 are successively shifted to an E stage register 27 and a W stage register 28 synchronously with instructions. When an interruption is generated and an interruption signal 19 is turned to true, the contents of the registers 27, 28 are respectively stored in registers 29, 30. In the case of restoring from interruption processing, a branch instruction to an address specified by the register 30 is executed and a branch instruction to an address specified by the register 29 is executed by the delay slot of the branch instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method in a pipeline type computer for processing a branch instruction having a delay slot.

[0002]

2. Description of the Related Art In a pipeline type computer, when a branch instruction is pipeline processed, a subsequent instruction is taken into the pipeline before execution of the branch unless the branch is performed at the first stage of the pipeline. , Hazard occurs in the pipeline.

As a method of reducing this pipeline hazard, a branch instruction is followed by an instruction field called a delay slot, and the instruction placed in this delay slot is executed regardless of whether or not there is a branch by the preceding branch instruction. It has been known. In this way, only instructions that may be executed independent of the branch will be placed in the delay slot. Therefore, if there is no instruction unrelated to the branch, a NOP (no operation) instruction is designated.

In the above example of the delay slot of the branch instruction, the pipeline has an instruction fetch stage (F stage).
And the stage of instruction decoding and branch processing (D stage)
And a four-stage configuration including an arithmetic stage (E stage) and a write back (write result) stage (W stage),
FIG. 4 shows a case where the delay slot has one stage (because branch processing is performed in the second D stage).

As shown in FIG. 4, a branch instruction (B) is conventionally used.
Interrupt is prohibited between the delay slot (S) and the delay slot (S). Further, unlike the example of FIG. 4, when the delay slot has a plurality of stages, it is prohibited to enter an interrupt between the delay slots. This is because the branch destination address of the preceding branch instruction is lost due to the occurrence of the interrupt from the delay slot, and the branch destination instruction cannot be executed when returning to the delay slot.

Therefore, conventionally, an instruction that may generate an interrupt, such as a load instruction or a store instruction, is not placed in a delay slot, and a branch instruction and a delay slot are not placed across a virtual address page boundary. Furthermore, processing such as not inserting an asynchronous interrupt between the branch instruction and the delay slot was performed. It should be noted that the load instruction, the store instruction, and the like may cause an interrupt because there is a possibility of causing an address conversion interrupt in the operand address generation.

[0007]

As described above, conventionally, when the branch destination address of the preceding branch instruction is lost due to the occurrence of an interrupt from the delay slot, and the branch destination instruction is returned to the delay slot, the branch destination instruction can be executed. Therefore, in order to prevent this, it was not possible to place an instruction such as a load / store instruction that could cause an interrupt in the delay slot of the branch instruction. Therefore, there is a problem that the instructions that can be placed in the delay slot are limited and the delay slot cannot be effectively used. Further, for the same reason, since the delay slot cannot be placed at the page boundary of the virtual address, there is a problem that performance is deteriorated when branch instructions are frequently used near the page boundary.

The present invention has been made in view of the above circumstances, and an object thereof is to enable an interrupt from within a delay slot and an interrupt return to the delay slot in a branch instruction having a delay slot, thereby providing a delay slot. The purpose of the present invention is to provide an interrupt processing method that can process instructions at high speed by eliminating the restriction of instructions that can be placed in the CPU, effectively utilizing delay slots.

[0009]

According to the present invention, there is provided first address holding means for holding an address of a return destination from an interrupt processing, and an address of an instruction to be executed subsequently to an instruction of a return destination from the interrupt processing. When returning from the interrupt processing, it branches to the return destination address held in the first address holding means, executes the instruction of the return destination, and then returns to the second address holding means. It is characterized by branching to the instruction address held in the address holding means.

[0010]

In the above arrangement, the address of the return destination from the interrupt processing is stored in the first holding means and the address of the instruction to be executed next to the instruction of the return destination is stored in the second holding means before the interrupt processing is started. Are held by the respective holding means. Then, when returning from the interrupt processing, first branch to the instruction of the return destination address held in the first address holding means, execute the instruction of the return destination, and then hold in the second address holding means. The instruction branches to the instruction having the specified instruction address, that is, the instruction to be executed next to the instruction at the return destination. As a result, if the return destination from the interrupt is the delay slot of the branch instruction, it is possible to branch to the branch destination of the preceding branch instruction after executing the instruction in the delay slot.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of essential parts showing an embodiment of a pipeline type computer to which the present invention is applied. In this embodiment, the pipeline has a four-stage configuration including an F stage, a D stage, an E stage, and a W stage, and branch processing is performed in the D stage. Further, the number of stages of the delay slot is one because the D stage performs branch processing.

In FIG. 1, 10 is a memory for storing various programs, data, etc., and 11 is a memory control device for controlling access to the memory 10. Unless there is a branch request or an interrupt request, the memory control device 11 sequentially fetches instructions from the memory 10 while incrementing the memory address, and the instruction decoding device 12
Supply to. Further, when there is a branch request or an interrupt request, the memory control device 11 starts fetching an instruction from the memory address indicated by the branch address or the interrupt address.

Reference numeral 12 is an instruction decoding device which controls the decoding of the instruction supplied from the memory control device 11, and 13 is a branch address generation device. This branch address generator 13
Generates and outputs a branch signal 14 and a branch address 15 which are true when a branch is taken, from the branch instruction decoded by the instruction decoding device 12. The branch address generator 13 also generates a control signal 16 which becomes true one cycle later than the branch signal 14. The control signal 16 indicates that the instruction currently in the D stage is the instruction in the delay slot (the instruction next to the branch instruction), and controls the fetching of the branch destination address into the location register 26 of the D stage described later. Used to do.

Reference numeral 17 is an interrupt detection device for detecting the occurrence of an interrupt. The interrupt detection device 17 generates an interrupt address 18 and an interrupt signal 19 when detecting an interrupt.
The interrupt detection device 17 also generates a control signal 20 which is one cycle delayed from the interrupt signal 19. This control signal 2
Like the control signal 16 described above, 0 is used to control fetching of a branch destination address (interrupt address) into the location register 26 of the D stage.

An OR circuit 21 ORs the branch signal 14 from the branch address generator 13 and the interrupt signal 19 from the branch address generator 13 and outputs the OR signal as a branch request to the memory controller 11. , 22 are selectors. The selector 22 includes the branch address 15 from the branch address generator 13 or the interrupt detector 17
One of the interrupt addresses 18 from 1 to 3 is selected according to the interrupt signal 19 and is output to the memory control device 11 as a branch destination address.

Reference numeral 23 is an address register (B-ADRS) for holding the branch destination address selectively output to the memory control device 11 by the selector 22, and 24 is a control signal 16 from the branch address generation device 13 and an interrupt detection device 17. An OR circuit for ORing with the control signal 20 from, and 25 is a selector. The selector 25 sets either the next instruction location obtained by incrementing the current instruction location indicated by the location register 26 described later or the output (branch destination address) of the address register 23 to O.
It is selected according to the output signal of the R circuit 24.

26 is a location register (D-LOC) for holding the output of the selector 25 as an instruction location of the D stage, 27 is the location register 2
A location register (E-LOC) for holding the output of 6 as the instruction location of the E stage, and a location register (W-LOC) for holding the output of the location register 27 as the instruction location of the W stage.

Reference numeral 29 is an address register (NXT-ADRS) for holding the output of the location register 27 as the address of the instruction to be executed next to the return destination instruction from the interrupt processing in response to the interrupt signal 19, and 30 is the location register 28. Is an address register (RTN-ADRS) for holding the output of as a return address from the interrupt processing in response to the interrupt signal 19.

Next, the operation of the configuration of FIG. 1 will be described with reference to the timing chart of FIG. 2 by taking the case where an interrupt occurs in the delay slot of a branch instruction as an example. The timing chart of FIG. 2 shows the movement of the pipeline when an address translation interrupt occurs in the generation of the operand address of the load instruction L executed in the delay slot of the branch instruction B. In the figure, N1 is a branch destination instruction specified by the branch instruction B, N2 and N3 are instructions subsequent to the branch destination instruction N1, I1,
I2, I3, ... Are instructions for interrupt processing generated by the load instruction L. In this embodiment, it is assumed that the operand address is generated in the D stage, the address conversion interrupt is detected in the E stage (interrupt determination by the interrupt detection device 17), and the interrupt processing is performed in the W stage.

When there is no instruction branch or interrupt, the memory controller 11 fetches an instruction from the memory 10 while incrementing the memory address, and the instruction decoder 12
Supply to. As a result, as in the example of FIG. 2, the branch instruction B is first fetched, then the load instruction L placed in the delay slot of the branch instruction B is sequentially fetched from the memory 10 (F stage of cycles T1, T2), and the instruction is executed. It is assumed that the data has been supplied to the decoding device 12.

The instruction decoding device 12 decodes the instruction supplied from the memory control device 11. As a result, in the case of the branch instruction B, the branch address generation device 1
In 3, a branch taken / not taken is determined, and when the branch is taken, a valid branch signal 14 and a branch address 15 indicating the storage destination of the branch destination instruction N1 are generated and output by the branch address generator 13 (D in cycle T2). stage). In the next cycle (T3), the control signal 16 which is a signal obtained by sending the branch signal 14 for one cycle is output from the branch address generation device 13.

The branch address 15 generated by the branch address generator 13 is supplied to the 0 side input of the selector 22. Unless the interrupt signal 19 from the interrupt detection device 17 is true, the selector 22 selects the branch address 15 which is the 0 side input and outputs it to the memory control device 11 as the branch destination address. At this time, the output of the OR circuit 21 is the valid branch signal 1 from the branch address generator 13.
4 becomes true, and a branch request is made to the memory controller 11.

As a result, the memory controller 11 fetches the branch destination instruction N1 designated by the branch address 15 generated at the D stage (cycle T2) of the branch instruction B from the memory 10 (F stage of cycle T3), and outputs the instruction. It is supplied to the decoding device 12.

When the load instruction L in the delay slot (of the branch instruction B) is fetched from the memory 10 in the cycle T2, the operand address is generated in the next cycle T3 (D stage). Then, in the next cycle T4 (E stage), the address detection interrupt is detected by the interrupt detection device 17.

If an address translation interrupt occurs and the fact is detected in the cycle T4 (E stage), the interrupt processing is started from the next cycle T5 (W stage) and the same cycle T5 (W stage). In the stage), the interrupt detection device 17 generates and outputs the valid interrupt signal 19 and the interrupt address 18 indicating the storage destination of the first instruction I1 of the interrupt processing. In the next cycle (T6),
A control signal 20 which is a signal obtained by sending the interrupt signal 19 for one cycle is output from the branch address generation device 13.

The interrupt address 18 generated by the interrupt detector 17 is supplied to the 1-side input of the selector 22. When the interrupt detection device 17 detects the occurrence of an interrupt, the selector 22 selects the interrupt address 18 which is one input to the selector 22 according to the valid interrupt signal 19 from the interrupt detection device 17 and sets it as a branch destination address. Output to the memory control device 11. At this time, the output of the OR circuit 21 is the valid interrupt signal 1 from the interrupt detection device 17.
It becomes true by 9 and a branch request is input to the memory control device 11.

As a result, the memory controller 11 sends the interrupt processing instruction sequence I1, I2, I3, ... Starting from the interrupt processing instruction I1 designated by the interrupt address 18 generated at the W stage (cycle T5) of the load instruction L to the next After the cycle T6, the data is sequentially fetched from the memory 10 and supplied to the instruction decoding device 12. As a result, interrupt processing is started.

In the present embodiment, the location is controlled as described below in order to know the location of the instruction that generated the interrupt. Further, since the branch address is determined in the D stage as described above, the location control is also performed in this D stage.

First, the branch destination address (branch address or interrupt address) selected by the selector 22 is held in the address register (B-ADRS) 23, and is delayed by one cycle from the cycle passed to the memory controller 11 by the branch request. It The branch destination address held in the address register 23 is supplied to the 1-side input of the selector 25. At the 0 side input of the selector 25, the next instruction location obtained by incrementing the instruction location of the current D stage indicated by the location register (D-LOC) 26 (for example, if the current D stage is the branch instruction B, , The location of the load instruction L within the delay slot of instruction B) is supplied.

The selector 25 performs a selection operation according to the output of the OR circuit 24. If the output of the OR circuit 24 is false, the 0 side (next instruction location) is selected. If the output is true, the 1 side (branch destination address) is selected. Select. The output of the OR circuit 24 is false when both the control signal 16 from the branch address generator 13 and the control signal 20 from the interrupt detector 17 are false, that is, when neither branch nor interrupt occurs. In some cases, the instruction location next to the current D stage instruction location is selected. On the contrary,
When a branch or interrupt occurs, the control signal 16 or 20 becomes true and the output of the OR circuit 24 becomes true,
The branch destination address held in the address register (B-ADRS) 23 is selected. The next instruction location or branch destination address selected by the selector 25 is held in the location register (D-LOC) 26.

In this embodiment, the branch address is determined in the D stage, and the delay slot of the branch instruction is one stage. Therefore, the instruction location of the D stage will change to the branch destination location two cycles after the branch instruction (that is, in the cycle next to the delay slot). Therefore, in this embodiment, as described above, the branch destination address that is selectively output from the selector 22 to the memory control device 11 is held in the address register 23 and delayed by one cycle to be supplied to the 1 side of the selector 25. Branch signal 1
4. The control signals 16 and 20 obtained by delaying the interrupt signal 19 by one cycle are input to the OR circuit 24 so that the contents of the location register 26 are correctly updated to the location of the branch destination after two cycles of the branch instruction. ..

As a result of the above, the location register (D-
LOC) 26 indicates the location of the branch instruction B in the cycle T2, the next instruction location obtained by incrementing the instruction location of the branch instruction B in the next cycle T3, that is, the delay slot of the branch instruction B is loaded. The location of the instruction L is indicated, and in the next cycle T4, it is updated to indicate the branch destination address (branch address 15) to the branch destination instruction N1 generated in the D stage of the branch instruction B.

Now, the detection of the interrupt (in the interrupt detecting device 17) is performed in the W stage as described above. Therefore, an instruction location is required in the W stage.
Therefore, in this embodiment, the location register (D-LO
C) The output side of the location register (E-LO
C) 27 and location register (W-LOC) 2
8 are connected in multiple stages so that the pipeline operation is performed up to the W stage in synchronization with the instruction. As a result, the contents of the location register (D-LOC) 26 are delayed by two cycles and the contents of the location register (W-LO) are delayed.
C) 28, the same register (W-LOC) 28,
In the cycle T4, the location of the branch instruction B is shown, in the next cycle T5, the location of the load instruction L is shown, and in the next cycle T6, the location of the branch destination instruction N1 is shown.

Here, as described above, an address translation interrupt occurs at the D stage (cycle T3) of the load instruction L, and the valid interrupt signal 19 and the start of interrupt processing at the W stage (cycle T5) of the same instruction L. The interrupt address 18 indicating the storage destination of the instruction I1 and the interrupt detection device 17
Shall be generated and output by. In this case, the interrupt address 18 is selected as the branch destination address by the selector 22 and output to the memory control device 11. Also, O
The output of the R circuit 21 becomes true, and a branch request is input to the memory control device 11. As a result, after the cycle T6, the interrupt processing instruction sequence I1, I2, I3 ... Is fetched from the memory 10 and the interrupt processing is performed.

When a valid interrupt signal 19 is output from the interrupt detector 17 in the cycle T5 (W stage of load instruction L), the instruction location indicated by the location register (W-LOC) 28 at that time, that is, the interrupt. The location of the load instruction L in the W stage that caused the (address conversion interrupt) is held in the address register (RTN-ADRS) 30 in cycle T6 as the address of the return destination instruction from the interrupt processing. At the same time, the location register at that time (EL
The instruction location indicated by OC) 27, that is, the location of the branch destination instruction N1 (the branch destination instruction N1 designated by the branch instruction B) at the E stage at that time (the branch destination address designated by the branch instruction B) is the return destination instruction. As the address of the next instruction to be executed, the address register (NXT-ADR
S) 29.

Next, the operation for returning from the above interrupt processing will be described with reference to the timing chart of FIG. 2 and the timing chart of FIG. In FIG. 3, B1 is a return destination from the interrupt processing (load instruction L)
To the instruction to be executed next to the load instruction L. Further, L is the return destination instruction from the interrupt processing (load instruction that caused the interrupt), and N1 is the instruction that was the branch destination of the branch instruction B shown in FIG.

When returning from the interrupt processing, first in cycle T11, the branch destination is set to the address register (RTN-
A branch instruction B1 having an address indicated by ADRS) 30, that is, a branch instruction B1 having a branch destination as a return destination (load instruction L) from the interrupt processing is fetched from the memory 10, and at the next cycle T12, D of the branch instruction B1 is fetched. The stage takes place. In cycle T12, the branch destination is the address indicated by the address register (NXT-ADRS) 29 (placed in the delay slot of the branch instruction B1).
2, that is, the branch instruction B2 to the instruction (N1) to be executed next to the return destination instruction (load instruction L) is fetched, and the D stage of the branch instruction B2 is performed in the next cycle T13.

At the D stage (cycle T12) of the branch instruction B1, the content held in the address register (RTN-ADRS) 30 is taken out by the branch address generation device 13 and the address indicated by the register (RTN-ADRS) 30, that is, The address of the return instruction (load instruction L) is output as the branch address 15. This branch address 1
Memory controller 11 is selected by selector 22
Is supplied to. At the same time, a valid branch signal 14 is output and a branch request is input to the memory controller 11.

As a result, the memory controller 11 fetches from the memory 10 the load instruction L designated by the branch address 15 (address of the return destination load instruction L) generated at the D stage (cycle T12) of the branch instruction B1. (F stage of cycle T13), and supplies to the instruction decoding device 12. As a result, from the next cycle T14, the processing after the D stage of the load instruction L that caused the interrupt in the delay slot of the branch instruction B is performed.

Next, in the D stage (cycle T13) of the branch instruction B2, the content held in the address register (NXT-ADRS) 29 is taken out by the branch address generation device 13, and is shown by the register (NXT-ADRS) 29. The address, that is, the address of the instruction (N1) to be executed next to the return destination instruction (load instruction L) is output as the branch address 15. This branch address 15 is the selector 22
And is supplied to the memory control device 11. At the same time, a valid branch signal 14 is output and a branch request is input to the memory controller 11.

As a result, the memory controller 11 selects the instruction N1 (in the delay slot) designated by the branch address 15 (address of the instruction N1 next to the return destination instruction L) generated in the D stage (cycle T13) of the branch instruction B2. The instruction which is the branch destination of the preceding branch instruction B) is fetched from the memory 10 (F stage of cycle T14), and the instruction decoding device 1
Supply to 2. As a result, from the next cycle T15, the processing after the D stage of the branch destination instruction N1 of the branch instruction B is performed.

In this way, in this embodiment, when returning from the interrupt processing, first, the address register (RTN-A
The branch instruction B1 designating a branch to the instruction (load instruction L) of the return address indicated by the DRS) 30 is executed, and further the address register (NXT-ADRS) 29 indicates (return in the delay slot of the branch instruction B1. A branch instruction B that specifies a branch to an instruction (N1) to be executed next to the preceding instruction)
2 is executed.

By executing the above branch instructions B1 and B2,
When the return destination is the delay slot of the branch instruction (B) as in this embodiment, the instruction (load instruction L) that generated the interrupt in the delay slot is executed first, and the instruction (L) is executed. After that, the branch instruction (B) preceding the delay slot is branched to the branch destination instruction (N1), and the return to the delay slot becomes possible.

When the return destination is not the delay slot of the branch instruction, the address register (NXT-ADRS)
Since the address of the instruction following the return instruction (next instruction) is held in 29, the address register (RTN-ADR
S) 30 return destination instruction and address register (NX
T-ADRS) 29 indicates a branch of consecutive addresses to the next instruction. That is, when the return destination is not the delay slot of the branch instruction, the branch instruction is only executed twice for consecutive addresses, and there is no problem in returning from the interrupt.

[0045]

As described in detail above, according to the present invention,
When starting interrupt processing, hold the return address from the interrupt processing and the address of the instruction to be executed next to the instruction at the return address, and when returning from the interrupt processing, first return address Since the branch instruction is executed, the return destination instruction is executed, and then the instruction is executed next to the return destination instruction, the interrupt from the delay slot of the branch instruction and the interrupt return to the delay slot are executed. It will be possible.

Therefore, there are no restrictions on the instructions that can be placed in the delay slot, and the delay slot can be effectively used. Further, the branch instruction and the delay slot can be placed over the page of the virtual address, and even if the branch instruction is used near the page boundary, the performance is not deteriorated.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of essential parts showing an embodiment of a pipeline type computer to which the present invention is applied.

FIG. 2 is a timing chart for explaining an operation when an interrupt occurs in a delay slot of a branch instruction.

FIG. 3 is a timing chart for explaining an operation when returning from interrupt processing.

FIG. 4 is a timing chart for explaining a delay slot of a branch instruction in a pipeline type computer.

[Explanation of symbols]

10 ... Memory, 11 ... Memory control device, 12 ... Instruction decoding device, 13 ... Branch address generation device, 14 ... Branch signal, 15 ... Branch address, 16, 20 ... Control signal, 17
... interrupt detection device, 18 ... interrupt address, 19 ... interrupt signal, 22, 25 ... selector, 23 ... address register (B-ADRS), 26 ... location register (D
-LOC), 27 ... Location register (E-LO
C), 28 ... Location register (W-LOC), 2
9 ... Address register (NXT-ADRS, second address holding means), 30 ... Address register (RTN-A
DRS, first address holding means).

Claims (1)

[Claims] 1. In a pipeline type computer for processing a branch instruction having a delay slot, first address holding means for holding an address of a return destination from interrupt processing, and an instruction of a return destination address from the interrupt processing. Second address holding means for holding the address of the instruction to be executed next, and when returning from the interrupt processing, branches to the return address held in the first address holding means, An interrupt processing method characterized in that after executing the instruction of the return destination, the instruction is branched to the instruction address held in the second address holding means.