JPH0514319A - Error detector - Google Patents

Abstract

PURPOSE:To prevent a problem that the hardware of the detector in a conventional error detector is increased at an increasing tempo when an input signal line number is increased because combinations of a multi-input OR and an AND gates are employed in the input of input signal lines for the discrimination as to whether or not two error signals '1' or over are in existence among plural signal lines. CONSTITUTION:The detector consists of a multiplexer section to multiplex an input signal line and a count discrimination section 2 converting and discriminating a multiplex signal. Moreover, the multiplex section 1 is provided with a multiplexing pulse generating counter 3 used to sample the input signal. Since the combination discrimination having been required for a conventional detector is not required for the circuit discriminating count after multiplexing of the input signal lines, rapid increase in the hardware is not caused even when number of signal lines is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm system in electronic equipment, and more particularly to an error detection function having a majority decision function for deciding whether or not two or more alarms have occurred among many alarm signals. It is related to vessels.

[0002]

2. Description of the Related Art A conventional error detector is shown in FIG. In the conventional detector shown in FIG. 3, in order to determine whether or not there are two or more signal lines of logic “1”, first, the signal line is separated into its own signal and other signals other than its own signal. However, it is determined whether or not the own signal is the logic "1" and the other signal is the logic "1", and the result of the determination for each signal line is logically ORed and output. The detection of the logic "1" in other signals in the drawing is performed by the n-1 input OR circuit connected to the input signal line.
Also, the judgment of the own signal logic "1" and the other signal logic "1" is 2
This is done by an input AND circuit.

[0003]

The above-mentioned conventional error detector performs error judgment by a combination of multi-input OR and AND gate, and has a simple circuit configuration, but the number of input signal lines is reduced. If it increases, the amount of hardware of this detector has the disadvantage that it increases at an accelerating rate.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel error detector capable of solving the above-mentioned drawbacks inherent in the conventional art. Especially.

[0005]

In order to achieve the above object, the error detector according to the present invention increases the amount of hardware in the conventional method of individually determining an error for each input signal line. The problem is solved by performing common processing without individually determining the input signal lines, that is, by performing a method of once multiplexing the input signal lines and determining whether there are two or more error signal lines within a certain period. There is. If such a method is used, each signal is sampled by the multiplexing pulse when the input signal line is multiplexed, so that it cannot be detected when an instantaneous error (alarm) less than the sampling period is input. This problem can be solved by obtaining the shortest time of the instantaneous error in the system design and setting the sampling cycle shorter than the shortest time.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings, which is a preferred embodiment thereof.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of each section.
It is

In FIG. 1, the multiplexer 1 receives the external clock 105 and receives the multiplexed pulses 111 (φ1), 11
2 (φ2), 113 (φ3), ... 114 (φn)
AND the multiplex pulse generation counter 3 for outputting the input signals 101, 102, 103 and 104
The count judging unit 2 is composed of, for example, a counter and a comparator, and judges whether the multiplexed signal contains two or more error information. To do.

The state in the counter of the count determination unit 2 is reset by the reset signal 115 which is a signal indicating the cycle of the multiplexed signal.

The state in the counter of the count judging unit 2 is shown at 210 in FIG. The output 107 is the count determination unit 2
As shown in the figure, the logic "1" is output when two or more input signals are error signals.

[0011]

As described above, the error detector of the present invention includes a multiplexer for converting a parallel signal of a plurality of signal lines into a serial signal and a count judgment for converting the multiplexed signal to make a judgment. Although it is completely different from the conventional one by including the section, the same output as the conventional one is obtained as a whole.

As a result, according to the present invention, it is possible to reduce the amount of hardware when the number of input lines to be subjected to error detection is relatively large, and it is possible to achieve a small space which has been impossible in the past. Will be able to implement.

[Brief description of drawings]

FIG. 1 is a circuit block configuration diagram showing an embodiment of an error detector according to the present invention.

FIG. 2 is a diagram showing an operation principle (timing chart) of the error detector according to the present invention.

FIG. 3 is a circuit block configuration diagram of a conventional error detector.

[Explanation of symbols]

1 ... Multiplexing unit 2 ... Count determination unit 3 ... Multiplex pulse generation counter

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[Procedure amendment]

[Submission date] July 6, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

Claims (2)

[Claims] 1. A signal line indicating the error input when it is judged as an error when there are two or more signal lines of the logic "1" indicating an error input in a plurality of signal lines and the logic "1" is output. In an error detector that determines that there is no error when the number is one or less and outputs a logic "0", a plurality of signal lines are multiplexed by multiplexing means, and the multiplexed signal is subjected to the next stage count determination. An error detector, wherein the error detector is input to the means, counts the logic "1" in the multiplexed signal by the count determination unit, and outputs by determining whether the count content is 2 or more. 2. The multiplexing means generates an AND circuit for inputting each signal line, an OR circuit for inputting an output of each AND circuit, and a multiplexing pulse for generating a multiplexing pulse to be supplied to each AND circuit. And a counter for counting the logic "1" output from the OR circuit, and a comparator for determining the output of the counter. The error detector described in 1.