JPS61140220A - Pulse signal detecting circuit - Google Patents

Abstract

PURPOSE:To remove the influences of noise by detecting each bit of input signal pulse by plural sampling pulses, and processing the result of detection by majority decision logic. CONSTITUTION:A sectional pulse generating circuit 8 oscillates pulses whose period in case of free oscillation is nearly T. This oscillation is synchronized at rising point and falling point of input signal pulse 12 and goes to sectional pulse. The sectional pulse 13 is inputted to a sampling pulse generating circuit 9, and eight pulses of equal intervals having period of <=T/8 is generated continuously synchronizing with, for instance, its falling point, and this is used as a sampling pulse 14. A pulse signal detecting and counting circuit 10 samples the input signal pulse 12 by the sampling pulse 14, and counts the number of pulses that obtained logic '1' as a sample value by a counter. The counter resets for each sectional pulse 13, and outputs counted value just before resetting from a pulse signal judging and outputting circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse signal detection circuit for detecting pulse signals.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional pulse signal detection circuit, in which (1) is a clock oscillation circuit, (2) is a sampling pulse correction circuit, and (3) is a signal detection circuit.

In the example shown in FIG. 3, if the bit period of the input signal pulse is T, the clock oscillation circuit (1) is T/32
oscillates a clock pulse with a period of 1/32
The input signal pulse is sampled by dividing the frequency and generating a sampling pulse with a period T, but the sampling pulse correction circuit (2) controls the sampling pulse so that it always coincides with the center of the bits of the input signal pulse. do.

FIG. 4 is an operation time diagram showing the timing of signals in each part of FIG. 3, where (4) shows the timing of logic change of the input signal pulse, the bit period is T, , (6) are sampling pulses,
The sampling pulse (6) is corrected by the sampling pulse correction circuit (2) so that it coincides approximately with the center of the bits of the input signal pulse (5).

FIG. 4 (7a), (7b) is a diagram for explaining the operation of the tri sampling pulse correction circuit (2), and (7a)
indicates the sampling pulse correction number corresponding to the sampling pulse four-division region (7b) and the Y'i region (7a).

The input signal pulse (5) is input to the sampling pulse correction circuit (
2), and the change points of the logic, that is, the rising and falling points of the waveform are detected. A clock with a period of T/32 from the clock oscillator circuit (1) is input to the sampling pulse correction circuit (21K, and is first frequency-divided to the fingers to generate 4 divided regions with a time width of V40, and then further divided into A. A sampling pulse with period T is output.2
Figure 4 (7a) shows the quadrant area between the two sampling pulses.
), we call them AI, Bl, and B2°A2.

The phase of the input signal pulse (5) and the sampling pulse (6)
) are determined independently from each other, so it is uncertain which of the four divided regions the logic change point of the input signal pulse (5) falls within. As shown in FIG. 4, when the logic change point of the input signal pulse (5) is between regions B1 and B2, the sampling pulse (6) coincides with the center of the bit of the input signal pulse (5). The sampling pulse correction circuit (2) performs control to maintain this state.

If the logic change point of the input signal pulse (5) falls within the A1 region, the sampling pulse correction circuit (2) converts the clock of period T/32 from the clock excavation circuit (1) to 1/32. A frequency dividing circuit that divides the frequency and generates a sampling pulse with a period T is controlled to have a frequency division ratio of 17 (32-2). -2 of the sampling pulse correction number (7b) represents -2 in 1/(32-2). As a result, the phase of the sampling pulse is advanced sequentially, and the logic change point of the input signal pulse (5) is in the area B1.
will enter. In region B1, the frequency is divided by 1/(32-1) to further advance the phase of the sampling pulse, so that the sampling pulse (6) comes to the center of the bits of the input signal pulse (5), and the input signal pulse (5) Control is performed so that the change point of the logic is between regions B1 and B2.

On the other hand, when in areas B2 and A2, the phase of the sampling pulse is delayed by 1/(32+1), respectively.
.

Perform frequency division by 1/(32+2).

Therefore, in the case where the logic change point of the input signal pulse (5) is at the left end of area A1, which is the worst case of desynchronization, it will take 4T to enter area B1, and after entering area B1, It takes 8T to reach the boundary point between Bl and B2 (that is, the synchronization point), and a total of 12T.

[Problem that the invention seeks to solve]

Since conventional circuits are configured as described above, there is a problem that if noise happens to mix into the input signal pulse at the time when sampling is performed with the sampling pulse, incorrect signal detection will be performed. In the worst case where there is a phase shift between the pulse and the sampling pulse, there is a problem in that it takes 12 T to achieve phase synchronization.

This invention was made to solve the above-mentioned problems. In this invention, it is not necessary to phase synchronize the input signal pulse and the sampling pulse, and even when noise is mixed in the input signal pulse, It is an object of the present invention to provide a pulse signal detection circuit that can eliminate the influence of this noise.

[Means for solving problems]

In this invention, a section pulse is generated that is synchronized with a logic change point of an input signal pulse and has a period T, and a plurality of sampling pulses are generated between each section pulse and the following section pulse. The results detected by the real sampling pulses are processed by majority logic within the relevant interval to determine the logic of the corresponding input signal pulse.

[Effect]

In this invention, each bit of the input signal pulse (bit with time width T) is detected by a plurality of sampling pulses, and the detected results are processed by full majority logic, so that the influence of noise can be removed.

Furthermore, since the plurality of sampling pulses are generated in synchronization with the interval pulses, synchronization with the input signal pulses is not required.

〔Example〕

All drawings of embodiments of this invention will be described below.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which (8) is a section pulse generation circuit, (9) is a sampling pulse generation circuit, (io') h pulse signal detection/counting circuit, and (11) is a block diagram showing an embodiment of the present invention. ) is a pulse signal judgment output circuit.

Figure 2 is an operation time diagram showing the timing of the signals of each part in Figure 1, where (12) is the input signal pulse, (13) is the interval pulse, (14) Vi sampling pulse, (15)
is the output data.

Next, the operation of the circuit shown in FIG. 1 will be explained. The interval pulse generation circuit (8) oscillates a pulse whose period is approximately T in the case of free oscillation, and this oscillation is synchronized with the rising and falling points of the input signal pulse (12), as shown in Fig. 2 (13). ) is the period pulse shown.

The sampling pulse generation circuit (9) generates an interval pulse (1
3) is input, and V8, for example, synchronizes with the falling point.
Eight equally spaced pulses having the following period are generated in succession. This is used as a sampling pulse (14). In the pulse signal detection counting time W&Cl0), the input signal pulse (12) is sampled with the e sampling pulse (14), and the number of pulses that obtain a logic "1" as a sample value is counted by a counter. The counter indicates each interval pulse (13
), and output from the counting compensation pulse signal judgment output circuit (11) immediately before the reset.

Therefore, when the input signal pulse (12) has no distortion or noise, the count value is 8 when the input signal pulse (12) is logic "1", and the count value is O when the input signal pulse (12) is logic "0". Due to the presence of noise, the count value in the case of logic "1" will be less than 8, and the count value in the case of logic "0" will be greater than 0, so
The pulse signal judgment output circuit (11) outputs a logic "1" when the count value is 5 or more, and a logic "0" when the count value is 4 or less. Although 8 pulses are generated and used as sampling pulses, any number of pulses other than 8 may be used.1. + They do not necessarily have to be equally spaced.

〔Effect of the invention〕

As described above, according to the present invention, sampling is performed using 8 sampling pulses corresponding to each period pulse, and 5 uh sampling pulses are used to perform logic r I J
Since the logic of the bit is set to "1" when t-detection is detected, there is no possibility of false detection due to noise or the like. Furthermore, since the interval pulse synchronizes the self-oscillation with the human input signal pulse, accurate synchronization can always be maintained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an operation time diagram showing the signal timing of each part of Fig. 1, Fig. 3 is a block diagram showing a conventional circuit, and Fig. 4 is 4 is an operation time diagram showing the timing of signals of each part in FIG. 3. FIG. In the figure, (8) is a section pulse generation circuit, (9) is a sampling pulse generation circuit, (10) is a pulse signal detection count number, and (11) is a pulse signal judgment output circuit.

Claims (1)

[Claims] When the bit period of the input signal pulse to be detected is T, a section pulse that generates a section pulse whose free oscillation period is approximately T and whose oscillation phase can be synchronized by an external signal. a generating circuit, a means for phase-synchronizing the interval pulse generating circuit with the rising and falling points of the input signal pulse, and a plurality of pulses between each interval pulse and the next interval pulse in synchronization with the interval pulse; a sampling pulse generation circuit that generates a sampling pulse of; a pulse signal detection and counting circuit that includes a counting circuit that samples the input signal pulse with the sampling pulse and counts the number of sampling pulses that obtain a logic "1" as a sample value; A pulse signal detection circuit comprising: means for resetting the counting circuit using the interval pulse; and a pulse signal determination output circuit for determining and outputting the logic of the input signal pulse based on the count value of the counting circuit immediately before being reset.