JPH02151144A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of a frame synchronizing circuit by using a counter generating a pulse for each frame and using the counter for detecting a detection signal from an even frame synchronizing pattern detector and for detecting a detection signal from an even frame synchronizing pattern detector. CONSTITUTION:When a signal series including a frame synchronizing pattern is inputted to, an input point 1 and an even frame synchronizing pattern detec tion circuit 3-1 detects an even frame synchronizing pattern, the circuit outputs a high level pulse as a detection signal. The detection signal is inputted to a forward/backward protection circuit 6 via an AND circuit 4-1. A control circuit 6 switches an output to an AND circuit 4-3 from a low level to a high level and an output to an AND circuit 4-4 from a low level to a high level. An odd frame synchronizing pattern detection circuit 3-2 detects an odd frame synchronizing pattern at the same time and outputs the detection signal, the detection signal reaches the forward/backward protection circuit 6 through the AND circuit 4-2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a frame synchronization circuit in a digital transmission device.

(Prior Art) A frame synchronization circuit establishes frame synchronization by continuously detecting a specific pattern signal from an input signal a certain number of times.

FIG. 2 is a configuration diagram showing a conventional example of a frame synchronization circuit in a case where frame synchronization patterns are different for even frames and odd frames. Here, 1 is an input point of a signal sequence including frame synchronization and a turn, 2-1 to 2-7 are 8-stage nostars, 3-1 is an even frame synchronization pattern detection circuit, 3
-2 is an odd frame synchronization pattern detection circuit, 4-1 to 4-
4 is an AND circuit, 8 is a clock input point, 9 is an output point of a frame synchronization establishment signal, 10 is an OR circuit, 11 is a control circuit, 12 is a forward/backward protection circuit, 13-1.13-2 is 2
It is an n counter. The signal sequence input to input point 1 has 8 bits as one constituent unit (octet), 80 octets as one frame, and LSB from octet O to octet 7 (bit O of 1 octet is LSB).
, bit 7 is the MSB). Note that n represents the number of bits in one frame.

Next, the operation of the frame synchronization circuit shown in FIG. 2 will be explained with reference to the time chart shown in FIG. 3. here,
For backward protection, synchronization is determined when an even frame synchronization turn, an odd frame IJtJ] no'' turn, and a corner frame synchronization pattern are detected consecutively. After synchronization is established, frames are detected as forward protection using consecutive even frame and odd frames. If the synchronization turn is incorrect by 1 bit or more, it is determined as a detection error, and if the detection error occurs three times in a row, it is determined that the synchronization is out of synchronization.

1. When in the initial state, a low
The level is output, the 2n counters 13-1 and 13-2 both stop counting, and the control circuit 11 c,
A high level is output to d. Since the even frame synchronization pattern detection circuit 3-1 and the odd frame synchronization pattern detection circuit 3-2 have not yet detected a frame synchronization pattern, their outputs are at Low level, so the output of the AND circuit 4-1.4-3 is The level becomes low, and the front
The rear protection circuit 9 outputs Lo to the output point 9 as an out-of-synchronization state.
Output w level.

Next, the signal sequence containing the frame synchronization pattern is input to the input point 1.
Suppose that it is entered in High when the even frame synchronization pattern detection circuit 3-1 detects an even frame synchronization pattern from the input and the output of the 8-stage shift renostars 2-1 to 2-7.
Outputs the h-level signal (a at time 1 in FIG. 3). At this time, the output of the 20 counter l3-1 is H
Since the signal is at a high level (C at time L! in FIG. 3), a high level signal (e at time 11 t l in FIG. 3) is output to the output of the AND circuit 4-1. The front/rear protection circuit 12 is this! When a pulse is detected, a high level is output to the AND circuit 4-2 and the OR circuit 10, and the 2n counter 13-1 starts counting based on the clock from the clock input point 8. The 2n counter 13-1 remains low until it counts 2n bits.
Output the level and count 2 n bits, it becomes High
A signal of h level (C at time t3 in FIG. 3) is output.

One frame after the even frame synchronization pattern detection circuit 3-1 detects the even frame synchronization pattern (time t1 in FIG. 3), the odd frame synchronization pattern detection circuit 3-2 detects the odd frame synchronization pattern (time 12 in FIG. 3). Detection of frame synchronization change L, Ht gh level noise (time t2 in
When b) is output, the 2n counter 13 is output in the same way as when the even frame synchronization pattern described above is detected.
-2 also starts counting.

However, one frame after the odd frame synchronization/turn detection circuit 3-2 detects the odd frame synchronization pattern (
At time t3 in FIG. 3), if the even frame synchronization/Q-turn detection circuit 3-1 cannot detect an even frame synchronization pattern, the forward/backward protection circuit 12 connects the AND circuit 4-2.
4-4 and OR circuit 10 output KLow level. 2
Both the n counters 13-1 and 13-2 stop counting, and their outputs are set to High level under the control of the control circuit 11 to return to the initial state. Note that even if an odd frame synchronization pattern is not detected one frame after the even frame synchronization pattern is detected (time tl in FIG. 3) (time t2), the initial state is returned in the same manner. That is, before synchronization is established, if an odd frame synchronization pattern or setan or an even frame synchronization pattern cannot be detected one frame after detecting an even frame synchronization pattern or an odd frame synchronization pattern, the process returns to the initial state.

Even frame synchronization
+ta), the forward/backward protection circuit 12 outputs the Hj gh level (9 at time t6 in FIG. 3) to the output point 9 as synchronization establishment.

After synchronization is established, the 2n counters 13-2 and 13-2 each output .P every 2n bits, that is, every 2 frames.
output from the pan frame synchronization/turn detection circuit 3-1 and the odd frame synchronization/turn detection circuit 3-2 via the AND circuit 4-1.4-3. input. However, if one or both of consecutive even frame synchronization patterns, odd frame synchronization, and P-turns cannot be detected, the forward/backward protection circuit 12 determines that there is a detection error and detects it three times in a row. When an error occurs, it is determined that synchronization has been lost and a low level is output to output point 9. At the same time, a LOW level is output to the AND circuits 4-2, 4-4 and the OR@ circuit 10. The 2n counters 13-1 and 13-2 both stop counting and set their outputs to High under the control of the control circuit 11.
Level and return to initial state. Figure 3 shows an example in which, after synchronization was established, no even frame synchronization pattern or odd frame synchronization/sequence could be detected between times t8 and t13, and it was determined that synchronization was lost at time t13, and the initial state was maintained thereafter. It shows.

(Problem to be Solved by the Invention) However, in the frame synchronization circuit with the above configuration, 2n
Since it requires two counter circuits and a control circuit to maintain the outputs of each of the 2n counters at a high level when synchronization is lost, there is a drawback that the scale of the circuit becomes enormous.

In order to eliminate the above-mentioned drawbacks, the present invention provides a frame synchronization circuit in which one n) counter is shared by an even frame synchronization pattern detection circuit and an odd frame synchronization pattern detection circuit, thereby reducing the circuit scale. purpose.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an even frame synchronization pattern detection circuit that detects an even frame synchronization pattern from an input signal, and an odd frame synchronization pattern detection circuit that detects an odd frame synchronization pattern from an input signal. A detection circuit and the even frame synchronization P
a gate circuit having a first gate that passes a detection signal from the turn detection circuit and a second gate that passes a detection signal from the odd frame synchronization pattern detection circuit; a forward/backward protection circuit that generates a second control signal; a counter that generates a signal synchronized with the detection signal for each frame based on the first control signal; a control circuit that switches the pulse and outputs it to the first or second gate of the gate circuit for control, and when the detection signal is a first detection signal, the counter operates according to the first control signal. and when the detection signal corresponds to an even frame synchronization pattern, the
The control circuit is controlled by the second control signal so as to output the signal to the second gate, and to the first gate when it corresponds to an odd frame synchronization pattern.

(Function) The detection signal from the even frame synchronization pattern detection circuit is passed through the first gate of the gate circuit, and the detection signal from the odd frame synchronization pattern detection circuit is passed through the second gate of the circuit. Each reaches the front and rear protection circuits.

Since the forward and backward protection circuits know in advance that even frame synchronization patterns and all frame synchronization patterns are sent alternately during normal operation, the A control circuit so as to apply the detection signal to the second gate when receiving a detection signal corresponding to an even frame synchronization pattern from the gate circuit, and to apply it to the first gate when receiving a detection signal corresponding to an odd seven frame synchronization pattern from the gate circuit. Does it control the even frame sync pattern or the odd frame sync pattern? The detection signal corresponding to the turn is extracted and the establishment of frame synchronization is determined.

Ru.

As described above, the present invention uses a single counter in common, without providing separate counters for extracting detection signals corresponding to even frame synchronization patterns and for extracting detection signals corresponding to odd frame synchronization patterns. The aim was to reduce the circuit scale.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention. In Figure 1, 1.2-1 to 2-7.3-1.3-2, 4-1 to
4-4, 8, and 9 are equivalent to those with the same symbols in Figure 2, 4-5 is an AND circuit, 5 is a control circuit, 6 is a forward/backward protection circuit, and 7 is an n counter. be. Furthermore, the signal sequence input to input point 1 is the same as in the case of FIG.

Next, the operation of this embodiment shown in FIG. 1 will be explained with reference to the time chart shown in FIG. 4. Here, as in the case of Fig. 2, as backward protection, synchronization is determined when an even frame synchronization pattern, an odd frame synchronization pattern, an even frame synchronization pattern, and a turn are detected consecutively, and after synchronization is established, forward protection is performed. If the frame synchronization pattern is incorrect by 1 bit or more in consecutive even frames and odd frames, it is determined to be a detection error, and if the detection error occurs three times in a row, it is determined to be out of synchronization. However, the above-mentioned criteria and the above-mentioned frame structure are only examples, and the present invention is not limited thereto. In FIG. 4, a is an even frame synchronization/9 turn detection circuit 3. -1 output, C is the output of the AND circuit 4-3, g is the output to the AND circuit 4-1 of the forward/backward protection circuit 6, e is the output of the AND circuit 4-1, b is odd frame synchronization, F The output of the turn detection circuit 3-2, d is the output of the AND circuit 4-4, h is the output of the n counter 7, f
is the output of the AND circuit 4-2, 9 is the forward/backward protection circuit 6
The outputs to output point 9 are shown respectively.

First, in the initial state, a low level is output from the forward/backward protection circuit 6 to the AND circuit 4-5, inhibiting the input of the clock from the clock input point 8 to the n counter 7. n counter 7 stops counting and becomes Hi.
gh level is output to AND circuit 4-3°4-4.

At the same time, the control circuit 5 sends a High level to the AND circuit 4-3 based on the signal from the front/rear protection circuit 6;
A low level is output to the circuit 4-4. Therefore, AND
The circuit 4-3 sends a High level to the AND circuit 4-1, and the A
The ND circuit 4-4 outputs a low level to the AND circuit 4-2, and when an even frame synchronization pattern is detected by the even frame synchronization pattern detection circuit 3-1, the detection signal is sent to the AND circuit 4-1. and is input to the front/rear protection circuit 6. Note that a low level is output to the output point 9 as an out-of-synchronization state.

Next, the signal sequence containing the frame synchronization pattern is input to the input point I.
Suppose that it is entered in The even frame synchronization pattern detection circuit 3-1 has an input and an 8-stage shift renostar 2-1 to 2-7.
High when an even frame synchronization pattern is detected from the output of
The h level pulse (a at time t1 in FIG. 4) is output as a detection signal. At this time, the output of the AND circuit 4-3 is at High level (C at time 1 in Figure 4).
Since the detection signal is held in the AND circuit 4-
1 to the front/rear protection circuit 6 (e at time t1 in FIG. 4). When the front/rear protection circuit 6 detects the detection signal, it outputs a high level to the AND circuit 4-5, and sends a predetermined signal to the control circuit 5. The control circuit 5 changes the output to the AND circuit 4-3 from High level to Low level based on the signal.
4 is switched from Low level to H4gh level. On the other hand, the counter 7 starts counting the clock input from the clock input point 8, and outputs a low level until it counts n bits, and when it counts n bits, it outputs 4 pulses of Hj gh level (at time t2 in FIG. 4). h) is output.

Therefore, the output pulse is input to the AND circuit 4-2 via the AND circuit 4-4 (d at time t2 in FIG. 4). The odd frame synchronization pattern detection circuit 3-2 is
Odd frame synchronization at the same time as the Luz was issued in
Since the turn is detected at , and a detection signal (b at time t2 in FIG. 4) is output, the detection signal is sent to the AND circuit 4-
2 and reaches the front/rear protection circuit 6 (f at time t2 in FIG. 4). The front/rear protection circuit 6 controls the control circuit 5 based on the detection signal and outputs the AND circuit 4-3.
is selected, the output pulse of the n counter 7 is input to the AND circuit 4-1, and a detection signal from the even frame 6 frame synchronization pattern detection circuit 3-2 is waited for.

However, if the even frame synchronization pattern detection circuit 3-1 cannot detect an even frame synchronization pattern at a predetermined time (time t3 in FIG. output the level,
A predetermined signal is output to the control circuit 5. The clock supply to the n counter 7 is stopped, and the n counter 7 stops counting. At this time, the output of the n counter is at High level.

On the other hand, the control circuit 5 outputs a High level to the AND circuit 4-3 and a Low level to the AND circuit 4-4.

This returns the frame synchronization circuit to its initial state. That is, before synchronization is established, if an odd frame synchronization turn or an even frame synchronization pattern cannot be detected one frame after detecting an even frame synchronization pattern or an odd frame synchronization pattern, the initial state is returned. return.

On the other hand, if an even frame synchronization pattern or an odd frame synchronization pattern is detected three times in a row (for example,
In the case of time E4 r j5 + t6 in FIG. 4),
The front and rear protection circuits 6 are in synchronization established state (rear protection complete)
, and outputs a high level (9 at time t6 in FIG. 4) to output point 9. After synchronization is established, the n counter 7 outputs a pulse every frame as described above, and the output pulse is switched by the AND circuit 4-3 and 4-4, and the output pulse is switched by the AND circuit 4 every two frames. -1.
Added to 4-2. On the other hand, the even frame synchronization pattern detection circuit 3-1 outputs a detection signal at the same timing as the signal applied to the AND circuit 4-1, and the odd frame synchronization pattern detection circuit 3-2 outputs a detection signal to the AND circuit 4-2. Since the detection signal is output at the same timing as the applied signal, each detection signal is output to the AND circuit 4-1 or 4-.
2 and sequentially reach the front and rear protection circuits 6.

Next, after synchronization is established, if one or both of the consecutive even frame synchronization/ξ turns and minute frame synchronization patterns cannot be detected, the forward/backward protection circuit 6 determines that a detection error has occurred, and If a detection error occurs three times in a row, it is determined that synchronization has been lost (forward protection has been completed) and a low level is output to output point 9. At the same time, the front/rear protection circuit 6 outputs a Low level to the AND circuit 4-5, and sends a predetermined signal to the control circuit 5, thereby setting it in an initial state. FIG. 4 shows the time t after synchronization is established.
Here is an example in which an even frame synchronization pattern and an odd frame synchronization pattern cannot be detected at each time from 8 to t13, and a detection error occurs three times in a row, and at time t13, it is determined that synchronization has been lost and the initial state is set. It shows.

After synchronization is established, in order to ensure the above-mentioned out-of-synchronization judgment operation, the forward and backward protection circuits 6 do not immediately return to the initial state when an even frame synchronization pattern or an odd frame synchronization pattern is not detected. The AND circuit 4-3, 4-4 is controlled via the control circuit 5 at the same timing as when the even frame synchronization pattern and the odd frame synchronization no' turn are normally detected until it is determined that the synchronization is out of synchronization. It is in a state of accepting detection signals from the even frame synchronization pattern detection circuit 3-1 and the odd frame synchronization pattern detection circuit 3-2.

(Effects of the Invention) As described above in detail, according to the present invention, the counter that generates frame 1 and guru is controlled by the detection signal from the even frame synchronization pattern detector and the odd frame synchronization pattern detector. Since it is shared for extracting the detection signal,
The number of counters that conventionally required two is now reduced to one, and with the accompanying simplification of peripheral circuits, it has become possible to reduce the circuit scale of the frame synchronization circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the frame synchronization circuit of the present invention, FIG. 2 is a block diagram of a conventional frame synchronization circuit, FIG. 3 is a time chart of the frame synchronization circuit shown in FIG. 2, and FIG. 4 is the diagram of the frame synchronization circuit shown in FIG. 3 is a time chart of the frame synchronization circuit shown in FIG. 1... Input point of signal sequence including frame/P turn,
2-1 to 2-7... 8-stage shift register, 3-1...
- Even frame synchronization pattern detection circuit, 3-2... Odd frame synchronization pattern detection circuit, 4-1 to 4-5...A
ND circuit, 5... control circuit, 6... forward/backward protection circuit, 7... n counter, 8... clock input point,
9...Frame synchronization establishment signal output point.

Claims (1)

[Claims] An even frame synchronization pattern detection circuit that detects an even frame synchronization pattern from an input signal; an odd frame synchronization pattern detection circuit that detects an odd frame synchronization pattern from an input signal; and an even frame synchronization pattern detection circuit that detects an odd frame synchronization pattern from the input signal. a gate circuit having a first gate that passes a detection signal from the odd frame synchronization pattern detection circuit and a second gate that passes a detection signal from the odd frame synchronization pattern detection circuit; and first and second control based on the detection signal from the gate circuit. a forward/backward protection circuit that generates a signal; a counter that generates a pulse synchronized with the detection signal for each frame based on the first control signal; and a counter that switches the pulse based on the second control signal and controls the gate. a control circuit that outputs a control signal to a first or second gate of the circuit; when the detection signal is the first detection signal, the first control signal starts the operation of the counter; The second control signal outputs the pulse to the second gate when corresponds to an even frame synchronization pattern, and outputs the pulse to the first gate when corresponds to an odd frame synchronization pattern. A frame synchronization circuit characterized by controlling a control circuit.