JP3092729B2 - Logic analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic analyzer which facilitates measurement of a pulse width distribution of a repetitive input signal.

[0002]

BACKGROUND ART logic analyzer samples the input digital signal stored in the memory by binarizing anew "1" and "0", a measuring instrument for performing waveform display.

FIG. 3 is a configuration diagram of a conventional example. In the figure, reference numeral 1 denotes a comparator which compares an input digital signal with a preset reference voltage and binarizes the digital signal into "1" and "0". These binarized signals are stored in the digital memory 2 at the set sampling rate.

The digital memory 2 stores the binarized data for one waveform display screen according to the clock signal input from the clock generator 4. It should be noted that the data for one waveform display screen is arranged in chronological order, and is hereinafter referred to as a data string.

A trigger circuit 3 generates a signal based on a trigger signal input from the outside and outputs the signal to a clock generator 4. The clock generator 4 generates a clock signal for displaying data in the digital memory 2 based on signals input from the trigger circuit 3 and the control circuit 7, and outputs the clock signal to the digital memory 2.

Reference numeral 5 denotes a signal processing circuit which converts a data string read from the digital memory 2 into display data.
Reference numeral 6 denotes a display for displaying display data output from the signal processing circuit 5. The control circuit 7 controls the timing of the clock signal output from the clock generator 4 to the digital memory 2 so as to control the display timing.

In such a configuration, when signals s1, s2, and s3 are superimposed and displayed as shown in FIG. 4, they are represented as w2. Here, the signals s1, s2, and s3 are data strings, respectively, and in the case of FIG. 4, data for three screens are viewed in an overlapping manner.

[0008]

However, in the case of the display example as shown in FIG. 4, even if the waveform of s4 overlaps with, for example, w2, it looks the same, and is the edge of e of w2 rising? It is difficult to determine whether it is falling.
That is, there is a problem that individual waveforms cannot be recognized, and it is not possible to know what input signals overlap.

The present invention has been made to solve such a problem, and realizes detection of the distribution of the pulse generation timing of an input signal by integrating the rising and falling events of digital data. The purpose is to:

[0010]

The present invention SUMMARY OF] inputs an input signal to the comparator binarizes at a predetermined reference voltage, the logic analyzer display, in the comparator
A differentiator for obtaining a difference between values before and after the binarized data sequence, and output data of the differentiator, and a comparator
A rising event discriminator for detecting the rising edge of the input digital input signal, the output data of said differentiator
Is input to the digital input signal input to the comparator.
A falling event discriminator for detecting a falling edge of a signal, a rising event integrator for adding the output of the rising event discriminator , and the falling event valve
And fall events integrator adds the output of another device, before
<br/> stores the output of the serial rising event integrator rising events register for outputting the value to rise event integrator, the fall event accumulator
Double based stores the output of the falling event register output to fall event integrator up the values provided, the trigger consists certain number of digital signals
The rising event of the data string taken several times and
The occurrence frequency of the falling event is determined by the rising event
Event register and falling event register
Display in the form of a histogram based on the data
Characterized in that it.

[0011]

The present invention integrates the rising and falling events of digital data and displays them in a histogram. This makes it easy to grasp the distribution of the pulse width data of the input waveform.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a basic hardware configuration diagram of the present invention. In FIG. 1, components similar to those in FIG. 3 are denoted by the same reference numerals.

In FIG. 1, reference numeral 10 denotes a differentiator for calculating a difference between before and after the data string input to the digital memory 2. Reference numeral 11a denotes a rising event discriminator.
Detects the rising edge of the signal input from. A falling event discriminator 11b detects the falling of the signal input from the differentiator 10.

Reference numeral 12a denotes a rising event register.
The internal data is updated by a signal input from the rising event discriminator 11a. Reference numeral 12b denotes a falling event register which updates internal data by a signal input from the falling event discriminator 11b.

A rising event integrator 13a integrates the output of the rising event discriminator into the data string of the rising event register 12 and updates the data string of the rising event register 12a. A falling event integrator 13b integrates the output of the falling event discriminator into the data string of the falling event register 12b and updates the data string of the falling event register 12b. The result of the integration is output to the signal processing circuit 5 and displayed on the display 6.

The operation of the above configuration will be described in detail with reference to FIG. FIG. 2 is a diagram showing the operation of each screen according to the present invention. p1 indicates a data string output from the digital memory 2 for screen display when a clock signal is input. At this time, the data in the data sequence is t1, t2,.
It changes every time. (P1) -1 indicates the first data string, and (p1) -2 indicates the second data string. Here, the first data string refers to a group of data which is taken in and stored in the digital memory 2 for display at the first acquisition, that is, at the first clock signal input.

P2 is the output of the differentiator 10, and (p2) -1
Represents the output of the first data sequence from the differentiator 10, and (p2)
-2 indicates an output of the differentiator 10 of the second data string.

P3 indicates the output of the rising event discriminator 11a, (p3) -1 indicates the output of the rising event discriminator 11a of the first data string, and (p3) -2 indicates the rising of the second data string. 5 shows the output of the event discriminator 11a.

P4 indicates the output of the falling event discriminator 11b, (p4) -1 indicates the output of the falling event discriminator 11b of the first data sequence, and (p4) -2 indicates the output of the second data sequence. 5 shows the output of the falling event discriminator 11b.

P5 is the output of the rising event integrator 13a, which is the result of integrating the rising events of the first and second data strings. p6 is the output of the falling event integrator 13b, which is the result of integrating the falling events of the first data string and the second data string.

Here, the data strings stored in the digital memory 2 are α1, α2, α3,... Αn. The outputs of the differentiator 10 are (α2-α1), (α3-α
2), (α4−α3).

Let (p1) -1 be the first data string. The output of the differentiator 10 at this time is as shown in (p2) -1. The output data of the differentiator 10 is -1, 0, 1 of 3
It consists of a value, -1 means falling of data, and 1 means rising. The output data of the differentiator 10 is discriminated into rising data and falling data in discriminators 11a and 11b, respectively.

That is, the rise discriminator 11a outputs 1 and 0 as they are, and outputs -1 by changing it to 0 (see (p3) -1). On the other hand, falling discriminator 11b
Outputs -1 and 0 as they are, and converts 1 to 0 and outputs (see (p4) -1).

The output data of the rise discriminator 11a is:
The rising integrator 13a adds the data string stored in the rising event register 12a to each item for each term, outputs the result to the signal processing circuit 5, and updates the value of the rising event register 12a. The initial value of the event register 12a is 0 for each item, and after the first acquisition, the data string of (p3) -1 rises and is stored in the event register 12a.

The output data of the falling discriminator 11b is
The falling integrator 13b adds the data string stored in the falling event register 12b to each item for each item, outputs the result to the signal processing circuit 5, and updates the value of the falling event register 12b. The initial value of the falling event register 12b is also 0 for each item, and after the first acquisition, the data string of (p3) -2 is stored in the falling event register 12b.

A data string obtained by the second acquisition is shown in (p1) -2. The output of the differentiator 10 is (p2)
-2, the outputs of the discriminators 11a and 11b are (p3) -2 and (p4) -2, respectively.

The rising integrator 13a adds the output of the rising discriminator 11a and the output of the rising event register 12a, and the falling integrator 13b outputs the output of the falling discriminator 11b and the falling event register 12b.
Add the outputs of These results are (p5) and (p6)
become that way. The same processing is performed for the third and subsequent acquisitions.

As described above, the change of the rising and falling events is represented in the form of a histogram for each event occurrence number, so that the distribution of the change of the pulse width including the jitter and the malfunction pulse can be detected. That is, in the case of this embodiment, since the data in the data string has a one-to-one correspondence with the time, information indicating which data is rising or falling is represented by (p5) or (p6). , The measurement of the change distribution of the pulse width becomes easy.

[0029]

As described above, according to the present invention,
A logic analyzer having a function of easily measuring the number of occurrences of rising and falling of a pulse visually and realizing efficient observation of a change in pulse width including jitter can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation for each screen according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional example of the present invention.

FIG. 4 is a diagram showing a screen of a conventional example of the present invention.

[Explanation of symbols]

 Reference Signs List 1 comparator 2 digital memory 3 trigger circuit 4 clock generation circuit 5 signal processing circuit 6 display 7 control circuit 10 differentiator 11a rising event discriminator 11b falling event discriminator 12a rising event register 12b falling event register 13a rising event integrator 13b Falling event integrator.

Claims (1)

(57) [Claims] An input signal is input to a comparator and a predetermined
In a logic analyzer that binarizes with a reference voltage and displays the difference, a difference device that calculates a difference between values before and after the data sequence binarized by the comparator, and output data of the difference device are input and input to the comparator.
The rising event discriminator that detects the rising of the input digital input signal and the output data of the differentiator are input and input to the comparator.
A falling event discriminator for detecting the falling of the input digital input signal, a rising event integrator for adding the output of the rising event discriminator, and a falling event accumulator for adding the output of the falling event discriminator And the output of the rising event integrator.
A rising event register for outputting the value to rise event integrator to, storing the output of the falling event accumulator Tomo
Multiple times based on a falling event register output to fall event integrator up the values provided, the trigger consists certain number of digital signals
Rising event and rising edge of the captured data string
The frequency of the falling event is determined by the rising event
Register and the falling event register.
A logic analyzer characterized in that the data is stacked and displayed in the form of a histogram based on data .