JPH05142567A - Formation of thin film - Google Patents

Formation of thin film

Info

Publication number
JPH05142567A
JPH05142567A JP30293891A JP30293891A JPH05142567A JP H05142567 A JPH05142567 A JP H05142567A JP 30293891 A JP30293891 A JP 30293891A JP 30293891 A JP30293891 A JP 30293891A JP H05142567 A JPH05142567 A JP H05142567A
Authority
JP
Japan
Prior art keywords
glass substrate
conductive
holder
film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30293891A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Kitamura
一芳 北村
Sadakichi Hotta
定▲吉▼ 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP30293891A priority Critical patent/JPH05142567A/en
Publication of JPH05142567A publication Critical patent/JPH05142567A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To provide the method for forming thin films used for production an image display device which reduces the coat by drastic simplification of process and has stable quality. CONSTITUTION:Overlap parts 7 of a conductive substrate holder 2 fixing a glass substrate 1 are formed long to the extent that these parts overlap on conductive electrode patterns 5 formed on the glass substrate 1 or a conductive mask is freshly added to the conductive substrate holder 2, by which the films are not deposited on the taking-out electrode part surface at the ends of the conductive electrode patterns 5 covered with the holder 2 or the mask added thereto and are selectively formed only in the regions exclusive thereof. In addition, the films are formed by electrically connecting the holder 2 or the mask added thereto and the conductive electrode patterns 5 formed on the glass substrate 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は従来のブラウン管に代わ
り、パソコンやテレビ等の表示機器として使用されつつ
ある液晶ディスプレイなどの平面型画像表示装置および
これを製造する上で必要不可欠な薄膜形成方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention replaces a conventional cathode ray tube with a flat image display device such as a liquid crystal display which is being used as a display device such as a personal computer and a television, and a thin film forming method essential for manufacturing the same. It is about.

【0002】[0002]

【従来の技術】液晶ディスプレイを始めとした薄膜形成
技術を用いたデバイスは軽薄短小、省エネルギーが求め
られる中、今後ますますその市場拡大が期待されてい
る。
2. Description of the Related Art As devices using thin film forming technology such as liquid crystal displays are required to be light, thin, short, and energy-saving, the market is expected to expand further in the future.

【0003】以下これら薄膜形成方法の中でも特に液晶
ディスプレイを製造する上で必要とされるプラズマCV
D法を例にとり、従来の技術について説明する。
Among these thin film forming methods, plasma CV required especially for manufacturing a liquid crystal display will be described below.
The conventional technique will be described by taking the D method as an example.

【0004】液晶ディスプレイは絶縁性のガラス基板上
に真空蒸着法(例えばスパッタリング法やプラズマCV
D法)により導電性薄膜や絶縁性薄膜さらには半導体薄
膜が幾層にも積み重ねられ製造される。
Liquid crystal displays are manufactured by vacuum vapor deposition (eg, sputtering or plasma CV) on an insulating glass substrate.
By the method D), a conductive thin film, an insulating thin film, and a semiconductor thin film are stacked in layers to be manufactured.

【0005】図4はプラズマCVD装置の概略構成を示
したものである。被成膜物であるガラス基板1がアース
電極を兼ねたステンレスまたはアルミニウムでできた金
属製のホールダ2に固定され、これに対向した高周波電
極3およびこれに接続された高周波電源4で構成されて
いる。これを100Pa程度のモノシランやアンモニア
などの低圧ガス中で両電極間に13.56MHzの高周波
電力を印加することにより、ガスの分解が生じガスの種
類に応じた所望の膜がガラス基板1の表面に堆積される
わけである。
FIG. 4 shows a schematic structure of a plasma CVD apparatus. A glass substrate 1 which is an object to be deposited is fixed to a metal holder 2 made of stainless steel or aluminum which also serves as a ground electrode, and is constituted by a high frequency electrode 3 facing the metal holder 2 and a high frequency power source 4 connected to the high frequency electrode 3. There is. By applying a high frequency power of 13.56 MHz between both electrodes in a low-pressure gas such as monosilane or ammonia of about 100 Pa, decomposition of the gas occurs and a desired film corresponding to the type of gas is formed on the surface of the glass substrate 1. It will be deposited on.

【0006】図5はガラス基板1がホールダ2に固定さ
れている状態の断面図である。既に電極パターン5が形
成された被成膜用ガラス基板1がホールダ2およびこれ
と同種の金属の裏板6で挟まれ固定されている。この時
ガラス基板1の表面(電極パターン5が形成された側の
面)はホールダ2とはガラス基板の周辺全てにおいて3
〜5mm程度の重なり部7を有している。通常この部分は
素子として使用しない領域であり、当然電極パターン5
もこれよりある間隙を有して内側に形成されている。従
って膜は前記電極パターン5の上にも堆積されるととも
に金属製ホールダ2とガラス基板1上の電極パターン5
は電気的に絶縁された構成で膜形成されることとなる。
FIG. 5 is a sectional view showing a state where the glass substrate 1 is fixed to the holder 2. A glass substrate 1 for film formation on which an electrode pattern 5 has already been formed is sandwiched and fixed by a holder 2 and a metal back plate 6 of the same kind as the holder 2. At this time, the surface of the glass substrate 1 (the surface on which the electrode pattern 5 is formed) is different from the holder 2 in all around the glass substrate.
It has an overlapping portion 7 of about 5 mm. Normally, this part is a region not used as an element, and naturally the electrode pattern 5
Is also formed inside with a certain gap. Therefore, the film is deposited on the electrode pattern 5 as well as the metal holder 2 and the electrode pattern 5 on the glass substrate 1.
Will be formed into a film with an electrically insulated structure.

【0007】[0007]

【発明が解決しようとする課題】このような従来方法で
はガラス基板上に既に形成されている電極パターンの上
全面にも膜が堆積されるため、その後さらにフォトリソ
グラフィおよびエッチング工程を追加して膜の一部分を
除去するという作業が必要となり、これが素子の歩留り
低下やコストアップの要因の1つになっている。
In such a conventional method, since the film is deposited on the entire surface of the electrode pattern already formed on the glass substrate, the photolithography and etching steps are further added thereafter. The work of removing a part of the above is required, and this is one of the factors that reduce the yield of the device and increase the cost.

【0008】また別の問題として、プラズマCVD法で
はモノシラン、アンモニアなどのガスを100Pa程度
の低圧で放電させるため、これらのガスはイオン化して
いる。このため液晶ディスプレイなどに用いるガラスな
ど絶縁性基板に膜形成する際、これらのイオンがガラス
基板の表面に付着し、ガラス基板上に形成された導電性
の電極パターンに帯電が生ずることにより放電の偏りや
スパークなどの異常放電が発生し、堆積される膜の不均
一が生ずる原因の1つとなっている。
As another problem, in the plasma CVD method, gases such as monosilane and ammonia are discharged at a low pressure of about 100 Pa, so these gases are ionized. Therefore, when a film is formed on an insulating substrate such as glass used for a liquid crystal display, these ions adhere to the surface of the glass substrate, and the conductive electrode pattern formed on the glass substrate is charged to cause discharge. Abnormal discharge such as unevenness and sparks is generated, which is one of the causes of nonuniformity of the deposited film.

【0009】[0009]

【課題を解決するための手段】これら従来の課題を解決
するために本発明の薄膜形成方法は、ガラス基板を固定
する導電性基板ホールダの重なり部分をガラス基板上に
形成されている導電性電極パターンと重なる程度に長く
する。
In order to solve these conventional problems, a thin film forming method of the present invention is a conductive electrode in which an overlapping portion of a conductive substrate holder for fixing a glass substrate is formed on the glass substrate. Make it long enough to overlap the pattern.

【0010】[0010]

【作用】この構成によれば、導電性基板ホールダに覆わ
れた導電性電極パターン端部の取り出し電極部表面には
膜を堆積させずに、それ以外の領域にのみ選択的に膜形
成されるとともに、前記ホールダとガラス基板上に形成
されている導電性電極パターンを電気的に接続させて膜
形成される。
According to this structure, no film is deposited on the surface of the extraction electrode portion at the end of the conductive electrode pattern covered with the conductive substrate holder, and the film is selectively formed only on the other regions. At the same time, a film is formed by electrically connecting the holder and the conductive electrode pattern formed on the glass substrate.

【0011】[0011]

【実施例】本発明の薄膜形成方法の一実施例について、
図1に示したプラズマCVD法による膜形成時のガラス
基板の固定状態を示す断面図を参照しながら説明する。
EXAMPLE An example of the thin film forming method of the present invention will be described.
Description will be made with reference to the cross-sectional view showing the fixed state of the glass substrate at the time of film formation by the plasma CVD method shown in FIG.

【0012】本実施例の薄膜形成方法を示す図1の各部
名称は図5に示した従来のものと同様であり、同一箇所
には同一符号を付した。
The names of the respective parts in FIG. 1 showing the thin film forming method of this embodiment are the same as those of the conventional one shown in FIG. 5, and the same parts are designated by the same reference numerals.

【0013】本実施例の構成では、ガラス基板1を固定
する導電性基板ホールダ2の重なり部分7を従来に比べ
導電性電極パターン5の端部を覆うように十分長くし、
これら導電性基板ホールダ2とガラス基板1上に形成さ
れている導電性電極パターン5は電気的に接続されてい
る。なお、導電性基板ホールダ2はアース電極としての
機能を有していることや、裏板6の機能などは従来のも
のと同じである。
In the structure of this embodiment, the overlapping portion 7 of the conductive substrate holder 2 for fixing the glass substrate 1 is made sufficiently long so as to cover the end portion of the conductive electrode pattern 5 as compared with the conventional case,
The conductive substrate holder 2 and the conductive electrode pattern 5 formed on the glass substrate 1 are electrically connected. The conductive substrate holder 2 has a function as a ground electrode and the function of the back plate 6 is the same as the conventional one.

【0014】また図2は画像表示装置周辺部の拡大断面
図であり、導電性電極パターン端部の取り出し端子部1
3およびその表面に堆積された絶縁性保護膜15,1
5′の断面形状を例にとり示したものである。
FIG. 2 is an enlarged cross-sectional view of the peripheral portion of the image display device, showing the lead-out terminal portion 1 at the end of the conductive electrode pattern.
3 and insulating protective films 15, 1 deposited on the surface thereof
The cross-sectional shape of 5'is shown as an example.

【0015】図2の(a)は従来方法によるもの、
(b)は本実施例によるものを示している。
FIG. 2A shows a conventional method,
(B) shows the one according to the present embodiment.

【0016】(a)の従来方法では薄膜形成時に絶縁性
保護膜15は取り出し端子部表面にも堆積するため、後
の工程でこの部分(絶縁性保護膜15の切欠部)をエッ
チングする必要がある。このためエッチングされた部分
近傍の絶縁性保護膜15の膜厚はほぼ均一である。
In the conventional method of (a), since the insulating protective film 15 is deposited on the surface of the lead-out terminal portion when the thin film is formed, it is necessary to etch this portion (the cutout portion of the insulating protective film 15) in a later step. is there. Therefore, the film thickness of the insulating protective film 15 near the etched portion is substantially uniform.

【0017】これに対し(b)の本実施例ではプラズマ
CVD法の性質により、絶縁性保護膜の膜厚は金属製ホ
ールダ2によってマスクされた取り出し端子部13の端
部から内側0.2〜10mmの領域において、なだらかな
斜面の特徴的形状を示す。
On the other hand, in the present embodiment (b), due to the nature of the plasma CVD method, the thickness of the insulating protective film is 0.2 to the inside from the end of the lead terminal portion 13 masked by the metal holder 2. In the area of 10 mm, a characteristic shape of a gentle slope is shown.

【0018】なお、本実施例は重なり部7を長くしたも
のであるが、これに限らず別途、パターン5を覆うよう
に導電性のマスクをホールダ2に設けても同様の効果が
得られる。
In this embodiment, the overlapping portion 7 is made long, but the present invention is not limited to this, and the same effect can be obtained by separately providing a conductive mask on the holder 2 so as to cover the pattern 5.

【0019】図3は薄膜トランジスタ(以下TFTと記
す)を内蔵した液晶パネルの周辺部の取り出し端子部と
逆スタガ構造のTFT部の概略構造を示す断面図であ
り、(a)は従来方法で作成したもの、(b)は本発明
の方法で作成したものを示している。
FIG. 3 is a cross-sectional view showing a schematic structure of a lead-out terminal portion of a liquid crystal panel in which a thin film transistor (hereinafter referred to as a TFT) is built-in and a TFT portion having an inverted stagger structure. FIG. And (b) shows the one prepared by the method of the present invention.

【0020】まず、(a)を例にとりその構造および製
造方法を簡単に説明する。ガラス基板1にCrなどのゲ
ート電極8をパターン形成しさらにゲート絶縁膜9およ
びアモルファスシリコンなどの半導体層10をプラズマ
CVD法で薄膜形成する。半導体層10をパターン化し
その両端にソース電極11およびドレイン電極12を形
成する。その後、酸化インジウム錫(ITO)で取り出
し用電極パッド13および絵素電極14を形成し、最後
に窒化シリコンの絶縁性保護膜15をプラズマCVD法
で形成する。またこのパネルを駆動するために電極パッ
ド13に導電性粒子16を介しリード電極17が接続さ
れ、これが外部IC(図示せず)につながれている。こ
こでゲート電極8、ゲート絶縁膜9、半導体層10で構
成された部分がMOS構造を有したTFT部であり、プ
ラズマCVD法で形成されるゲート絶縁膜および半導体
層の均一性が重要であると共に静電気による素子の特性
劣化や破壊に注意しなければならない。
First, the structure and manufacturing method will be briefly described by taking (a) as an example. A gate electrode 8 of Cr or the like is patterned on the glass substrate 1, and a gate insulating film 9 and a semiconductor layer 10 of amorphous silicon or the like are formed into a thin film by a plasma CVD method. The semiconductor layer 10 is patterned and the source electrode 11 and the drain electrode 12 are formed on both ends thereof. After that, the extraction electrode pad 13 and the pixel electrode 14 are formed of indium tin oxide (ITO), and finally the insulating protective film 15 of silicon nitride is formed by the plasma CVD method. Further, in order to drive this panel, a lead electrode 17 is connected to the electrode pad 13 via the conductive particles 16, and this is connected to an external IC (not shown). Here, the portion composed of the gate electrode 8, the gate insulating film 9 and the semiconductor layer 10 is a TFT portion having a MOS structure, and the uniformity of the gate insulating film and the semiconductor layer formed by the plasma CVD method is important. At the same time, attention must be paid to the deterioration and destruction of the characteristics of the element due to static electricity.

【0021】図3(a)に示す従来方法では、ゲート絶
縁膜9や絶縁性保護膜15をプラズマCVD法で形成す
る際、ゲート電極8や電極パッド13の全面に堆積され
るため、この例では後工程でゲート電極8と電極パッド
13を接続するためのゲート絶縁膜9のコンタクト窓形
成および電極パッド13と導電性粒子16を接触させる
ための絶縁性保護膜15のコンタクト窓形成が必要であ
る。またこれらのコンタクト窓形成は絶縁性膜9,15
を液体や気体中で化学反応させ除去するが、この時に下
地の電極表面に反応生成物が形成されたり、レジスト除
去時に有機物の付着が生じ、電極間の接触性が損なわれ
るという弊害が発生する。
In the conventional method shown in FIG. 3A, when the gate insulating film 9 and the insulating protective film 15 are formed by the plasma CVD method, they are deposited on the entire surface of the gate electrode 8 and the electrode pad 13. In a later step, it is necessary to form a contact window for the gate insulating film 9 for connecting the gate electrode 8 and the electrode pad 13 and a contact window for the insulating protective film 15 for contacting the electrode pad 13 and the conductive particles 16. is there. Moreover, these contact windows are formed by insulating films 9 and 15
Is chemically reacted in a liquid or gas to remove it, but at this time reaction products are formed on the surface of the underlying electrode, and organic substances are attached during resist removal, resulting in the loss of contact between electrodes. ..

【0022】しかし本発明によれば、図3(b)に示す
ようにゲート絶縁膜9および絶縁性保護膜15をプラズ
マCVD法で堆積させる際に、ガラス基板1の端部から
ゲート電極9の一部まで基板ホールダで覆われた構成と
なっているため、この部分の電極表面には選択的に絶縁
性膜が堆積されず、少なくとも2ヵ所のコンタクト窓形
成工程は不要となる。実際の液晶パネルの製造工程はさ
らに複雑であるが、本発明の方法を駆使すれば従来7〜
9枚のマスク回数で製造されていたものが4〜6枚に削
減することができ、大幅な工程の簡略化が実現できる。
However, according to the present invention, as shown in FIG. 3B, when the gate insulating film 9 and the insulating protective film 15 are deposited by the plasma CVD method, the gate electrode 9 is removed from the end portion of the glass substrate 1. Since the structure is partially covered with the substrate holder, the insulating film is not selectively deposited on the electrode surface in this part, and the contact window forming step at least at two places is unnecessary. The actual manufacturing process of the liquid crystal panel is more complicated.
The number of masks manufactured with 9 masks can be reduced to 4 to 6 masks, and a great simplification of the process can be realized.

【0023】また、コンタクト窓形成が不要になること
により、電極表面は化学的処理にさらされることがなく
常に清浄であり、電極間の接触性が大幅に向上し素子の
歩留りや信頼性が向上するなどその効果は非常に大なる
ものがある。
Further, since the formation of the contact window is not necessary, the electrode surface is not exposed to the chemical treatment and is always clean, the contact property between the electrodes is greatly improved, and the yield and reliability of the element are improved. The effect is very great.

【0024】また従来方法では、プラズマCVDによる
膜形成時に図5で示した導電性電極パターン5に相当す
るゲート電極8および電極パッド13はアース電極を兼
ねた導電性基板ホールダ2に接していないため、ガラス
基板1の表面電位が不安定になり膜の不均一および素子
の特性劣化や破壊が発生しやすい。しかし本発明の方法
によれば、図1に示すようにガラス基板1上に形成され
た導電性電極パターン5は常にアース電極である導電性
基板ホールダ2と接触し同電位が保たれる所となり、ガ
ラス基板表面の電位が非常に安定し、異常放電などが回
避でき、膜の均一性が大幅に向上すると共に、放電によ
る素子へのダメージも大幅に低減できる。
Further, in the conventional method, the gate electrode 8 and the electrode pad 13 corresponding to the conductive electrode pattern 5 shown in FIG. 5 are not in contact with the conductive substrate holder 2 which also functions as a ground electrode when the film is formed by plasma CVD. In addition, the surface potential of the glass substrate 1 becomes unstable, and unevenness of the film and deterioration or destruction of device characteristics are likely to occur. However, according to the method of the present invention, as shown in FIG. 1, the conductive electrode pattern 5 formed on the glass substrate 1 is always in contact with the conductive substrate holder 2 which is the ground electrode and is kept at the same potential. The potential on the surface of the glass substrate is very stable, abnormal discharge can be avoided, the uniformity of the film is greatly improved, and damage to the device due to discharge can be significantly reduced.

【0025】[0025]

【発明の効果】以上のように本発明によれば、ホールダ
に覆われたガラス基板周辺部の電極パターンの上には選
択的に膜形成が行われないため、従来実施していた後工
程での電極取り出しのための膜の除去作業が不要とな
り、大幅な工程の簡略化が実現できるところとなる。
As described above, according to the present invention, a film is not selectively formed on the electrode pattern in the peripheral portion of the glass substrate covered with the holder. Since the work of removing the film for taking out the electrode is unnecessary, a great simplification of the process can be realized.

【0026】さらに膜形成時のイオン性ガス雰囲気中に
おいてもガラス基板上に形成された導電性電極パターン
はアース電極であるホールダと常に同電位が保たれる所
となり、ガラス基板表面の電位が非常に安定し、異常放
電などが回避でき、膜の均一性が大幅に向上する。
Furthermore, even in an ionic gas atmosphere during film formation, the conductive electrode pattern formed on the glass substrate is always kept at the same potential as the holder serving as the ground electrode, and the potential of the glass substrate surface is extremely high. It is stable, and abnormal discharge can be avoided, and the uniformity of the film is greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における薄膜形成時のガラス
基板の固定状態を示す断面図
FIG. 1 is a cross-sectional view showing a fixed state of a glass substrate at the time of forming a thin film in one embodiment of the present invention.

【図2】(a)従来の画像表示装置の周辺部断面構造図 (b)本発明の一実施例における画像表示装置の周辺部
断面構造図
FIG. 2A is a sectional structure view of a peripheral portion of a conventional image display device. FIG. 2B is a sectional structure diagram of a peripheral portion of an image display device according to an embodiment of the invention.

【図3】(a)従来方法で作成したTFT液晶パネル周
辺部の断面構造図 (b)本発明の方法で作成したTFT液晶パネル周辺部
の断面構造図
FIG. 3A is a sectional structure view of a peripheral portion of a TFT liquid crystal panel prepared by a conventional method. FIG. 3B is a sectional structure view of a peripheral portion of a TFT liquid crystal panel prepared by the method of the present invention.

【図4】プラズマCVD装置の概略構成図FIG. 4 is a schematic configuration diagram of a plasma CVD apparatus.

【図5】従来の薄膜形成時のガラス基板の固定状態を示
す断面図
FIG. 5 is a cross-sectional view showing a fixed state of a glass substrate when forming a conventional thin film.

【符号の説明】[Explanation of symbols]

1 ガラス基板 2 導電性基板ホールダ 5 ガラス基板上に形成された導電性電極パターン 6 裏板 7 ガラス基板と基板ホールダの重なり部 1 Glass Substrate 2 Conductive Substrate Holder 5 Conductive Electrode Pattern Formed on Glass Substrate 6 Back Plate 7 Overlapping Area of Glass Substrate and Substrate Holder

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板を導電性基板ホールダで固定し
て真空蒸着法により前記絶縁性基板上に薄膜形成する方
法であって、 前記導電性基板ホールダ上に形成されている電極パター
ンに重なるように前記絶縁性基板を前記導電性基板ホー
ルダで固定して薄膜形成する薄膜形成方法。
1. A method of fixing an insulating substrate with a conductive substrate holder and forming a thin film on the insulating substrate by a vacuum deposition method, the method including overlapping with an electrode pattern formed on the conductive substrate holder. A thin film forming method of forming a thin film by fixing the insulating substrate with the conductive substrate holder as described above.
JP30293891A 1991-11-19 1991-11-19 Formation of thin film Pending JPH05142567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30293891A JPH05142567A (en) 1991-11-19 1991-11-19 Formation of thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30293891A JPH05142567A (en) 1991-11-19 1991-11-19 Formation of thin film

Publications (1)

Publication Number Publication Date
JPH05142567A true JPH05142567A (en) 1993-06-11

Family

ID=17914946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30293891A Pending JPH05142567A (en) 1991-11-19 1991-11-19 Formation of thin film

Country Status (1)

Country Link
JP (1) JPH05142567A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009016231A (en) * 2007-07-06 2009-01-22 Sony Corp Manufacturing method of organic el display device, and organic el display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009016231A (en) * 2007-07-06 2009-01-22 Sony Corp Manufacturing method of organic el display device, and organic el display device
US8901813B2 (en) 2007-07-06 2014-12-02 Sony Corporation Method for manufacturing organic EL display and organic EL display
US8926390B2 (en) 2007-07-06 2015-01-06 Sony Corporation Method for manufacturing organic EL display and organic EL display
US9136314B2 (en) 2007-07-06 2015-09-15 Joled Inc. Method for manufacturing organic EL display and organic EL display
US9508781B2 (en) 2007-07-06 2016-11-29 Joled Inc. Method for manufacturing organic EL display and organic EL display

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