JP2001339065A - Optoelectronic device, and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of an optoelectronic device for collectively performing the formation of data lines and the cutting process of wiring for short-circuiting, and the optoelectronic device. SOLUTION: A plurality of scanning lines 3 and a plurality of data lines 6 that cross one another are arranged on an FET array substrate for composing this optoelectronic device, a TFT 30 and a pixel electrode 9 are arranged at each crossing part, and further capacitors 3b are arranged nearly in parallel for each of the scanning lines 3. While the TFT array substrate is being manufactured, wiring 90 for short-circuiting for electrically connecting the scanning lines 3 and the capacity lines 3b is formed, and the wiring 90 for short-circuiting is cut at a cutting position that is marked by X. The cutting process of the wiring 90 for short-circuiting and the formation process of the data lines 6 are performed collectively by dry etching, thus reducing manufacturing processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electro-optical device and a technical field of the electro-optical device, and more particularly to a method of manufacturing an electro-optical device for cutting a short-circuit wiring during a process of forming a switching element, and a method of manufacturing the same. The present invention relates to an electro-optical device manufactured by the same.

[0002]

2. Description of the Related Art For example, a liquid crystal device as an electro-optical device has a structure in which a liquid crystal layer is held between a TFT (Thin Film Transistor) array substrate and a counter substrate which are arranged opposite to each other. In a TFT array substrate, a semiconductor layer is disposed on a substrate such as a quartz substrate, a gate insulating film is disposed over the semiconductor layer, a plurality of scanning lines are disposed on the gate insulating film, and a first line is disposed over the scanning line. An interlayer insulating film is arranged, and a plurality of data lines are arranged on the first interlayer insulating film so as to intersect with the scanning lines. Further, a second interlayer insulating film is arranged so as to cover the data lines, and a pixel electrode is arranged on the second interlayer insulating film. The data line is electrically connected to the source region of the semiconductor layer through a first contact hole formed in the gate insulating film and the first interlayer insulating film, and the pixel electrode is formed by the gate insulating film and the first interlayer insulating film And a second contact hole formed in the second interlayer insulating film, and is electrically connected to the drain region of the semiconductor layer. During the manufacturing process of the TFT array substrate having such a configuration, a short-circuit wiring is formed in order to prevent the TFT from being destroyed by static electricity generated during the manufacturing process.

For example, in order to prevent the TFT from being destroyed during the manufacturing process, a short-circuit wiring for electrically connecting the scanning lines is formed in the same layer as the scanning lines. At present, the step of disconnecting the short-circuit wiring for disconnecting the electrical connection between the scanning lines is performed after the step of forming the data lines. Specifically, a cutting hole is provided by wet-etching a part of the first interlayer insulating film on the short-circuit wiring. Next, after forming an aluminum film on the first interlayer insulating film, the data line is formed by patterning the aluminum film by wet etching using the data line shape resist as a mask,
After that, the resist is removed. Further, the electrical connection between the scanning lines is cut by etching the short-circuit wiring made of polysilicon using the cutting hole as a mask. Thereafter, the surface of the first interlayer insulating film is wet-etched.
The etching of the surface of the first interlayer insulating film is for removing the surface of the first interlayer insulating film that has been altered by forming an aluminum film on the first interlayer insulating film by sputtering. Thereby, the shape of the second contact hole to be formed later can be improved.

[0004]

However, in the above-described method, it is necessary to separately perform a data line forming step, a short-circuit wiring cutting step, and an etching step of the first interlayer insulating film surface.

An object of the present invention is to provide a method of manufacturing electro-optics in which these steps are performed collectively to reduce the number of manufacturing steps, and an electro-optical device manufactured by the method.

[0006]

In order to solve such a problem, the present invention employs the following configuration.

In a method of manufacturing an electro-optical device according to the present invention, a semiconductor layer having a source region and a drain region disposed on a substrate with a channel region interposed therebetween is formed, and a gate is formed on the substrate so as to cover the semiconductor layer. Forming an insulating film;
Forming, on the gate insulating film, a plurality of scan lines partially corresponding to the channel region, and a short-circuit wire for electrically connecting each scan line in the same layer as the scan lines; Forming an interlayer insulating film on the gate insulating film so as to cover the line and the short-circuit wiring, and forming a first contact hole at a position corresponding to the source region of the gate insulating film and the interlayer insulating film. Forming a second contact hole, which is a cutting hole, between adjacent scanning lines in the interlayer insulating film on the short-circuit wiring;
Forming a conductive film for forming a data line on the interlayer insulating film including a contact hole and a second contact hole; etching the conductive film into the data line shape by dry etching; Etching a portion below the second contact hole.

According to this structure of the present invention, by employing dry etching, the step of forming the data line and the step of cutting the short-circuit wiring can be performed continuously in the same processing chamber. Has the effect of being able to reduce. In addition, during the manufacturing process until the short-circuit wiring is formed and cut, the scanning lines are electrically connected by the short-circuit wiring. Therefore, even if, for example, static electricity is generated, the static electricity is dispersed by the short-circuit wiring. As a result, the occurrence of a short circuit between the scanning line and the semiconductor layer due to static electricity can be prevented. Therefore, it is possible to obtain a high-quality electro-optical device free from inter-wiring failure and electrostatic breakdown of a switching element having a semiconductor layer.

Also, a display pixel area in which a pixel electrode is formed at each intersection of the scanning line and the data line is provided on the substrate, and the display of the display pixel area is controlled, so that the scanning line is electrically connected to the display pixel area. And a driving circuit region in which a scanning line driving circuit to be electrically connected is formed, and the driving circuit region is formed simultaneously with the display pixel region.

With such a configuration, when the drive circuit region and the display pixel region are formed simultaneously on the same substrate, a period from when the short-circuit wiring is formed to when it is cut off, for example, static electricity or the like Even if the occurrence of the short circuit, the static electricity is dispersed by the short-circuit wiring, so that the TFT in the display pixel region is prevented from being destroyed and the TFT in the driving circuit region is also prevented from being destroyed. Having.

In the step of forming the scanning line and the short-circuiting line, the scanning line and the short-circuiting line are electrically connected to each other and arranged in the same layer as the scanning line and substantially in parallel with the scanning line. Forming the cutting hole, the forming the cutting hole includes forming a cutting hole between the adjacent scanning line and the capacitor line in the interlayer insulating film on the short-circuit wiring. The process is characterized in that According to such a configuration, even when forming the capacitance line, each capacitance line and each scanning line are electrically connected by the short-circuit wiring, so that the capacitance line due to static electricity or the like and the scanning line can be connected. A short circuit can be prevented, and a short circuit between the scan line or the capacitor line and the semiconductor layer can be prevented.

Further, the conductive film is made of a metal containing aluminum, and the dry etching is performed in a state where the data line-shaped resist layer is disposed on the conductive film. With such a configuration, a data line containing aluminum is formed by etching the conductive film using the resist layer as a mask, and a short circuit is formed using the cutting hole as a mask while the resist layer remains on the data line. The wiring is etched. That is, since the data line surface is protected by the resist layer when the short-circuit wiring is etched, the data line surface is not etched, and a data line having desired electrical characteristics can be obtained.

The conductive film is made of a metal containing aluminum, the short-circuit wiring is made of polysilicon, and in the dry etching, a mixed gas of chlorine gas and boron chloride gas is used as an etching gas. The etching of the conductive film and the etching of the short-circuit wiring are continuously performed by changing the flow ratio of the ion implantation and the RF power for drawing ions into the substrate. According to such a configuration, by changing the flow ratio of the mixed gas used as the etching gas and the RF power for ion attraction into the substrate, the etching of the conductive film and the etching of the short-circuit wiring can be continuously performed efficiently. Can be.

Further, the interlayer insulating film is made of a silicon oxide film, the conductive film is formed by sputtering, and the surface of the interlayer insulating film is etched by the dry etching. According to such a configuration, the deteriorated portion of the surface of the interlayer insulating film is etched, so that the interlayer insulating film and the insulating film formed thereon are connected for connection between the pixel electrode and the drain region of the semiconductor layer. When the contact hole described above is formed, the shape of the contact hole can be made good, thereby preventing the occurrence of a connection failure between the pixel electrode and the drain region.

Here, the alteration of the surface of the interlayer insulating film will be described. When a conductive film is formed by sputtering on an interlayer insulating film made of a silicon oxide film, the surface of the interlayer insulating film is deteriorated. An insulating film is further formed on the interlayer insulating film, and a contact hole is formed between the interlayer insulating film and the insulating film. However, the contact is made in a state where the deteriorated layer described above remains between the two insulating films. When the hole is formed, a step is generated and the shape of the contact hole may be defective. As a result, a connection failure between the pixel electrode and the drain region may occur.

An electro-optical device according to the present invention is manufactured by the above-described method for manufacturing an electro-optical device. This prevents a short circuit between wirings and the occurrence of TFT destruction during the manufacturing process, so that a high-quality electro-optical device with reduced short circuit defects can be obtained.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking a liquid crystal device as an electro-optical device as an example. In each figure, the scale is appropriately set for each configuration so that each configuration has a size recognizable on the drawings.

First, the structure of the liquid crystal device is shown in FIGS. 1 and 3 (4).
This will be described with reference to FIG. FIG. 1 is an equivalent circuit of various elements, wirings, and the like arranged on a TFT array substrate 10 constituting a liquid crystal device. FIG. 3D is a partially enlarged view of a circle A in FIG. 1 and is a view near a short-circuit wiring in a display pixel region. FIG. 4 is a cross-sectional view of the liquid crystal device corresponding to a section taken along line BB ′ of FIG.

As shown in FIG. 1, a TFT array substrate 10
The scanning line 3 and the data line 6 which intersect each other are arranged, the switching element 30 arranged at each intersection thereof, and the pixel electrode 9 electrically connected to the switching element 30 are arranged. It comprises a display pixel area and a drive circuit area for controlling the display of the display pixel area.

In the display pixel area, a capacitor line 3b is formed in the same layer as the scanning line 3 and is substantially parallel to the scanning line 3. Then, during the manufacturing process of the TFT array substrate, a short-circuit wire 90 surrounding the scanning line 3 and the capacitor line 3b and electrically connecting these wires is formed. This disconnects the electrical connection between the scanning lines. For details, see FIG.
As shown in (4), the short-circuit wiring 9 formed in a zigzag shape so as to electrically connect the scanning line 3 and the capacitance line 3b.
0 is cut at the cutting position 90a.

The driving circuit area includes a scanning line driving circuit 104,
It comprises a data line drive circuit 101, a sampling circuit 301, and a precharge circuit 201. Scan line drive circuit 104
Are electrically connected to the scanning lines 3 and the data line driving circuit 10
1 is electrically connected to the data line 6. The scanning line driving circuit 104 pulse-sequentially applies the scanning signals G1, G2,..., Gm to the scanning line 3 at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY, its inverted clock, and the like. Is applied. Data line drive circuit 101
Is a power supplied from an external control circuit, a reference clock C
A transfer signal from the shift register as a sampling circuit drive signal for each data line 6a in accordance with the timing at which the scan line drive circuit 104 applies the scan signals G1, G2,. X
, Xn are supplied to the sampling circuit 301 at a predetermined timing via the sampling circuit drive signal line 306. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6a.
, And a precharge circuit drive signal line 206 is connected to the gate electrode of the TFT 202.

As shown in FIG. 3D, the scanning line 3 and the data line 6 are arranged so as to intersect with each other.
A pixel electrode 9 (hatched portion) electrically connected to the TFT 30 is disposed. Further, a capacitor line 3b is formed in the same layer as the scanning line 3 and substantially in parallel with the scanning line 3, and the capacitor line 3b and the pixel electrode 9 are formed by using a first interlayer insulating film and a second interlayer insulating film described later as a dielectric film. Forming a storage capacitor. The scanning line 3 has a straight main line portion and a branch portion, and the branch portion functions as a gate electrode 3a. TFT
The region of the semiconductor layer 1 that constitutes 30 and overlaps with the gate electrode 3a is a channel region.

As shown in FIG. 4, the liquid crystal device 30 has a TF
A liquid crystal layer 50 is held between the T array substrate 10 and the counter substrate 20.

In the TFT array substrate 10, the semiconductor layer 1 is disposed on a substrate 60 such as a quartz substrate, and the gate insulating film 2 is disposed so as to cover the semiconductor layer 1. Gate insulating film 2
A plurality of scanning lines 3 and capacitance lines 3b are arranged above. The gate electrode 3a which is a part of the scanning line 3 is a semiconductor layer 1
On the channel region 1a. Further, a first interlayer insulating film 4 is arranged so as to cover the scanning lines 3 and the capacitor lines 3b, and a plurality of data lines 6 are arranged on the first interlayer insulating film 4. The data line 6 is electrically connected to the source region 1b of the semiconductor layer 1 via a contact hole 5 formed in the gate insulating film 2 and the first interlayer insulating film 4. On the second interlayer insulating film 7 including the data line 6, the pixel electrode 9 is formed, and further, the alignment film 16 is formed. Pixel electrode 9
Are electrically connected to the drain region 1c of the semiconductor layer 1 through contact holes 8 formed in the gate insulating film 2, the first interlayer insulating film 4, and the second interlayer insulating film 7. The storage line is formed in a region where the capacitor line 3b and the pixel electrode 9 overlap with the first interlayer insulating film 4 and the second interlayer insulating film 7 interposed therebetween.

On the other hand, the opposing substrate 20 is formed on a substrate 70 such as a glass substrate on a matrix-shaped light shielding layer 2 arranged along the scanning lines 3 and the data lines 6 on the TFT array substrate 10.
3 are arranged. Further, the substrate 70 including the light shielding layer 23
On top, a counter electrode 21 and an alignment film 22 are sequentially arranged.

Next, a method for manufacturing a liquid crystal device will be described.

First, a method for manufacturing the TFT array substrate 10 will be described with reference to FIGS. 2, 3, 5 and 6. Each drawing is a process drawing showing a manufacturing process. 2 and 3 are plan views of the short-circuit wiring and the display pixel area. FIG.
6 is a cross-sectional view of the short-circuit wiring and the display pixel region, and corresponds to a cross-section taken along line CC ′ in FIG.

First, as shown in FIG. 5A, a semiconductor layer 1 is formed on a quartz substrate 60. Specifically, the quartz substrate 6
Pressure CVD using monosilane gas, disilane gas or the like at a flow rate of about 400 to 600 cc / min in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C.
An amorphous silicon film is formed by (for example, CVD at a pressure of about 20 to 40 Pa). Thereafter, the polysilicon film is annealed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours, so that the polysilicon film has a thickness of about 50 to 200 nm, preferably about Solid phase growth is performed to a thickness of 100 nm. As a method for solid phase growth, laser annealing or the like may be used. After the formation of the polysilicon film, the semiconductor layer 1 is formed by patterning the polysilicon film by a photolithography process, an etching process, or the like. At this time, in plan view, FIG.
The semiconductor layer 1 is formed as shown in FIG.

Next, as shown in FIG.
And a gate insulating film 2 having a thickness of 50 to 120 nm is formed by PECVD using a mixed gas of TEOS (tetraethyl orthosilicate) and oxygen gas as a source gas. Here, SiH ₄ and oxygen gas may be used as the source gas.

Next, as shown in FIG. 5C, on the gate insulating film 2, a scanning line 3, a capacitance line (not shown), and a short-circuit wiring 90, each of which includes a gate electrode 3a, are formed of polysilicon. Form. Specifically, first, a polysilicon film is formed on the gate insulating film 2 by about 100 to 50
Deposited at a thickness of 0 nm, and thermally diffused phosphorus (P),
The polysilicon film is made conductive. Then, the polysilicon film is subjected to a photolithography process, an etching process, and the like to form scanning lines 3 having a predetermined pattern as shown in FIG.
A short-circuit line 90 for electrically connecting the capacitance line 3b, each scanning line 3 and the capacitance line 3b is formed. The gate electrode 3a is formed so as to overlap a part of the semiconductor layer 1. As shown in the figure, each scanning line 3 and capacitance line 3b are connected to a short-circuit wiring 9
Therefore, even if static electricity or the like occurs, for example, until the subsequent disconnection process of the short-circuit wiring, the static electricity is dispersed by the short-circuit wiring, and the scanning line and the capacitance due to the static electricity are dissipated. It is possible to prevent a short circuit between lines and a short circuit between the wiring and the semiconductor layer.

Thereafter, using the gate electrode 3a as a mask,
A dopant of a group V element such as P is doped at a high concentration, for example, P ions at a dose of 1 to 3 × 10 ¹⁵ / cm ² . Thus, the semiconductor layer 1 has the source region 1b and the drain region 1c formed on both sides of the channel region 1a. Due to the doping of the impurity, the capacitance line 3b, the scanning line 3, and the short-circuit line 90 are further reduced in resistance.

Next, as shown in FIG. 5 (4), the gate insulating film 2 is covered with TECVD as a source gas by PECVD so as to cover the scanning lines 3, the capacitance lines 3b and the short-circuit wiring 90.
1500 nm thick Si using OS and ozone gas
A first interlayer insulating film 4 made of O ₂ is formed.

Next, as shown in FIG. 5 (5), a first contact hole 5 for a data line 6 to be formed later is formed in the gate insulating film 2 and the first interlayer insulating film 4. In addition, the first portion of the portion corresponding to the mark x on the short-circuiting wire 90 shown in FIG.
A cutting hole 91 is formed in the interlayer insulating film 4.

Next, as shown in FIG. 5 (6), the gate insulating film 2 including the first contact hole 5 and the cutting hole 91 is formed.
On top, a film thickness of 200 to 600 nm by sputtering,
Here, a 400 nm aluminum film 6a is formed.
Further, a resist film 400 having a shape corresponding to the data line is formed on the aluminum film 6a.

Next, as shown in FIG. 5 (7), the data line is formed by etching the aluminum film 6a by dry etching and continuously using the resist film 400 as a mask in the same processing chamber. The short-circuit wiring 90 corresponding to the cutting hole 91 is etched through the hole 91, and the surface of the first interlayer insulating film 4 is further etched. As a result of the etching of the short-circuit wiring 90, the scanning lines and the capacitance lines are in a state where their electrical connections are disconnected.

This dry etching is performed in detail as follows. As an etching apparatus, an ICP (In) that independently supplies an RF (high frequency of about 13.56 MHz) power for generating plasma and an RF (high frequency of about 13.56 MHz) power for attracting ions to the substrate is used.
dudvery Coupled Plasma)
The system was used. As the etching gas, a chlorine-based mixed gas of chlorine gas (Cl ₂ ) and boron chloride gas (BCl ₃ ) is used. Then, by gradually changing the flow ratio of the mixed gas, the formation of the data line, the etching of the short-circuit wiring, and the etching of the surface of the first interlayer insulating film 4 are continuously performed.

First, a substrate is carried into an etching apparatus. Thereafter, the flow rate of chlorine gas (Cl ₂ ) is set to 6 in the processing chamber.
0 sccm, the flow rate of boron chloride gas (BCl ₃ ) is 20
A gas is introduced as sccm, and the aluminum film is etched to form a data line. At this time, the apparatus uses an RF power for plasma of 600 W (13.56 MHz) and an RF power of 120 W (1
5.36 MHz), and the pressure in the processing chamber is 1.1.
Pa and the temperature of the stage on which the substrate is placed are set to 70 ° C.

Next, the RF power for attracting ions to the substrate was changed to 150 W without changing the RF power for plasma.
(13.56 MHz). Further, the flow rate ratio of the mixed gas was changed to 70 sccm for the chlorine gas (Cl ₂ ) and 10 sccm for the boron chloride gas (BCl ₃ ), and etching was continued. As a result, the short-circuit wiring 90 mainly made of polysilicon is etched through the cutting holes 91. Further, the surface of the first interlayer insulating film 4 is also partially etched.

Next, the RF power for attracting ions to the substrate is set to 100 W without changing the RF power for plasma. Thereby, the surface of first interlayer insulating film 4 is mainly etched. Further, the short-circuit wiring 90 made of polysilicon is also etched through the cutting hole 91. Here, the etching of the surface of the first interlayer insulating film 4 is to remove the surface of the first interlayer insulating film 4 which has been altered by forming the aluminum film 6a on the first interlayer insulating film 4 by sputtering. Thereby, the shape of the second contact hole to be formed later can be improved.

As described above, in this embodiment, by employing dry etching, the aluminum film 6a is continuously etched in the same processing chamber to form data lines, and the data lines are formed through the cutting holes 91. The short-circuit wiring 90 corresponding to the cutting hole 91 can be etched, and further, the surface of the first interlayer insulating film 4 can be etched, so that the number of manufacturing steps can be reduced as compared with the case where the conventional process is performed in another step. it can. Further, at the time of dry etching, by appropriately setting the flow ratio of the etching gas and the RF power for drawing ions into the substrate, each film can be efficiently etched.

After that, the resist 400 is removed. FIG. 3 (3) is a plan view when formed through the above-described steps. As shown in FIG. 3, the data line 6 is formed, and the short-circuit wiring 90 is etched at the cutting position 90a. The connection between each scanning line and the capacitance line is electrically disconnected.

Next, as shown in FIG. 5 (8), a second interlayer insulating film 7 made of BPSG (a silicate glass film containing boron and phosphorus) is formed on the first interlayer insulating film 4 including the cutting holes 91. To form

Next, as shown in FIG. 6 (9), after a contact hole 8 for connecting a pixel electrode to be formed later is formed in the second interlayer insulating film 7, the contact hole 8 is formed on the second interlayer insulating film 7. Then, an ITO film 9a having a thickness of about 50 to 200 nm is formed by a sputtering method.

Thereafter, as shown in FIG.
The O film 9a is patterned through a photolithography process, an etching process, and the like to obtain the pixel electrode 9. FIG.
(4) is a plan view at this time. Thereafter, as shown in FIG. 4, a polyimide film is formed on the second interlayer insulating film 7 including the pixel electrode 9, and this is subjected to an alignment treatment to form an alignment film 16, whereby a TFT array substrate is manufactured.

On the other hand, the counter substrate 20 is formed as follows. First, on a substrate 70 such as a glass substrate, a light-shielding layer 23 made of a light-shielding metal such as Cr or a black resin is formed in a matrix in a region corresponding to the scanning lines 3 and the data lines 6 of the TFT array substrate 10. Next, the counter electrode 21 made of ITO is formed on the entire surface of the substrate 70 including the light shielding layer 23. After that, a polyimide film is formed on the counter electrode 21 and is subjected to an alignment treatment to form an alignment film 22.

The TFT array substrate 1 thus formed
The sealing material is applied to either one of the substrate 0 and the opposing substrate 20 along the outer edge of the substrate by a dispenser in a rectangular shape leaving one opening to be a liquid crystal injection port later. Thereafter, the two substrates are attached to each other, liquid crystal is injected into the gap between the substrates from an injection port, and the opening is sealed with a sealing material, whereby a liquid crystal device is completed.

As described above, in the present embodiment, the scanning lines and the capacitance lines are electrically connected by the short-circuit wiring. For example, even if static electricity or the like is generated, the static electricity is dispersed by the short-circuit wiring, which prevents a short circuit between the scanning line and the capacitor line due to the static electricity and a short circuit between the wiring and the semiconductor layer. it can.

In the case where the drive circuit area and the display pixel area are formed in the same manner, even if static electricity or the like is generated between the time when the short-circuit wiring is formed and the time when the short-circuit wiring is cut, the short-circuit Since the wiring disperses the static electricity, it is possible to prevent a short circuit between the TFT semiconductor and the wiring in the driving circuit area due to the static electricity and a short circuit between the wirings in the driving circuit area.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating an equivalent circuit such as various elements and wiring provided in a display pixel region and a drive circuit region of a liquid crystal device.

FIG. 2 is a plan view illustrating a manufacturing process (part 1) of a TFT array substrate of the liquid crystal device according to the embodiment.

FIG. 3 is a plan view illustrating a manufacturing process (part 2) of the TFT array substrate of the liquid crystal device in the embodiment.

FIG. 4 is a sectional view taken along line B-B ′ of FIG. 3 (4).

FIG. 5 is a cross-sectional view illustrating a manufacturing process (part 1) of the TFT array substrate of the liquid crystal device in the embodiment.

FIG. 6 is a cross-sectional view illustrating a manufacturing step (part 2) of the TFT array substrate of the liquid crystal device in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor layer 1a ... Channel region 1b ... Source region 1c ... Drain region 2 ... Gate insulating film 3 ... Scanning line 3b ... Capacitance line 4 ... First interlayer insulating film 5 ... First contact hole 6 ... Data line 7 ... Second Interlayer insulating film 9 ... Pixel electrode 10 ... TFT array substrate 40 ... Liquid crystal device 90 ... Short wiring 91 ... Cutting hole 104 ... Scan line drive circuit

Continued on the front page F term (reference) 2H092 GA29 JA24 JA34 JA37 JA41 JA46 JB22 JB31 JB67 KA04 KB25 MA05 MA07 MA13 MA18 MA19 MA29 MA30 NA14 NA16 NA27 PA01 5C094 AA43 AA60 BA03 BA43 CA19 HA10 5F004 AA16 BA20 CA02 DA04 DB11 DB30 DB02 EB01 EB02 5F110 AA16 AA26 AA27 BB02 CC02 DD03 EE09 EE45 FF02 FF30 GG02 GG13 GG24 GG25 GG47 HJ01 HJ04 HL03 HL23 NN03 NN04 NN22 NN23 NN35 NN72 PP03 PP10 PP13 QQ04 QQ11

Claims (7)

[Claims] A step of forming a semiconductor layer in which a source region and a drain region are arranged on a substrate with a channel region interposed therebetween; a step of forming a gate insulating film on the substrate so as to cover the semiconductor layer; Forming, on a gate insulating film, a plurality of scan lines partially corresponding to the channel region, and a short-circuit wire for electrically connecting each scan line in the same layer as the scan lines; Forming an interlayer insulating film on the gate insulating film so as to cover the short-circuit wiring; and forming a first contact hole at a position corresponding to the source region of the gate insulating film and the interlayer insulating film. Forming a second contact hole, which is a cutting hole, between adjacent scanning lines in the interlayer insulating film on the short-circuit wiring, and the first contact hole and the second contact hole. Forming a conductive film for forming a data line on the interlayer insulating film; etching the conductive film into the data line shape by dry etching; A method of manufacturing an electro-optical device, comprising: 2. A display pixel region in which a pixel electrode is formed at each intersection of the scanning line and the data line on the substrate, and a display of the display pixel region is controlled, so that the scanning line is electrically connected to the display pixel region. 2. An electro-optical device according to claim 1, wherein a driving circuit region in which a scanning line driving circuit to be electrically connected is formed, and the driving circuit region is formed simultaneously with the display pixel region. Manufacturing method. 3. In the step of forming the scanning line and the short-circuiting line, the scanning line and the short-circuiting line are electrically connected to each other and arranged in the same layer as the scanning line and substantially in parallel with the scanning line. Forming the cutting hole, forming the cutting hole between each adjacent scanning line and the capacitor line in the interlayer insulating film on the short-circuit wiring. The method of manufacturing an electro-optical device according to claim 1, wherein the process is performed. 4. The dry etching is performed in a state where the conductive film is made of a metal containing aluminum, and the data line-shaped resist layer is disposed on the conductive film. A method for manufacturing an electro-optical device according to any one of claims 1 to 3. 5. The conductive film is a metal containing aluminum,
The short-circuit wiring is made of polysilicon. In the dry etching, a mixed gas of chlorine gas and boron chloride gas is used as an etching gas, and etching and etching of the conductive film are performed by changing a flow ratio of the mixed gas. The method of manufacturing an electro-optical device according to claim 1, wherein the etching of the short-circuit wiring is performed continuously. 6. The electric device according to claim 5, wherein the interlayer insulating film is made of a silicon oxide film, the conductive film is formed by sputtering, and the surface of the interlayer insulating film is etched by the dry etching. A method for manufacturing an optical device. 7. An electro-optical device manufactured by the method of manufacturing an electro-optical device according to claim 1.