JPH0514205A - Data compression control circuit - Google Patents

Abstract

PURPOSE:To operate a data compression at a further high speed by making an apparent sampling frequency high. CONSTITUTION:The same 8 bit data are inputted to two DPCM encoders 12 and 14 whose constitutions are the same. A sampling clock is 1/2 frequency- divided by a frequency division circuit 16, and inputted to the DPCM encoders 12 and 14 so that the 8 bit data can alternately be data latched by the DPCM encoders 12 and 14. Then, a selector which receives the 1/2 frequency-divided sampling clock, alternately selects and outputs 4 bit data outputted from the DPCM encoders 12 and 14. Thus, the sampling frequency can apparently be doubled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression control circuit, and more particularly, it is used for a VTR having a function of digitally processing an image using an image memory and displaying a digital image by the digital processing on a monitor. The present invention relates to a data compression control circuit.

[0002]

2. Description of the Related Art Conventionally, many data compression techniques have been proposed, and the applicant of the present application has proposed a new differential encoding circuit in Japanese Patent Application No. 2-142220 filed on May 31, 1990. . The proposed technique is a technique for converting 8-bit image data into 4-bit and storing the image data in the image memory, and compressing the data to halve the image memory.

[0003]

However, since this differential encoding circuit includes many arithmetic circuits, processing such as arithmetic operations is performed until input 8-bit data is converted into 4-bit data and output. It took some time to get there. Since this time is fixed by hardware, there is a problem that data conversion cannot be performed when processing is required in a time shorter than this time, that is, when sampling is performed at a higher sampling frequency. there were.

Therefore, a main object of the present invention is to provide a data compression control circuit capable of processing data at a higher speed.

[0005]

A first invention is a plurality of DPCM encoders that receive the same data, and a plurality of DPCM encoders.
Data comprising a dividing means for dividing a sample clock according to the number of encoders and giving it to each DPCM encoder, and a selecting means for selecting output data from a plurality of DPCM encoders in response to outputs of the dividing means. It is a compression control circuit.

According to a second aspect of the invention, a plurality of DPCM decoders for receiving the same data, a frequency dividing means for dividing the sample clock according to the number of the plurality of DPCM decoders and giving it to each DPCM decoder, and an output of the frequency dividing means. Is a data compression control circuit including selection means for selecting output data from a plurality of DPCM decoders in response to the above.

[0007]

In the first aspect of the invention, a plurality of DPCM encoders are provided, each of which encodes, for example, 8-bit data into 4-bit data at a predetermined speed. And
Depending on the number of DPCM encoders, the sampler is divided by the frequency dividing means (1 if the number of DPCM encoders is n).
/ N). Input data is sequentially input to each DPCM encoder in response to the output of the frequency dividing means.
The sample clock divided by the dividing means is also given to the selecting means, and in response to the sample clock, the selecting means sequentially selects and outputs the data output from the plurality of DPCM encoders. This makes it possible to increase the apparent sampling frequency.

In the second invention, a plurality of DPCM decoders each capable of decoding, for example, 4-bit data into 8-bit data at a predetermined speed are provided. Then, the frequency dividing means sets the sample clock according to the number of DPCM decoders (1 if the number of DPCM decoders is n).
/ N). Input data is sequentially input to each DPCM decoder in response to the output of the frequency dividing means. The sample clock divided by the dividing means is also given to the selecting means, and in response to this sample clock, the selecting means sequentially selects and outputs the data output from the plurality of DPCM decoders. This makes it possible to increase the apparent sampling frequency.

[0009]

According to the present invention, since the apparent sampling frequency can be increased, data can be encoded or decoded at higher speed. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

1 and 2, the data compression control circuit 10 of this embodiment is an encoder circuit 10 shown in FIG.
a and the decoder circuit 10b shown in FIG. The encoder circuit 10a shown in FIG. 1 has two DPCM (Differe
ntial Pulse Code Modulation) encoders 12 and 1
Including 4. Known DPCM encoders as shown in FIG. 3 are used as the DPCM encoders 12 and 14. The details of the DPCM encoders 12 and 14 are well known and therefore omitted here.
The PCM encoders 12 and 14 have a function of converting input 8-bit data into 4-bit data.
The same 8-bit data is input to the two DPCM encoders 12 and 14. Further, the frequency divider circuit 16 divides the sample clock having a predetermined frequency by 1/2. Then, the sample clock divided by ½ is input to the DPCM encoders 12 and 14 so that the same input data is alternately latched in the DPCM encoders 12 and 14. That is, the non-inverted output of the D-FF forming the frequency dividing circuit 16 is given as the clock of the DPCM encoder 12, and its inverted output is given as the clock of the DPCM encoder 14.

Then, the DPCM encoders 12 and 1
The encoded data converted into 4 bits is output from each of 4 and input to the selector 18. Selector 1
Further, a sample clock divided by 1/2 by the frequency dividing circuit 16, that is, a non-inverted output and an inverted output of the D-FF is applied to 8. Therefore, when the DPCM encoder 12 is encoding in response to the inverted output from the D-FF, the encoded data from the DPCM encoder 12 is selected, and the DPCM encoder 14 is encoding in response to the non-inverted output. Is DPCM encoder 1
The encoded data from 4 is selected. That is, the DPCM encoder 12 side and the DPCM encoder 14 side are alternately selected or enabled by the output of the frequency dividing circuit 16 that divides the sample clock by 1/2.

In such an encoder circuit 10a, if the cycle of the sample clock is the time t ₃ shown in FIG. 5, the cycle of the clock given to the frequency dividing circuit 16 and the selector 18 is the times t ₁ and t ₂ . However, t ₁
= T ₂ = 2 · t ₃ . If the DPCM encoder 12 side is activated at the timing shown by the solid line in FIG. 5 and the DPCM encoder 14 side is activated at the timing shown by the dotted line, the selector 18 outputs the encoded data at both the solid line and dotted line timings in FIG. Will be output. Therefore, each DPCM encoder 12 and 1
Even if 4 can respond only to 15 MHz, for example, it can be sampled at 30 MHz, and the frequency of the apparent sample clock can be increased.

For example, if the delay of the basic cell of the IC is 1.2 nanoseconds, it takes 40 nanoseconds from the data IN to the data OUT in the DPCM encoder shown in FIG.
Considering temperature conditions, power supply fluctuations, etc., it is necessary to suppress the IC to 35 nanoseconds or less. Therefore, although the required design cannot be performed as it is, the design condition can be satisfied by using the embodiment of FIG.

The decoder circuit 10b shown in FIG. 2 includes two DPCM decoders 20 and 22. This DPCM
As the decoders 20 and 22, known DPCM decoders as shown in FIG. 4 are used. The details of the DPCM decoders 20 and 22 are already well known and therefore omitted here, but the DPCM decoders 20 and 22 are omitted.
Has a function of converting input 4-bit data into 8-bit data. Then, the same 4-bit data is input to the DPCM decoders 20 and 22. Further, the frequency divider circuit 24 divides the sample clock having a predetermined frequency by 1/2. Then, the sample clock divided by ½ has a DPCM so that the same input data is alternately latched by the DPCM decoders 20 and 22.
It is input to the decoders 20 and 22. That is, the non-inverted output of the D-FF forming the frequency dividing circuit 24 is given as the clock of the DPCM decoder 20, and its inverted output is given as the clock of the DPCM decoder 22.

Then, the DPCM decoders 20 and 22
The decoded data converted into 8-bit data is output from each of the input terminals and input to the selector 26. The selector 26 is further supplied with the sample clock divided by 1/2 by the frequency dividing circuit 24, that is, the non-inverted output and the inverted output of the D-FF. Therefore, when the DPCM decoder 20 is decoding in response to the inverted output from the D-FF, the decoded data from the DPCM decoder 20 is selected, and the DPCM decoder 22 is decoding in response to the non-inverted output. The decoded data from the DPCM decoder 22 is selected. That is, set the sample clock to 1
The DPCM decoder 20 side and the DPCM decoder 22 side are alternately selected or validated by the output of the frequency dividing circuit 24 that divides the frequency by 1/2.

Such a decoder circuit 10b also operates on Saturdays and can be expected to have the same effect as the encoder circuit 10a shown in FIG. 1, but since it is repeated here, it will be omitted. Data compression control circuit 10 of this embodiment
When storing a still image in the image memory, for example, it is used as a means for compressing the image data of the still image and storing the compressed image data in the image memory to reduce the use area of the image memory. In this case, the encoder circuit 10a functions as a data compression circuit, and the decoder circuit 10b functions as a data decompression circuit. Then, the encoder circuit 10
The 4-bit data encoded in a is stored in the image memory, and the 4-bit data read from the image memory is decoded by the decoder circuit 10b. At this time, DPC
It is necessary to adjust the timing so that the data output from the M encoder 12 is input to the DPCM decoder 20 and the data output from the DPCM encoder 14 is input to the DPCM decoder 22. If this is reversed, the still image will be distorted.

It should be noted that this embodiment can be applied to improve the image quality of a still image stored in the image memory by increasing the density of the sample data. That is, the DPCM encoder 12 in the data compression control circuit 10
And 14 and DPCM decoders 20 and 22 are capable of processing within the required sampling time, or if the required sampling period is originally long, it is not necessary to use this embodiment, but the embodiment is used. In this case, the data quality can be improved because the data can be doubled.

Although two DPCM encoders and two DPCM decoders are used in the above embodiment, three or more (n) DPCM encoders and three DPCM decoders may be used. in this case,
It is necessary to divide the sample clock by 1 / n and synchronize the DPCM encoder and DPCM decoder with the selector.

[Brief description of drawings]

FIG. 1 is a block diagram showing an encoder circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a decoder according to an embodiment of the present invention.

3 is a block diagram showing the DPCM encoder shown in FIG. 1. FIG.

4 is a block diagram showing the DPCM decoder shown in FIG. 2. FIG.

FIG. 5 is an illustrative view showing sampling timing.

[Explanation of symbols]

10 ... Data compression control circuit 10a ... Encoder circuit 10b ... Decoder circuit 12, 14 ... DPCM encoder 16, 24 ... Divider circuit 18, 26 ... Selector 20, 22 ... DPCM decoder

Claims (2)

[Claims] 1. A plurality of DPCM encoders for receiving the same data, a frequency dividing means for dividing a sample clock according to the number of the plurality of DPCM encoders, and giving the divided clocks to the respective DPCM encoders, and an output of the frequency dividing means. A data compression control circuit, comprising a selection unit that responds to select output data from the plurality of DPCM encoders. 2. A plurality of DPCM decoders for receiving the same data, frequency dividing means for dividing a sample clock according to the number of the plurality of DPCM decoders and giving it to each of the DPCM decoders, and an output of the frequency dividing means. A data compression control circuit comprising a selection means for responding to select the output data from the plurality of DPCM decoders.