JPH0513961A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPH0513961A
JPH0513961A JP3158273A JP15827391A JPH0513961A JP H0513961 A JPH0513961 A JP H0513961A JP 3158273 A JP3158273 A JP 3158273A JP 15827391 A JP15827391 A JP 15827391A JP H0513961 A JPH0513961 A JP H0513961A
Authority
JP
Japan
Prior art keywords
wiring board
power supply
multilayer wiring
layer
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3158273A
Other languages
Japanese (ja)
Inventor
Kenichi Matsumura
健一 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3158273A priority Critical patent/JPH0513961A/en
Publication of JPH0513961A publication Critical patent/JPH0513961A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To prevent a multilayer wiring board from generating power supply noises to a semiconductor device or the like even if the board is not mounted with an additional capacitor component and to enable the multilayer wiring board to be enhanced in both wiring density and component mounting density and lessened in number of components. CONSTITUTION:A circular or polygonal hole having a diameter of 2r1 is bored in an insulating layer 7 whose permittivity is epsilon1 penetrating through it, a dielectric body layer 8 of a permittivity of epsilon2 is provided fitting in the hole concerned and fixed with hardening dielectric resin or the like, where epsilon is so set as to satisfy a formula, epsilon<epsilon. As mentioned above, a power supply conductor layer (conductor pattern) is formed on both the sides of an integral structure where the dielectric layer 8 and the insulating layer 7 are formed into one piece. By this setup, a capacitor part whose capacitance C is as large as epsilon2epsilon0 (pir1<2>/d1) is formed, so that a multilayer wiring board of this design is adequate to be used as a multilayer wiring board provided with a power supply noise preventing function.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多層配線板に係り、特に
電源ノイズ防止のためのコンデンサ機能を具備した多層
配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board having a capacitor function for preventing power source noise.

【0002】[0002]

【従来の技術】近年、IC素子などの半導体装置を、配
線板に実装して成る実装回路装置においては、電源から
のノイズを吸収する手段として、コンデンサを利用する
ことが一般に知られている。図3および図4は、電源ノ
イズ防止用コンデンサの実装例をそれぞれ斜視的に示し
たもので、これらの図において、1は導体パターン層
(導体層)および絶縁層を交互に積層してなる多層配線
板、2はその一主面上に搭載され実装されているICパ
ッケージのような半導体装置である。そして、この多層
配線板1の前記実装された半導体装置2の近くのには、
電源ノイズ防止用のコンデンサ3部品が搭載されてお
り、このコンデンサ3のリード線4a、4bは、多層配線板
1に内層配置されている異なる電位を有する電源供給導
体層5、6にそれぞれ接続されている。
2. Description of the Related Art In recent years, it has been generally known to use a capacitor as a means for absorbing noise from a power source in a mounted circuit device in which a semiconductor device such as an IC element is mounted on a wiring board. 3 and 4 are perspective views showing mounting examples of the power supply noise prevention capacitor. In these figures, 1 is a multilayer in which conductor pattern layers (conductor layers) and insulating layers are alternately laminated. The wiring board 2 is a semiconductor device such as an IC package mounted and mounted on one main surface thereof. And, in the vicinity of the mounted semiconductor device 2 of the multilayer wiring board 1,
A capacitor 3 component for preventing power supply noise is mounted, and lead wires 4a and 4b of the capacitor 3 are connected to power supply conductor layers 5 and 6 having different potentials which are arranged in inner layers of the multilayer wiring board 1, respectively. ing.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記構
成の電源ノイズ防止構造においては、前記電源ノイズ防
止用コンデンサ3の搭載によって、多層配線板1面に電
子部品を搭載・実装し得る領域および配線パターン(導
体層)の形成可能な領域が規制を受けることになり、高
密度実装化ないし実装回路装置のコンパクト化が損なわ
れるという問題がある。つまり、高密度実装化ないし実
装回路装置のコンパクト化を図ろうとすると、逆に電源
ノイズ防止用コンデンサ3の搭載・配置領域が大幅に制
約されるばかりでなく、異なる電位を有する電源供給導
体層5、6への接続も複雑で繁雑な構成とならざるを得
ない。
However, in the power supply noise prevention structure having the above-mentioned structure, by mounting the power supply noise prevention capacitor 3, a region and a wiring pattern in which electronic parts can be mounted and mounted on the surface of the multilayer wiring board 1 There is a problem that the area where the (conductor layer) can be formed is regulated, which impairs high-density mounting or downsizing of a mounted circuit device. That is, when attempting to achieve high-density mounting or downsizing of a mounted circuit device, conversely, not only the mounting / arrangement area of the power supply noise prevention capacitor 3 is significantly restricted, but also the power supply conductor layer 5 having different potentials. , 6 is inevitably complicated and complicated.

【0004】本発明はこのような問題を解決するために
なされたもので、配線の高密度化と電子部品の高密度実
装化、ならびに電子部品点数の削減を実現することがで
き、したがって実装回路装置の小形化も可能な多層配線
板の提供を目的とする。
The present invention has been made in order to solve such a problem, and it is possible to realize high density wiring, high density mounting of electronic parts, and reduction of the number of electronic parts, and therefore a mounting circuit. It is an object of the present invention to provide a multilayer wiring board that can be downsized.

【0005】[0005]

【課題を解決するための手段】本発明に係る多層配線板
は、絶縁層を介して導体層を積層してなる多層配線板に
おいて、 前記導体層のうちで隣接する電位の異なる2
つの電源供給導体層間の絶縁層の所定領域をこの絶縁層
の誘電率以上の誘電率を有する誘電体で選択的に構成
し、2つの電源供給導体層間にコンデンサとして機能す
る部分を形成して成ることを特徴とする。
A multi-layer wiring board according to the present invention is a multi-layer wiring board in which conductor layers are laminated with an insulating layer interposed between adjacent conductor layers having different potentials.
A predetermined region of an insulating layer between two power supply conductor layers is selectively configured by a dielectric having a dielectric constant higher than that of the insulating layer, and a portion functioning as a capacitor is formed between the two power supply conductor layers. It is characterized by

【0006】[0006]

【作用】上記した多層配線板においては、電位の異なる
電源供給用導体(パターン)層間の絶縁層の所定領域
が、その誘電率以上の誘電率を有する誘電体で選択的に
置換された構成を成している。そして、前記選択的に置
換された誘電体領域が、前記2つの電源供給用導体パタ
ーン層間にコンデンサとしての機能を有する部分を形成
することになり、もって電源からのノイズ防止に効果的
に機能する。したがって、多層配線板主面に、格別に電
源ノイズ防止用コンデンサを搭載・実装する必要がなく
なり、配線板表面を有効に活用し電子部品および配線の
高密度化を実現することができる。
In the above-mentioned multilayer wiring board, a predetermined region of the insulating layer between the power supply conductors (patterns) having different potentials is selectively replaced with a dielectric having a dielectric constant higher than the dielectric constant. Is made. Then, the selectively replaced dielectric region forms a portion having a function as a capacitor between the two power supply conductor pattern layers, and thus effectively functions to prevent noise from the power supply. .. Therefore, it is not necessary to specifically mount and mount a power supply noise preventing capacitor on the main surface of the multilayer wiring board, and it is possible to effectively utilize the surface of the wiring board and achieve high density of electronic components and wiring.

【0007】[0007]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0008】図1は、本発明に係る多層配線板の要部構
成例を断面的に示すもので、内層を成す電源供給導体層
5、6間に介在させた絶縁層7の一部(所定領域)を、
前記絶縁層7の誘電率以上の誘電率を有するに誘電体8
で置換(埋め込み)した構成を成している。すなわち、
本発明に係る多層配線板は、電源供給導体層5、6間に
介在させた誘電率ε1 の絶縁体からなる厚さがd1の内
層絶縁層7の一部を、前記内層絶縁層7の誘電率ε1
りもはるかに大きな誘電率ε2 を有する誘電体の8で置
き換えたことをその構成の骨子としている。
FIG. 1 is a cross-sectional view showing an example of the essential structure of a multilayer wiring board according to the present invention. A part of an insulating layer 7 interposed between power supply conductor layers 5 and 6 forming an inner layer (predetermined). Area)
A dielectric 8 having a dielectric constant higher than that of the insulating layer 7
It is configured by replacing (embedding) with. That is,
In the multilayer wiring board according to the present invention, a part of the inner insulating layer 7 having a thickness of d 1 and made of an insulating material having a dielectric constant ε 1 interposed between the power supply conductor layers 5 and 6 is used. It is the essence of the configuration that it is replaced with 8 of a dielectric having a dielectric constant ε 2 much larger than the dielectric constant ε 1 of .

【0009】そして、このような構成を成す多層配線板
は、次のようにして容易に製造・構成し得る。すなわ
ち、支持基体面上に第1の電源供給導体層(パターン)
5を形成した後、この第1の電源供給導体層(パター
ン)5面上に誘電率ε1 の絶縁層7を形成する。次い
で、前記形成した絶縁層7の所定領域に、第1の電源供
給導体層(パターン)5面に達する直径2r1 の円形ま
たは多角形の孔を明け、この孔に誘電率ε2 の誘電体8
を挿嵌・充填し、誘電性の硬化性樹脂などにより固定す
る。しかる後、前記誘電体層8および絶縁層7を一体化
した面上に、第2の電源供給導体層(パターン)6を被
着形成する。なお、この構成において、誘電体層8およ
び絶縁層7を一体化した後、その両面に、それぞれ銅箔
を重ね誘電性の硬化性樹脂により貼着し、いわゆるフォ
トエッチング処理して電源供給用の導体パターン5、6
を形成してもよい。
The multilayer wiring board having such a structure can be easily manufactured and constructed as follows. That is, the first power supply conductor layer (pattern) is formed on the surface of the supporting substrate.
After forming 5, the insulating layer 7 having a dielectric constant ε 1 is formed on the surface of the first power supply conductor layer (pattern) 5. Next, a circular or polygonal hole having a diameter 2r 1 reaching the surface of the first power supply conductor layer (pattern) 5 is made in a predetermined region of the formed insulating layer 7, and a dielectric material having a dielectric constant ε 2 is formed in this hole. 8
Insert and fill, and fix with a dielectric curable resin. After that, a second power supply conductor layer (pattern) 6 is deposited on the surface where the dielectric layer 8 and the insulating layer 7 are integrated. In this structure, after the dielectric layer 8 and the insulating layer 7 are integrated, copper foils are laminated on both surfaces of the dielectric layer 8 and the insulating layer 7 with a dielectric curable resin, and a so-called photo-etching process is performed to supply power. Conductor pattern 5, 6
May be formed.

【0010】上記により所要の電源ノイズ防止用コンデ
ンサ機能領域を形成した後は、要すればさらに絶縁層、
導体層(パターン層)を、常套の手段にしたがって順次
積層的に形成することによって、所要の多層配線板が得
られる。
After forming the required power supply noise preventing capacitor functional area as described above, if necessary, further insulating layer,
A required multilayer wiring board can be obtained by sequentially forming the conductor layers (pattern layers) in a laminated manner by a conventional method.

【0011】このように形成された多層配線板において
は、2つの電源供給用パターン層5、6およびこの電源
供給用パターン層5、6間に挟持ないし配置されたたと
えば円柱状の誘電体層8(直径2r1 、誘電率ε2 )に
より、容量C=ε2 ε0 ( πr1 2 /d1 ) (ここでε
0 は真空誘電率、πは円周率である。)をもつコンデン
サ部が形成される。実際に絶縁層7を厚さ0.5mmのプリ
プレグ(誘電率ε1 48)とし、誘電体として誘電率ε2
が1200のセラミックを使用して直径10.0mmのセラミック
の円柱体を前記プリプレグに埋設・配置した構成の場
合、容量が0.01μF のコンデンサが形成された。
In the multilayer wiring board thus formed, two power supply pattern layers 5 and 6 and, for example, a columnar dielectric layer 8 sandwiched or arranged between the power supply pattern layers 5 and 6 are provided. From (diameter 2r 1 , dielectric constant ε 2 ), the capacitance C = ε 2 ε 0 (πr 1 2 / d 1 ) (where ε
0 is the vacuum permittivity and π is the circular constant. ) Is formed. And actually the thickness 0.5mm prepreg insulating layer 7 (dielectric constant epsilon 1 48), the dielectric constant epsilon 2 as dielectric
In the case where a ceramic columnar body having a diameter of 10.0 mm is embedded and arranged in the prepreg using 1200 ceramics, a capacitor having a capacitance of 0.01 μF was formed.

【0012】このように構成される内層電源供給部の両
面に、それぞれプリプレグを介して外層銅箔を積層する
ことにより多層配線板が得られるが、多層配線板におい
ては、内層部にコンデンサとしての機能を有する部分が
内蔵されているので、コンデンサ部品を別に搭載しなく
ても、ノイズのない安定した電気信号を半導体装置に供
給することができる。そのため、配線板上の配線可能な
領域の面積が増大し、配線密度を上げることができる。
さらに、部品点数も削減されるため、他の部品の集積度
を従来より上げることができる。
A multilayer wiring board can be obtained by laminating outer layer copper foils on both surfaces of the inner layer power supply section thus configured through prepregs. In the multilayer wiring board, the inner layer section serves as a capacitor. Since the portion having the function is built in, a stable electric signal without noise can be supplied to the semiconductor device without separately mounting a capacitor component. Therefore, the area of the area where wiring is possible on the wiring board is increased, and the wiring density can be increased.
Further, since the number of parts is also reduced, the degree of integration of other parts can be increased as compared with the conventional one.

【0013】次に、図2を参照して本発明の他の実施例
を説明する。図2は要部構成例を斜視的に示したもの
で、9は誘電率ε3 の絶縁体からなる厚さがd2 の絶縁
層、10、11は前記絶縁層9の両面にそれぞれ貼着配置さ
れた電源供給導体層である。ここでは、電源供給導体層
10、11は、いずれも銅箔からなり、一方の電源供給導体
層10にはスリット状の切欠部12が所定の間隔r2 をおい
て一定の方向に設けられている。また、他方の電源供給
導体層11には、スリット状の切欠部12が同じ間隔r2
前記切欠部12に対して直交するように設けられいる。
Next, another embodiment of the present invention will be described with reference to FIG. FIG. 2 is a perspective view showing an example of the essential structure, in which 9 is an insulating layer made of an insulating material having a permittivity ε 3 and having a thickness of d 2 , and 10 and 11 are attached to both surfaces of the insulating layer 9, respectively. It is a power supply conductor layer arranged. Here, the power supply conductor layer
Both 10 and 11 are made of copper foil, and one power supply conductor layer 10 is provided with slit-shaped notches 12 in a certain direction at a predetermined interval r 2 . Further, the other power supply conductor layer 11 is provided with slit-shaped notches 12 so as to be orthogonal to the notches 12 at the same interval r 2 .

【0014】この構成においては、絶縁層9(厚さ
2 、誘電率ε3 )のうちで、上下両面から銅箔からな
る電源供給導体層10、11で挟持されている(電源供給導
体層10、11間に介在する)部分が、それぞれ容量C=ε
3 ε0 ( r2 2/d2 ) をもつコンデンサとしての機能
を有することになる。
In this structure, the insulating layer 9 (thickness d 2 , dielectric constant ε 3 ) is sandwiched by the power supply conductor layers 10 and 11 made of copper foil from both upper and lower sides (power supply conductor layer). (Interposed between 10 and 11) is the capacitance C = ε
It has a function as a capacitor having 3 ε 0 (r 2 2 / d 2 ).

【0015】したがって、内層電源供給導体層10、11の
面上にそれぞれプリプレグを介して外層銅箔を積層して
得られた多層配線板においては、配線密度を上げ部品点
数を削減することができる。さらに、前記実施例の多層
配線板に比べて、絶縁層9に別途他の誘電体を選択的に
配置・挿入する手間が省け製造が容易であるうえに、誘
電率のより小さい誘電体を使用して電源ノイズを防止す
る効果を挙げることができるという利点がある。
Therefore, in the multilayer wiring board obtained by laminating the outer layer copper foils on the surfaces of the inner layer power supply conductor layers 10 and 11 via the prepregs respectively, the wiring density can be increased and the number of parts can be reduced. .. Further, as compared with the multilayer wiring board of the above-described embodiment, it is possible to save the labor of separately disposing and inserting another dielectric in the insulating layer 9 and to facilitate the manufacturing, and to use the dielectric having a smaller dielectric constant. Therefore, there is an advantage that the effect of preventing power source noise can be achieved.

【0016】[0016]

【発明の効果】以上説明したように本発明に係る多層配
線板によれば、半導体装置などの実装面から電源ノイズ
防止用のコンデンサ部品を取り除くことができる。その
ため、配線の高密度化および部品点数の削減を実現する
ことができる。また、従来はコンデンサ部品が搭載され
ていた領域に他の部品を搭載することができるうえに、
基板サイズをより小形化することができる。
As described above, according to the multilayer wiring board of the present invention, the capacitor component for preventing power source noise can be removed from the mounting surface of a semiconductor device or the like. Therefore, it is possible to realize high density wiring and reduce the number of parts. In addition to being able to mount other parts in the area where capacitor parts were conventionally mounted,
The substrate size can be made smaller.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る多層配線板の要部構成例を示す断
面図。
FIG. 1 is a cross-sectional view showing a configuration example of a main part of a multilayer wiring board according to the present invention.

【図2】本発明の別の要部構成例を示す斜視図。FIG. 2 is a perspective view showing another configuration example of the main part of the present invention.

【図3】従来の電源ノイズ防止コンデンサを付設した実
装回路装置の構成を示す斜視図。
FIG. 3 is a perspective view showing a configuration of a conventional mounted circuit device provided with a power supply noise prevention capacitor.

【図4】従来の電源ノイズ防止コンデンサを付設した実
装回路装置の構成を示す一部断面図。
FIG. 4 is a partial cross-sectional view showing a configuration of a conventional mounted circuit device provided with a power supply noise prevention capacitor.

【符号の説明】[Explanation of symbols]

1…多層配線板 2…半導体装置 3…コンデンサ
4a、4b…コンデンサのリード線 5、6、10、11
…電源供給導体層 7、9…絶縁層 8…誘電体層
12…切欠部
1 ... Multilayer wiring board 2 ... Semiconductor device 3 ... Capacitor
4a, 4b ... Capacitor lead wires 5, 6, 10, 11
... Power supply conductor layers 7, 9 ... Insulating layer 8 ... Dielectric layer
12 ... Notch

Claims (1)

【特許請求の範囲】 【請求項1】 絶縁層を介して導体層を積層してなる多
層配線板において、前記導体層のうちで隣接する電位の
異なる2つの電源供給導体層間の絶縁層の所定領域をこ
の絶縁層の誘電率以上の誘電率を有する誘電体で選択的
に構成し、2つの電源供給導体層間にコンデンサとして
機能する部分を形成して成ることを特徴とする多層配線
板。
Claim: What is claimed is: 1. In a multilayer wiring board in which conductor layers are laminated with an insulating layer interposed therebetween, a predetermined insulating layer between two adjacent power supply conductor layers having different potentials in the conductor layers. A multilayer wiring board characterized in that a region is selectively constituted by a dielectric having a dielectric constant higher than that of the insulating layer, and a portion functioning as a capacitor is formed between two power supply conductor layers.
JP3158273A 1991-06-28 1991-06-28 Multilayer wiring board Withdrawn JPH0513961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3158273A JPH0513961A (en) 1991-06-28 1991-06-28 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3158273A JPH0513961A (en) 1991-06-28 1991-06-28 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH0513961A true JPH0513961A (en) 1993-01-22

Family

ID=15668005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3158273A Withdrawn JPH0513961A (en) 1991-06-28 1991-06-28 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH0513961A (en)

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JPH08204341A (en) * 1995-01-27 1996-08-09 Nec Corp Printed board built-in type bypass capacitor
JP2006237314A (en) * 2005-02-25 2006-09-07 Matsushita Electric Ind Co Ltd Wiring board with built-in capacitors and manufacturing method thereof
US7312289B2 (en) 2003-03-03 2007-12-25 Unimatec Co., Ltd. Fluorine-containing elastomer and its composition
WO2019156175A1 (en) 2018-02-08 2019-08-15 ダイキン工業株式会社 Method for manufacturing fluoropolymer, surfactant for polymerization, use for surfactant, and composition
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